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| september 2013 doc id 14629 rev 8 1/904 RM0017 reference manual spc560b40x, spc560b50x, spc560c40x, spc560c50x 32-bit mcu family built on the embedded power architecture ? introduction the spc560bx and spc560cx is a new family of next generation microcontrollers built on the power architecture ? embedded category. this document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the device. the spc560bx and spc560cx family of 32-bit microcontrollers is the latest achievement in integrated automotive body application controllers. it belongs to an expanding family of automotive-focused products designed to address the next wave of body electronics applications within the vehicle. the advanced a nd cost-efficient host processor core of the spc560bx and spc560cx automotive controller family complies with the power architecture embedded category, which is 100 percent user-mode compatible with the original power architecture technology. it operates at speeds of up to 64 mhz and offers high performance processing optimized for low power consumption. it capitalizes on the available development infrastructure of current power architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations. www.st.com
RM0017 contents doc id 14629 rev 8 2/904 contents 1 preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 1.2 audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 1.3 guide to this reference manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 1.4 register description conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 1.5 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 1.6 how to use the spc560bx and spc560cx documents . . . . . . . . . . . . . 41 1.6.1 the spc560bx and spc560cx document set . . . . . . . . . . . . . . . . . . . 41 1.6.2 reference manual content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 1.7 using the spc560bx and spc560cx . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 1.7.1 hardware design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 1.7.2 input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 1.7.3 software design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 1.7.4 other features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.1 the spc560bx and spc560cx microcontroller family . . . . . . . . . . . . . . 46 2.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.2.1 spc560bx and spc560cx family comparison . . . . . . . . . . . . . . . . . . . 46 2.2.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.2.3 chip-level features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2.3 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.4 developer support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.2 package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.3 pad configuration during reset phases . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.4 voltage supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.5 pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.6 system pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 contents RM0017 3/904 doc id 14629 rev 8 4.7 functional ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.8 nexus 2+ pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5 microcontroller boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.1 boot mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.1.1 flash memory boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.1.2 serial boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.1.3 censorship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.2 boot assist module (bam) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 5.2.1 bam software flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 5.2.2 linflex (rs232) boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.2.3 flexcan boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 5.3 system status and configuration module (sscm) . . . . . . . . . . . . . . . . . 98 5.3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.3.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.3.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.3.4 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . 99 6 clock description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 6.1 clock architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 6.2 clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6.3 fast external crystal oscillator (fxosc) digital interface . . . . . . . . . . . . 108 6.3.1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.3.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.3.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6.4 slow external crystal oscillator (sxosc) digital interface . . . . . . . . . . . 110 6.4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 6.4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 6.4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 6.4.4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 6.5 slow internal rc oscillator (sirc) digital interface . . . . . . . . . . . . . . . . 112 6.5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 6.5.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 6.5.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 6.6 fast internal rc oscillator (firc) digita l interface . . . . . . . . . . . . . . . . . 114 6.6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 RM0017 contents doc id 14629 rev 8 4/904 6.6.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.6.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 6.7 frequency-modulated phase-locked loop (fmpll) . . . . . . . . . . . . . . . . 115 6.7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 6.7.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 6.7.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 6.7.4 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 6.7.5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 6.7.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.7.7 recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 6.8 clock monitor unit (cmu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 6.8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 6.8.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 6.8.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.8.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 6.8.5 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . 126 7 clock generation module (mc_cgm). . . . . . . . . . . . . . . . . . . . . . . . . . 131 7.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 7.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 7.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 7.3.1 normal and reset modes of operation . . . . . . . . . . . . . . . . . . . . . . . . 133 7.4 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 7.5 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 7.5.1 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 7.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 7.6.1 system clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 7.6.2 output clock multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 7.6.3 output clock division selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 8 mode entry module (mc_me) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 8.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 8.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 8.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 8.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 contents RM0017 5/904 doc id 14629 rev 8 8.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 8.3.1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 8.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 8.4.1 mode transition request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 8.4.2 modes details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 8.4.3 mode transition process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 8.4.4 protection of mode configuration registers . . . . . . . . . . . . . . . . . . . . 191 8.4.5 mode transition interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 8.4.6 peripheral clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 8.4.7 application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 9 reset generation m odule (mc_rgm). . . . . . . . . . . . . . . . . . . . . . . . . . 195 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 9.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 9.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 9.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 9.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 9.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 9.3.1 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 9.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 9.4.1 reset state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 9.4.2 destructive resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 9.4.3 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 9.4.4 functional resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 9.4.5 standby entry sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 9.4.6 alternate event generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 9.4.7 boot mode capturing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 10 power control unit (mc_pcu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 10.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 10.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 10.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 10.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 10.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 10.3.1 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 RM0017 contents doc id 14629 rev 8 6/904 10.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 10.4.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 10.4.2 reset / power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 10.4.3 mc_pcu configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 10.4.4 mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 10.5 initialization information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 10.6 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 10.6.1 standby mode considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 11 voltage regulators and powe r supplies . . . . . . . . . . . . . . . . . . . . . . . 229 11.1 voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 11.1.1 high power regulator (hpreg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 11.1.2 low power regulator (lpreg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 11.1.3 ultra low power regulator (ulpreg) . . . . . . . . . . . . . . . . . . . . . . . . . . 229 11.1.4 lvds and por . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 11.1.5 vreg digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 11.1.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 11.2 power supply strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 11.3 power domain organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 12 wakeup unit (wkpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 12.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 12.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 12.3 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 12.4 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . 236 12.4.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 12.4.2 nmi status flag register (nsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 12.4.3 nmi configuration register (ncr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 12.4.4 wakeup/interrupt status flag register (wisr) . . . . . . . . . . . . . . . . . . 239 12.4.5 interrupt request enable register (irer) . . . . . . . . . . . . . . . . . . . . . 240 12.4.6 wakeup request enable register (wrer) . . . . . . . . . . . . . . . . . . . . . 240 12.4.7 wakeup/interrupt rising-edge event enable register (wireer) . . . 241 12.4.8 wakeup/interrupt fallin g-edge event enable regi ster (wifeer) . . . 241 12.4.9 wakeup/interrupt filter enable register (wifer) . . . . . . . . . . . . . . . . 241 12.4.10 wakeup/interrupt pullup enable register (wipuer) . . . . . . . . . . . . . 242 12.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 contents RM0017 7/904 doc id 14629 rev 8 12.5.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 12.5.2 non-maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 12.5.3 external wakeups/interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 12.5.4 on-chip wakeups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 13 real time clock / autonomous peri odic interrupt (rtc/a pi) . . . . . . 247 13.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 13.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 13.3 device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 13.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 13.4.1 functional mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 13.4.2 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 13.5 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 13.5.1 rtc supervisor control register (rtcsupv) . . . . . . . . . . . . . . . . . . 250 13.5.2 rtc control register (rtcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 13.5.3 rtc status register (rtcs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 13.5.4 rtc counter register (rtccnt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 13.6 rtc functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 13.7 api functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 14 can sampler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 14.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 14.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 14.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 14.3.1 control register (cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 14.3.2 sample register n (n = 0..11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 14.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 14.4.1 enabling/disabling the can sampler . . . . . . . . . . . . . . . . . . . . . . . . . . 259 14.4.2 baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 15 e200z0h core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 15.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 15.2 microarchitecture summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 15.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 15.4 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 15.4.1 instruction unit features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 RM0017 contents doc id 14629 rev 8 8/904 15.4.2 integer unit features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 15.4.3 load/store unit features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 15.4.4 e200z0h system bus features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 15.4.5 nexus 2+ features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 15.5 core registers and programmer?s model . . . . . . . . . . . . . . . . . . . . . . . . 266 16 interrupt controller (intc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 16.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 16.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 16.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 16.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 16.4.1 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 16.5 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . 271 16.5.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 16.5.2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 16.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 16.6.1 interrupt request sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 16.6.2 priority management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 16.6.3 handshaking with processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 16.7 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 16.7.1 initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 16.7.2 interrupt exception handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 16.7.3 isr, rtos, and task hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 16.7.4 order of execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 16.7.5 priority ceiling protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 16.7.6 selecting priorities according to request rates and deadlines . . . . . . . 296 16.7.7 software configurable interrupt requests . . . . . . . . . . . . . . . . . . . . . . . 296 16.7.8 lowering priority within an isr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 16.7.9 negating an interrupt request outside of its isr . . . . . . . . . . . . . . . . . 297 16.7.10 examining lifo contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 17 crossbar switch (xbar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 17.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 17.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 17.3 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 17.4 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 contents RM0017 9/904 doc id 14629 rev 8 17.5 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 17.5.1 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 17.5.2 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 17.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 17.6.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 17.6.2 general operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 17.6.3 master ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 17.6.4 slave ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 17.6.5 priority assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 17.6.6 arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 18 memory protection unit (mpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 18.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 18.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 18.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 18.4 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 18.5 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . 306 18.5.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 18.5.2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 18.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 18.6.1 access evaluation macro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 18.6.2 putting it all together and ahb error terminations . . . . . . . . . . . . . . . . 321 18.7 initialization information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 18.8 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 19 system integration unit lite (siul) . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 19.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 19.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 19.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 19.4 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 19.4.1 detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 19.5 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . 327 19.5.1 siul memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 19.5.2 register protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 19.5.3 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 RM0017 contents doc id 14629 rev 8 10/904 19.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 19.6.1 pad control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 19.6.2 general purpose input and output pads (gpio) . . . . . . . . . . . . . . . . . 346 19.6.3 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 19.7 pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 20 inter-integrated circui t bus controller module (i 2 c) . . . . . . . . . . . . . 349 20.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 20.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 20.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 20.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 20.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 20.2.1 scl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 20.2.2 sda . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 20.3 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . 350 20.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 20.3.2 i 2 c bus address register (ibad) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 20.3.3 i 2 c bus frequency divider register (ibfd) . . . . . . . . . . . . . . . . . . . . 352 20.3.4 i 2 c bus control register (ibcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 20.3.5 i 2 c bus status register (ibsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 20.3.6 i 2 c bus data i/o register (ibdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 20.3.7 i 2 c bus interrupt config register (ibic) . . . . . . . . . . . . . . . . . . . . . . . 361 20.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 20.4.1 i-bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 20.4.2 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 20.5 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 20.5.1 i 2 c programming examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 21 lin controller (linflex) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 21.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 21.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 21.2.1 lin mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 21.2.2 uart mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 21.2.3 features common to lin and uart . . . . . . . . . . . . . . . . . . . . . . . . . . 372 21.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 21.4 fractional baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 contents RM0017 11/904 doc id 14629 rev 8 21.5 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 21.5.1 initialization mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 21.5.2 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 21.5.3 low power mode (sleep) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 21.6 test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 21.6.1 loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 21.6.2 self test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 21.7 memory map and registers description . . . . . . . . . . . . . . . . . . . . . . . . . 377 21.7.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 21.8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403 21.8.1 uart mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403 21.8.2 lin mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 21.8.3 8-bit timeout counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 21.8.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 22 flexcan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 22.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 22.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 22.1.2 flexcan module features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 22.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 22.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 22.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 22.2.2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 22.3 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . 419 22.3.1 flexcan memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 22.3.2 message buffer structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 22.3.3 rx fifo structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 22.3.4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 22.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 22.4.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 22.4.2 local priority transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 22.4.3 transmit process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 22.4.4 arbitration process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 22.4.5 receive process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 22.4.6 matching process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449 22.4.7 data coherence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 RM0017 contents doc id 14629 rev 8 12/904 22.4.8 rx fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452 22.4.9 can protocol related features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 22.4.10 modes of operation details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 22.4.11 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 22.4.12 bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 22.5 initialization/application info rmation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 22.5.1 flexcan initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 22.5.2 flexcan addressing and sram size configurations . . . . . . . . . . . . . . 460 23 deserial serial peripheral interface (dspi) . . . . . . . . . . . . . . . . . . . . . 461 23.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 23.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462 23.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 23.3.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 23.3.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 23.3.3 module disable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 23.3.4 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464 23.4 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464 23.4.1 signal overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464 23.4.2 signal names and descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464 23.5 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . 465 23.5.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 23.5.2 dspi module configuration register (dspix_mcr) . . . . . . . . . . . . . . 466 23.5.3 dspi transfer count register (dspix_tcr) . . . . . . . . . . . . . . . . . . . . 469 23.5.4 dspi clock and transfer attributes registers 0?5 (dspix_ctarn) . . 470 23.5.5 dspi status register (dspix_sr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 23.5.6 dspi interrupt request enable register (dspix_rser) . . . . . . . . . . 480 23.5.7 dspi push tx fifo register (dspix_pushr) . . . . . . . . . . . . . . . . 482 23.5.8 dspi pop rx fifo register (dspix_popr) . . . . . . . . . . . . . . . . . . 484 23.5.9 dspi transmit fifo registers 0?3 (dspix_txfrn) . . . . . . . . . . . . . . 485 23.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 23.6.1 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 23.6.2 start and stop of dspi transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 23.6.3 serial peripheral interface (spi) configuration . . . . . . . . . . . . . . . . . . . 489 23.6.4 dspi baud rate and clock delay generation . . . . . . . . . . . . . . . . . . . . . 492 23.6.5 transfer formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 contents RM0017 13/904 doc id 14629 rev 8 23.6.6 continuous serial communications clock . . . . . . . . . . . . . . . . . . . . . . . 503 23.6.7 interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 23.6.8 power saving features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 23.7 initialization and application information . . . . . . . . . . . . . . . . . . . . . . . . . 508 23.7.1 how to change queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508 23.7.2 baud rate settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508 23.7.3 delay settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 23.7.4 calculation of fifo pointer addresses . . . . . . . . . . . . . . . . . . . . . . . . 510 24 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 24.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 24.2 technical overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 24.2.1 overview of the stm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515 24.2.2 overview of the emios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515 24.2.3 overview of the pit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517 24.3 system timer module (stm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517 24.3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517 24.3.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 24.3.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . 518 24.3.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 24.4 enhanced modular io subsystem (emios) . . . . . . . . . . . . . . . . . . . . . . 522 24.4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522 24.4.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 24.4.3 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . 525 24.4.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 24.4.5 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . 567 24.5 periodic interrupt timer (pit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 24.5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 24.5.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 24.5.3 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 24.5.4 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . 572 24.5.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576 24.5.6 initialization and application information . . . . . . . . . . . . . . . . . . . . . . . 577 25 analog-to-digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579 25.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579 RM0017 contents doc id 14629 rev 8 14/904 25.1.1 device-specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579 25.1.2 device-specific implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 25.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 25.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581 25.3.1 analog channel conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581 25.3.2 analog clock generator and conversion timings . . . . . . . . . . . . . . . . . . 584 25.3.3 adc sampling and conversion timing . . . . . . . . . . . . . . . . . . . . . . . . . 585 25.3.4 adc ctu (cross triggering unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586 25.3.5 presampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587 25.3.6 programmable analog watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588 25.3.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 25.3.8 external decode signals delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 25.3.9 power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 25.3.10 auto-clock-off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591 25.4 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591 25.4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591 25.4.2 control logic registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596 25.4.3 interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 25.4.4 threshold registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 25.4.5 presampling registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608 25.4.6 conversion timing registers ctr[0..2] . . . . . . . . . . . . . . . . . . . . . . . . . 611 25.4.7 mask registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611 25.4.8 delay registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616 25.4.9 data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617 26 cross triggering unit (ctu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619 26.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619 26.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619 26.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619 26.4 memory map and register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 620 26.4.1 event configuration registers (ctu_evtcfgrx) (x = 0...63) . . . . . . 620 26.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621 26.5.1 channel value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623 27 static ram (sram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 27.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 contents RM0017 15/904 doc id 14629 rev 8 27.2 low power configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 27.3 register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 27.4 sram ecc mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626 27.4.1 access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626 27.4.2 reset effects on sram accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627 27.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627 27.6 initialization and application information . . . . . . . . . . . . . . . . . . . . . . . . . 627 28 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629 28.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629 28.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630 28.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630 28.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631 28.4.1 module structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631 28.4.2 flash memory module sectorization . . . . . . . . . . . . . . . . . . . . . . . . . . 632 28.4.3 testflash block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633 28.4.4 shadow sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634 28.4.5 user mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 28.4.6 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636 28.4.7 power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636 28.4.8 low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637 28.5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637 28.5.1 cflash register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639 28.5.2 dflash register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668 28.6 programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692 28.6.1 modify operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692 28.6.2 double word program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693 28.6.3 sector erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695 28.7 platform flash memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703 28.7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703 28.7.2 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . 706 28.8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715 28.8.1 access protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716 28.8.2 read cycles ? buffer miss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716 28.8.3 read cycles ? buffer hit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716 28.8.4 write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716 RM0017 contents doc id 14629 rev 8 16/904 28.8.5 error termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716 28.8.6 access pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717 28.8.7 flash error response operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717 28.8.8 bank0 page read buffers and prefetch operation . . . . . . . . . . . . . . . . . 717 28.8.9 bank1 temporary holding register . . . . . . . . . . . . . . . . . . . . . . . . . . . 719 28.8.10 read-while-write functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720 28.8.11 wait-state emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721 29 register protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723 29.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723 29.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723 29.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724 29.4 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724 29.5 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . 724 29.5.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725 29.5.2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726 29.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728 29.6.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728 29.6.2 change lock settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728 29.6.3 access errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731 29.7 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732 29.8 protected registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732 30 software watchdog timer (swt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737 30.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737 30.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737 30.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737 30.4 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737 30.5 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . 738 30.5.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738 30.5.2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738 30.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743 31 error correction status module (ecsm) . . . . . . . . . . . . . . . . . . . . . . . 745 31.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745 contents RM0017 17/904 doc id 14629 rev 8 31.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745 31.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745 31.4 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . 745 31.4.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745 31.4.2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746 31.4.3 register protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767 32 ieee 1149.1 test access port controller (jtagc) . . . . . . . . . . . . . . . 768 32.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768 32.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768 32.3 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768 32.4 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769 32.5 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769 32.5.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769 32.5.2 ieee 1149.1-2001 defined test modes . . . . . . . . . . . . . . . . . . . . . . . . 769 32.6 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770 32.7 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . 770 32.7.1 instruction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770 32.7.2 bypass register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771 32.7.3 device identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771 32.7.4 boundary scan register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772 32.8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772 32.8.1 jtagc reset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772 32.8.2 ieee 1149.1-2001 (jtag) test access port . . . . . . . . . . . . . . . . . . . . 772 32.8.3 tap controller state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772 32.8.4 jtagc instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774 32.8.5 boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776 32.9 e200z0 once controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776 32.9.1 e200z0 once controller block diagram . . . . . . . . . . . . . . . . . . . . . . . 776 32.9.2 e200z0 once controller functional description . . . . . . . . . . . . . . . . . 777 32.9.3 e200z0 once controller register description . . . . . . . . . . . . . . . . . . 777 32.10 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779 33 nexus development interface (ndi ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 780 33.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780 33.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780 RM0017 contents doc id 14629 rev 8 18/904 33.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781 33.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782 33.4.1 nexus reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782 33.4.2 operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783 33.5 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783 33.5.1 nexus signal reset states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783 33.6 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . 783 33.6.1 nexus debug interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784 33.6.2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785 33.7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795 33.7.1 npc_hndshk module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795 33.7.2 enabling nexus clients for tap access . . . . . . . . . . . . . . . . . . . . . . . . 796 33.7.3 configuring the ndi for nexus messaging . . . . . . . . . . . . . . . . . . . . . . 796 33.7.4 programmable mcko frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797 33.7.5 nexus messaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797 33.7.6 evto sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797 33.7.7 debug mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798 33.7.8 ownership trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798 appendix a register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879 list of tables RM0017 19/904 doc id 14629 rev 8 list of tables table 1. guide to this reference manual. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 2. reference manual integration and functional content . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 3. code flash memory scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 4. sram memory scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 5. spc560bx and spc560cx device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 6. spc560bx and spc560cx memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 7. voltage supply pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 8. system pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 9. functional port pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 10. nexus 2+ pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 11. boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 12. rchw field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 13. examples of legal and illegal passwords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 14. censorship configuration and truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 table 15. sscm_status[bmode] values as used by bam . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 16. serial boot mode ? baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 17. bam censorship mode detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 18. uart boot mode download protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 19. flexcan boot mode download protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 20. sscm memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 21. sscm_status allowed register accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 22. sscm_status field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 23. sscm_memconfig field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 24. sscm_memconfig allowed register accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 25. sscm_error field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 26. sscm_error allowed register accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 27. sscm_debugport field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 28. debug status port modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 29. sscm_debugport allowed register accesses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 30. password comparison register field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 31. sscm_pwcmph/l allowed register accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 32. spc560bx and spc560cx ? peripheral clock sources . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 33. truth table of crysta l oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 34. fxosc_ctl field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 35. sxosc truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 36. sxosc_ctl field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 37. sirc_ctl field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 38. firc_ctl field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 39. fmpll memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 40. cr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 41. input divide ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 42. output divide ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 43. loop divide ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 44. mr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 45. fmpll lookup table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 46. progressive clock switching on pll_select rising edge . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 47. cmu memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 48. cmu_csr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 RM0017 list of tables doc id 14629 rev 8 20/904 table 49. cmu_fdr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 table 50. cmu_hfrefr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 table 51. cmu_lfrefr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 9 table 52. cmu_isr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 53. cmu_mdr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 54. mc_cgm register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 table 55. mc_cgm memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 56. output clock enable register (cgm_oc_en) field descriptions. . . . . . . . . . . . . . . . . . 138 table 57. output clock division select register (cgm_ocds_sc) field descriptions . . . . . . . . . 139 table 58. system clock select status register (cgm_sc_ss) field descriptions . . . . . . . . . . . . 140 table 59. system clock divider configuration registers (cgm_sc_dc0?2) field descriptions . 140 table 60. mc_me mode descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 table 61. mc_me register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 table 62. mc_me memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 table 63. global status register (me_gs) field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 64. mode control register (me_mctl) field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 158 table 65. mode enable register (me_me) field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 table 66. interrupt status register (me_is) field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 table 67. interrupt mask register (me_im) field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 68. invalid mode transition status register (me_imts) field descriptions . . . . . . . . . . . . . 162 table 69. debug mode transition status register (me_dmts) field descriptions . . . . . . . . . . . . 163 table 70. mode configuration registers (me_ list of tables RM0017 21/904 doc id 14629 rev 8 table 100. wisr field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 table 101. irer field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 table 102. wrer field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 table 103. wireer field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 table 104. wifeer field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 table 105. wifer field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 table 106. wipuer field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 table 107. rtc/api register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 table 108. rtcsupv field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 table 109. rtcc field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 table 110. rtcs field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 table 111. rtccntfield descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 table 112. can sampler memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 table 113. cr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 table 114. interrupt sources available . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 table 115. intc memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 table 116. intc_mcr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 table 117. intc_cpr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 table 118. pri values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 table 119. intc_iackr field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 table 120. intc_sscir[0:7] field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 table 121. intc_psr0_3?intc_psr208_210 field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . 278 table 122. intc priority select register address offsets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 table 123. interrupt vector table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 table 124. order of isr execution example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 table 125. xbar switch ports for spc560b x and spc560cx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 table 126. hardwired bus master priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 table 127. mpu memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 table 128. mpu_cesr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 table 129. mpu_earn field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 table 130. mpu_edrn field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 table 131. mpu_rgdn.word0 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 table 132. mpu_rgdn.word1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 table 133. mpu_rgdn.word2 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 table 134. mpu_rgdn.word3 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 table 135. mpu_rgdaacn field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 table 136. protection violation definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 table 137. siul signal properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 table 138. siul memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 table 139. midr1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 table 140. midr2 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 table 141. isr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 table 142. irer field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 table 143. ireer field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 table 144. ifeer field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 table 145. ifer field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 table 146. pcr bit implementation by pad type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5 table 147. pcrx field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 table 148. psmi0_3 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 table 149. peripheral input pin selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 table 150. gpdo0_3 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 table 151. gpdi0_3 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 RM0017 list of tables doc id 14629 rev 8 22/904 table 152. pgpdo0 ? pgpdo3 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 table 153. pgpdi0 ? pgpdi3 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 table 154. mpgpdo0 ? mpgpdo7 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 table 155. mpgpdo0..mpgpdo7 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 table 156. ifmc field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 table 157. ifcpr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 table 158. i2c memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 table 159. ibad field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 table 160. ibfd field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 table 161. i-bus multiplier factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 table 162. i-bus prescaler divider values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 table 163. i-bus tap and prescale values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 table 164. i 2 c divider and hold values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 table 165. ibcr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 table 166. ibsr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 table 167. ibic field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 table 168. interrupt summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 table 169. error calculation for programmed baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 table 170. linflex memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 table 171. lincr1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 table 172. checksum bits configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 table 173. lin master break length selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 table 174. operating mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 table 175. linier field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 table 176. linsr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 table 177. linesr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 table 178. uartcr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 table 179. uartsr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 table 180. lintcsr field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 table 181. linocr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 table 182. lintocr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 table 183. linfbrr field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 table 184. linibrr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 table 185. integer baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 table 186. lincfr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 table 187. lincr2 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 table 188. bidr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 table 189. bdrl field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 table 190. bdrm field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 table 191. ifer field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 table 192. ifer[fact] configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 table 193. ifmi field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 table 194. ifmr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 table 195. ifmr[ifm] configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 table 196. ifcr2 n field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 table 197. ifcr2 n + 1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403 table 198. message buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 table 199. filter to interrupt vector correlation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 table 200. linflex interrupt control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 table 201. flexcan signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 table 202. flexcan memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 table 203. message buffer mb0 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 list of tables RM0017 23/904 doc id 14629 rev 8 table 204. message buffer structure field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 table 205. message buffer code for rx buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 table 206. message buffer code for tx buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 table 207. rx fifo structure field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 table 208. mcr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 table 209. idam coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 table 210. ctrl field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 table 211. rxgmask field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 table 212. esr field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 table 213. fault confinement state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440 table 214. imask2 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 table 215. imask1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 table 216. iflag2 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 table 217. iflag1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444 table 218. rximr0 ? rximr63 field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 table 219. time segment syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 table 220. can standard compliant bit time segment settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 table 221. minimum ratio between peripheral clock frequency and can bit rate . . . . . . . . . . . . . . . 457 table 222. signal properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464 table 223. dspi memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 table 224. dspix_mcr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467 table 225. dspix_tcr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 table 226. dspi x _ctar n field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 table 227. dspi sck duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 table 228. dspi transfer frame size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 table 229. dspi pcs to sck delay scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 table 230. dspi after sck delay scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 table 231. dspi delay after transfer scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 table 232. dspi baud rate scaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 table 233. dspi sck duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 table 234. dspi transfer frame size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 table 235. dspi pcs to sck delay scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 table 236. dspi after sck delay scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 table 237. dspi delay after transfer scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 table 238. dspi baud rate scaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 table 239. dspix_sr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 table 240. dspix_rser field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 table 241. dspix_pushr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 83 table 242. dspix_popr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 table 243. dspix_txfrn field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 table 244. dspix_rxfrn field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 table 245. state transitions for start and stop of dspi transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 table 246. baud rate computation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 table 247. cs to sck delay computation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 table 248. after sck delay computation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 table 249. delay after transfer computation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 table 250. peripheral chip select strobe assert computation example. . . . . . . . . . . . . . . . . . . . . . . . 495 table 251. peripheral chip select strobe negate computation example . . . . . . . . . . . . . . . . . . . . . . . 495 table 252. delayed master sample point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 table 253. interrupt request conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 table 254. baud rate values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 table 255. delay values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 RM0017 list of tables doc id 14629 rev 8 24/904 table 256. emios_0 channel to pin mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6 table 257. emios_1 channel to pin mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6 table 258. stm memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 table 259. stm_cr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 table 260. stm_cnt field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520 table 261. stm_ccrn field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520 table 262. stm_cirn field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 table 263. stm_cmpn field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 table 264. emios memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 table 265. unified channel memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526 table 266. emiosmcr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526 table 267. global prescaler clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527 table 268. emiosgflag field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 28 table 269. emiosoudis field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 table 270. emiosucdis field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 table 271. emiosa[n], emiosb[n] and emiosalta[n] values assignment. . . . . . . . . . . . . . . . . . . 530 table 272. emiosc[n] field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532 table 273. uc internalprescaler clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 table 274. uc input filter bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 table 275. uc bsl bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 table 276. channel mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 table 277. emioss[n] field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536 table 278. pit memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 table 279. timer channel n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 table 280. pitmcr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573 table 281. ldval field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574 table 282. cval field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574 table 283. tctrl field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575 table 284. tflg field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576 table 285. configurations for starting normal conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581 table 286. adc sampling and conversion timing at 5 v / 3.3 v for adc_0 . . . . . . . . . . . . . . . . . . . . 586 table 287. max/min adc_clk frequency and related configuration settings at 5 v / 3.3 v for adc_0 586 table 288. presampling vo ltage selection based on prevalx fields . . . . . . . . . . . . . . . . . . . . . . . . 588 table 289. values of wdgxh and wdgxl fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589 table 290. adc_0 digital registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591 table 291. mcr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597 table 292. msr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 table 293. isr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 table 294. ceocfr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 table 295. interrupt mask register (imr) field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603 table 296. cimr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604 table 297. wtisr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605 table 298. wtimr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606 table 299. trcx field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 table 300. thrhlrx field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608 table 301. pscr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609 table 302. psr field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610 table 303. ctr field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611 table 304. ncmr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613 table 305. jcmr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615 table 306. dsdr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616 table 307. pdedr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617 list of tables RM0017 25/904 doc id 14629 rev 8 table 308. cdr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617 table 309. ctu memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620 table 310. ctu_evtcfgrx field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620 table 311. trigger source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621 table 312. ctu-to-adc channel assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623 table 313. low power configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 table 314. sram memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 table 315. number of wait states required for sram operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . 627 table 316. flash memory features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630 table 317. cflash module sectorization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632 table 318. dflash module sectorization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633 table 319. cflash testflash structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633 table 320. dflash testflash structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634 table 321. shadow sector structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 table 322. cflash registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637 table 323. dflash registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638 table 324. cflash_mcr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 39 table 326. low address space configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643 table 327. mid address space configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643 table 325. array space size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643 table 328. cflash_mcr bits set/clear priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644 table 329. cflash_lml field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645 table 330. cflash_nvlml field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647 table 331. cflash_sll field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649 table 332. cflash_nvsll field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652 table 333. cflash_lms field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 55 table 334. cflash_adr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 56 table 335. cflash_adr content: priority list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656 table 336. cflash_ut0 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 table 337. cflash_ut1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659 table 338. cflash_ut2 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660 table 339. cflash_umisr0 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660 table 340. cflash_umisr1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661 table 341. cflash_umisr2 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662 table 342. cflash_umisr3 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663 table 343. cflash_umisr4 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664 table 344. nvpwd0 field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665 table 345. nvpwd1 field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666 table 346. nvscc0 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666 table 347. nvscc1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667 table 348. nvusro field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668 table 349. dflash_mcr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 69 table 350. array space size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672 table 351. low address space configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673 table 352. mid address space configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673 table 353. dflash_mcr bits set/clear priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673 table 354. dflash_lml field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675 table 355. dflash_nvlml field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677 table 356. dflash_sll field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679 table 357. dflash_nvsll field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681 table 358. dflash_lms field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 82 table 359. dflash_adr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 83 RM0017 list of tables doc id 14629 rev 8 26/904 table 360. dflash_adr content: priority list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683 table 361. dflash_ut0 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684 table 362. dflash_ut1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686 table 363. dflash_ut2 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687 table 364. dflash_umisr0 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688 table 365. dflash_umisr1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689 table 366. dflash_umisr2 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690 table 367. dflash_umisr3 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691 table 368. dflash_umisr4 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692 table 369. flash memory modify operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693 table 370. bit manipulation: double words with the same ecc value . . . . . . . . . . . . . . . . . . . . . . . . 701 table 371. flash memory-related regions in the system memory map . . . . . . . . . . . . . . . . . . . . . . . 707 table 372. platform flash memory controller 32-bit memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . 707 table 373. pfcr0 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709 table 374. pfcr1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712 table 375. pfapr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714 table 376. nvpfapr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715 table 377. platform flash memory controller stall-while-write interrupts. . . . . . . . . . . . . . . . . . . . . . . 721 table 378. additional wait-state encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721 table 379. extended additional wait-state encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722 table 380. register protection memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725 table 381. slbr n field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726 table 382. soft lock bits vs. protected address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727 table 383. gcr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728 table 384. protected registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732 table 385. swt memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738 table 386. swt_cr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739 table 387. swt_ir field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740 table 388. swt_to register field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 41 table 389. swt_wn register field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 1 table 390. swt_sr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742 table 391. swt_co field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742 table 392. ecsm memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745 table 393. pct field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747 table 394. rev field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747 table 395. iopmc field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748 table 396. mwcr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749 table 397. mir field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 table 398. mudcr field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751 table 399. ecr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753 table 400. esr field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755 table 401. eegr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757 table 402. pfear field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759 table 403. pfemr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760 table 404. pfeat field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761 table 405. pfedr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762 table 406. prear field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762 table 407. presr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763 table 408. ram syndrome mapping for single-bit correctable errors. . . . . . . . . . . . . . . . . . . . . . . . . 763 table 409. premr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765 table 410. preat field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766 table 411. predr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766 list of tables RM0017 27/904 doc id 14629 rev 8 table 412. jtag signal properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770 table 413. device identification register field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771 table 414. jtag instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774 table 415. e200z0 once register addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778 table 416. ndi signal reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783 table 417. nexus debug interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784 table 418. did field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785 table 419. pcr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786 table 420. dc1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788 table 421. dc2 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790 table 422. ds field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790 table 423. rwcs field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792 table 424. read/write access status bit encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793 table 425. wt field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795 table 426. jtagc instruction opcodes to enable nexus clients . . . . . . . . . . . . . . . . . . . . . . . . . . . 796 table 427. nexus client jtag instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796 table 428. ndi configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797 table 429. src packet encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797 table 430. error code encoding (tcode = 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799 table 431. module base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801 table 432. detailed register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802 table 433. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879 RM0017 list of figures doc id 14629 rev 8 28/904 list of figures figure 1. register figure conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 2. spc560bx and spc560cx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 3. lqfp 64-pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 4. lqfp 100-pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 figure 5. lqfp 144-pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 figure 6. lbga208 configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 7. boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 8. boot sector structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 9. flash memory boot mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 10. censorship control in flash memory boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 11. censorship control in serial boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 12. bam logic flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 13. bam censorship mode detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 14. bam serial boot mode flow for censorship enabled and private password. . . . . . . . . . . . . 93 figure 15. start address, vle bit and download size in bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 16. linflex bit timing in uart mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 17. flexcan bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 18. sscm block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 19. system status register (sscm_status) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 20. system memory configuration register (sscm_memconfig) . . . . . . . . . . . . . . . . . . . 100 figure 21. error configuration (sscm_error). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 figure 22. debug status port register (sscm_debugport) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 23. password comparison register high word (sscm_pwcmph) . . . . . . . . . . . . . . . . . . . 104 figure 24. password comparison register low word (sscm_pwcmpl). . . . . . . . . . . . . . . . . . . . 104 figure 25. spc560bx and spc560cx system clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 26. fast external crystal osc illator control register (f xosc_ctl) . . . . . . . . . . . . . . . . . . . 109 figure 27. slow external crystal osc illator control register ( sxosc_ctl) . . . . . . . . . . . . . . . . . . 111 figure 28. low power rc control register (sirc_ctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 29. firc oscillator control register (firc_ctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 30. fmpll block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 31. control register (cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 32. modulation register (mr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 figure 33. fmpll output clock division flow during progressive switching . . . . . . . . . . . . . . . . . . . . 121 figure 34. frequency modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 35. clock monitor unit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 36. control status register (cmu_csr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 37. frequency display register (cmu_fdr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 figure 38. high frequency reference register fmpll (cmu_hfrefr) . . . . . . . . . . . . . . . . . . . . 128 figure 39. low frequency reference register fmpll (cmu_lfrefr) . . . . . . . . . . . . . . . . . . . . . 129 figure 40. interrupt status register (cmu_isr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 figure 41. measurement duration register (cmu_mdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 figure 42. mc_cgm block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 figure 43. output clock enable register (cgm_oc_en) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 figure 44. output clock division select register (cgm_ocds_sc) . . . . . . . . . . . . . . . . . . . . . . . . 138 figure 45. system clock select status register (cgm_sc_ss) . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 figure 46. system clock divider configuration registers (cgm_sc_dc0?2) . . . . . . . . . . . . . . . . 140 figure 47. mc_cgm system clock generation overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 figure 48. mc_cgm output clock multiplexer and pa[0] generation . . . . . . . . . . . . . . . . . . . . . . . 143 list of figures RM0017 29/904 doc id 14629 rev 8 figure 49. mc_meblock diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 figure 50. global status register (me_gs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 figure 51. mode control register (me_mctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 figure 52. mode enable register (me_me) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8 figure 53. interrupt status register (me_is). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 figure 54. interrupt mask register (me_im) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 figure 55. invalid mode transition status register (me_imts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 figure 56. debug mode transition status register (me_dmts) . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 figure 57. invalid mode transition status register (me_imts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 figure 58. test mode configuration register (me_test_mc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 figure 59. safe mode configuration register (me_safe_mc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 figure 60. drun mode configuration r egister (me_drun_mc) . . . . . . . . . . . . . . . . . . . . . . . . . . 167 figure 61. run0?3 mode configuration registers (me_run0?3_mc) . . . . . . . . . . . . . . . . . . . . 167 figure 62. halt mode configuration register (me_halt_mc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 figure 63. stop mode configuration register (me_stop_mc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 figure 64. standby mode configuration register (me_standby_mc). . . . . . . . . . . . . . . . . . . . 169 figure 65. peripheral status register 0 (me_ps0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 figure 66. peripheral status register 1 (me_ps1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 figure 67. peripheral status register 2 (me_ps2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 figure 68. peripheral status register 3 (me_ps3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 figure 69. run peripheral configuration registers (me_run_pc0?7) . . . . . . . . . . . . . . . . . . . . . 173 figure 70. low-power peripheral configuration registers (me_lp_pc0?7) . . . . . . . . . . . . . . . . . 174 figure 71. peripheral control registers (me_pctl0?143) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 figure 72. mc_me mode diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 figure 73. mc_me transition diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 figure 74. mc_me application example flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 figure 75. mc_rgm block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 figure 76. functional event status register (rgm_fes). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 figure 77. destructive event status register (rgm_des) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 figure 78. functional event reset disable register (rgm_ferd) . . . . . . . . . . . . . . . . . . . . . . . . . 204 figure 79. destructive event reset disable register (rgm_derd) . . . . . . . . . . . . . . . . . . . . . . . . 205 figure 80. functional event alternate request register (rgm_fear) . . . . . . . . . . . . . . . . . . . . . . 206 figure 81. destructive event alternate request register (rgm_dear) . . . . . . . . . . . . . . . . . . . . . 208 figure 82. functional event short sequ ence register (rgm_fess). . . . . . . . . . . . . . . . . . . . . . . . 209 figure 83. standby reset sequence register (rgm_stdby) . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 figure 84. functional bidirectional reset enable register (rgm_fbre) . . . . . . . . . . . . . . . . . . . . 211 figure 85. mc_rgm state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 figure 86. mc_pcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 figure 87. power domain #0 configuration register (pcu_pconf0) . . . . . . . . . . . . . . . . . . . . . . . 222 figure 88. power domain #1 configuration register (pcu_pconf1) . . . . . . . . . . . . . . . . . . . . . . . 224 figure 89. power domain #2 configuration register (pcu_pconf2) . . . . . . . . . . . . . . . . . . . . . . . 224 figure 90. power domain status register (pcu_pstat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 figure 91. mc_pcu events during power sequences (non-standby mode) . . . . . . . . . . . . . . . . 226 figure 92. mc_pcu events during power sequences (standby mode). . . . . . . . . . . . . . . . . . . . 227 figure 93. voltage regulator control register (vreg_ctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 figure 94. power domain organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 figure 95. wkpu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 figure 96. nmi status flag register (nsr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 figure 97. nmi configuration register (ncr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 38 figure 98. wakeup/interrupt status flag register (wisr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 figure 99. interrupt request enable register (irer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 figure 100. wakeup request enable register (wrer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 RM0017 list of figures doc id 14629 rev 8 30/904 figure 101. wakeup/interrupt rising-edge event enable register (wireer) . . . . . . . . . . . . . . . . . . 241 figure 102. wakeup/inte rrupt falling-edge event enable register (w ifeer) . . . . . . . . . . . . . . . . . . 241 figure 103. wakeup/interrupt filter enable register (wifer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 figure 104. wakeup/interrupt pullup enable register (wipuer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 figure 105. nmi pad diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 figure 106. external interrupt pad diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 figure 107. rtc/api block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 figure 108. clock gating for rtc clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 figure 109. rtc supervisor control register (rtcsupv). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 figure 110. rtc control register (rtcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 figure 111. rtc status register (rtcs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 figure 112. rtc counter register (rtccnt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4 figure 113. extended can data frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 figure 114. control register (cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 figure 115. sample register n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 figure 116. e200z0h block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 figure 117. e200z0 supervisor mode program model sprs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 figure 118. intc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 figure 119. intc module configuration register (intc_mcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 figure 120. intc current priority register (intc_cpr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 figure 121. intc interrupt acknowledge register (intc_iackr) when intc_mcr[vtes] = 0 . . . . 275 figure 122. intc interrupt acknowledge register (intc_iackr) when intc_mcr[vtes] = 1 . . . . 275 figure 123. intc end-of-interrupt register (intc_eoir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 figure 124. intc software set/clear interrupt register 0?3 (intc_sscir[0:3]). . . . . . . . . . . . . . . . 276 figure 125. intc software set/clear interrupt register 4?7 (intc_sscir[4:7]). . . . . . . . . . . . . . . . 277 figure 126. intc priority select register 0?3 (intc_psr[0:3]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 figure 127. intc priority select register 208-210 (intc_psr[208:210]) . . . . . . . . . . . . . . . . . . . . . 278 figure 128. software vector mode handshaking timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 figure 129. hardware vector mode handshaking timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 figure 130. xbar block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 figure 131. mpu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 figure 132. mpu control/error status register (mpu_cesr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 figure 133. mpu error address register, slave port n (mpu_earn) . . . . . . . . . . . . . . . . . . . . . . . . 309 figure 134. mpu error detail register, slave port n (mpu_edrn) . . . . . . . . . . . . . . . . . . . . . . . . . . 310 figure 135. mpu region descriptor, word 0 register (mpu_rgdn.word0) . . . . . . . . . . . . . . . . . . . 311 figure 136. mpu region descriptor, word 1 register (mpu_rgdn.word1) . . . . . . . . . . . . . . . . . . . 312 figure 137. mpu region descriptor, word 2 register (mpu_rgdn.word2) . . . . . . . . . . . . . . . . . . . 313 figure 138. mpu region descriptor, word 3 register (mpu_rgdn.word3) . . . . . . . . . . . . . . . . . . . 316 figure 139. mpu rgd alternate access control n (mpu_rgdaacn). . . . . . . . . . . . . . . . . . . . . . . . 317 figure 140. mpu access evaluation macro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 figure 141. system integration unit lite block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 figure 142. mcu id register #1 (midr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 figure 143. mcu id register #2 (midr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 figure 144. interrupt status flag register (isr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 figure 145. interrupt request enable register (irer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 figure 146. interrupt rising-edge event enable register (ireer). . . . . . . . . . . . . . . . . . . . . . . . . . . 332 figure 147. interrupt falling-edge event en able register (ifeer). . . . . . . . . . . . . . . . . . . . . . . . . . . 333 figure 148. interrupt filter enable register (ifer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 figure 149. pad configuration registers (pcrx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 35 figure 150. pad selection for multiplexed inputs register (psmi0_3) . . . . . . . . . . . . . . . . . . . . . . . . 337 figure 151. port gpio pad data output register 0?3 (gpdo0_3) . . . . . . . . . . . . . . . . . . . . . . . . . . 340 figure 152. port gpio pad data input register 0?3 (gpdi0_3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 list of figures RM0017 31/904 doc id 14629 rev 8 figure 153. interrupt filter maximum counter registers (ifmc0?ifmc15) . . . . . . . . . . . . . . . . . . . . 344 figure 154. interrupt filter clock prescaler register (ifcpr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 figure 155. data port example arrangement showing configuration for different port width accesses 346 figure 156. external interrupt pad diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 figure 157. i 2 c block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 0 figure 158. i 2 c bus address register (ibad) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 figure 159. i 2 c bus frequency divider register (ibfd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 figure 160. sda hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 figure 161. scl divider and sda hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 figure 162. i 2 c bus control register (ibcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 figure 163. i 2 c bus status register (ibsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 figure 164. i 2 c bus data i/o register (ibdr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 figure 165. i 2 c bus interrupt config register (ibic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 figure 166. i 2 c bus transmission signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 figure 167. start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 figure 168. i 2 c bus clock synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 figure 169. flow-chart of typical i 2 c interrupt routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 figure 170. lin topology network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 figure 171. linflex block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 figure 172. linflex operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 figure 173. linflex in loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 figure 174. linflex in self test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 figure 175. lin control register 1 (lincr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 figure 176. lin interrupt enable register (linier) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 figure 177. lin status register (linsr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 figure 178. lin error status register (linesr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 figure 179. uart mode control register (uartcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 figure 180. uart mode status register (uartsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 figure 181. lin timeout control status register (lintcsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 figure 182. lin output compare register (linocr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 figure 183. lin timeout control register (lintocr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 92 figure 184. lin fractional baud rate register (linfbrr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 figure 185. lin integer baud rate register (linibrr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4 figure 186. lin checksum field register (lincfr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 95 figure 187. lin control register 2 (lincr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 figure 188. buffer identifier register (bidr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 figure 189. buffer data register lsb (bdrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 figure 190. buffer data register msb (bdrm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 figure 191. identifier filter enable register (ifer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 figure 192. identifier filter match index (ifmi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 figure 193. identifier filter mode register (ifmr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 figure 194. identifier filter control register (ifcr2 n ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 figure 195. identifier filter control register (ifcr2 n + 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403 figure 196. uart mode 8-bit data frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 figure 197. uart mode 9-bit data frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 figure 198. filter configuration?register organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 10 figure 199. identifier match index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 figure 200. lin synch field measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 figure 201. header and response timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 figure 202. flexcan block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 figure 203. message buffer structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 figure 204. rx fifo structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 RM0017 list of figures doc id 14629 rev 8 32/904 figure 205. id table 0 ? 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 figure 206. module configuration register (mcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7 figure 207. control register (ctrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 figure 208. free running timer (timer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 figure 209. rx global mask register (rxgmask). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 figure 210. error counter register (ecr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 figure 211. error and status register (esr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 figure 212. interrupt masks 2 register (imask2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 41 figure 213. interrupt masks 1 register (imask1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 42 figure 214. interrupt flags 2 register (iflag2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 figure 215. interrupt flags 1 register (iflag1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444 figure 216. rx individual mask registers (rximr0 ? rximr63) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 figure 217. can engine clocking scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 figure 218. segments within the bit time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 figure 219. arbitration, match and move time windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 figure 220. dspi block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 figure 221. dspi with queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462 figure 222. dspi module configuration register (dspix_mcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467 figure 223. dspi transfer count register (dspix_tcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 figure 224. dspi clock and transfer attributes registers 0?5 (dspix_ctarn) . . . . . . . . . . . . . . . . 471 figure 225. dspi status register (dspix_sr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 78 figure 226. dspi interrupt request enable register (dspix_rser). . . . . . . . . . . . . . . . . . . . . . . . . 480 figure 227. dspi push tx fifo register (dspix_pushr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482 figure 228. dspi pop rx fifo register (dspix_popr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 figure 229. dspi transmit fifo register 0?3 (dspix_txfrn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 figure 230. dspi receive fifo registers 0?3 (dspix_rxfrn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 figure 231. spi serial protocol overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 figure 232. dspi start and stop state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 figure 233. communications clock prescalers and scalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 figure 234. peripheral chip select strobe timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 figure 235. dspi transfer timing diagram (mtfe = 0, cpha = 0, fmsz = 8) . . . . . . . . . . . . . . . . . . 497 figure 236. dspi transfer timing diagram (mtfe = 0, cpha = 1, fmsz = 8) . . . . . . . . . . . . . . . . . . 498 figure 237. dspi modified transfer format (mtfe = 1, cpha = 0, f sck =f sys / 4) . . . . . . . . . . . . . . 500 figure 238. dspi modified transfer format (mtfe = 1, cpha = 1, f sck =f sys / 4) . . . . . . . . . . . . . . 501 figure 239. example of non-continuous format (cpha = 1, cont = 0) . . . . . . . . . . . . . . . . . . . . . . . 502 figure 240. example of continuous transfer (cpha = 1, cont = 1). . . . . . . . . . . . . . . . . . . . . . . . . . 502 figure 241. polarity switching between frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 figure 242. continuous sck timing diagram (cont= 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 figure 243. continuous sck timing diagram (cont=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 figure 244. tx fifo pointers and counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 figure 245. interaction between timers and relevant peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 figure 246. stm control register (stm_cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 19 figure 247. stm count register (stm_cnt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9 figure 248. stm channel control register (stm_ccrn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520 figure 249. stm channel interrupt register (stm_cirn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 figure 250. stm channel compare register (stm_cmpn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 figure 251. channel configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 figure 252. emios module configuration register (emiosmcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 526 figure 253. emios global flag (emiosgflag) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 figure 254. emios output update disable (emiosoudis) register. . . . . . . . . . . . . . . . . . . . . . . . . 528 figure 255. emios enable channel (emiosucdis) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 figure 256. emios uc a register (emiosa[n]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 list of figures RM0017 33/904 doc id 14629 rev 8 figure 257. emios uc b register (emiosb[n]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 figure 258. emios uc counter register (emioscnt[n]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 figure 259. emios uc control register (emiosc[n]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532 figure 260. emios uc status register (emioss[n]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536 figure 261. emios uc alternate a register (emiosalta[n]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 figure 262. single action input capture with rising edge triggering example . . . . . . . . . . . . . . . . . . . . 539 figure 263. single action input capture with both edges triggering example. . . . . . . . . . . . . . . . . . . . 539 figure 264. saoc example with edpol value being transferred to the output flip-flop . . . . . . . . . . . 540 figure 265. saoc example toggling the output flip-flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 figure 266. saoc example with flag behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 figure 267. input pulse width measurement example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 figure 268. b1 and a1 updates at emiosa[n] and emiosb[n] reads . . . . . . . . . . . . . . . . . . . . . . . . 542 figure 269. input period measurement example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3 figure 270. a1 and b1 updates at emiosa[n] and emiosb[n] reads . . . . . . . . . . . . . . . . . . . . . . . . 544 figure 271. double action output compare with flag set on the second match . . . . . . . . . . . . . . . . 545 figure 272. double action output compare with flag set on both matches. . . . . . . . . . . . . . . . . . . . 545 figure 273. daoc with transfer disabling example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6 figure 274. modulus counter up mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 figure 275. modulus counter up/down mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548 figure 276. modulus counter buffered (mcb) up count mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549 figure 277. modulus counter buffered (mcb) up/down mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549 figure 278. mcb mode a1 register update in up counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 550 figure 279. mcb mode a1 register update in up/down counter mode . . . . . . . . . . . . . . . . . . . . . . 550 figure 280. opwfmb a1 and b1 match to output register delay. . . . . . . . . . . . . . . . . . . . . . . . . . . 551 figure 281. opwfmb mode with a1 = 0 (0% duty cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552 figure 282. opwfmb a1 and b1 registers update and flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553 figure 283. opwfmb mode from 100% to 0% duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553 figure 284. opwmcb a1 and b1 registers load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555 figure 285. opwmcb with lead dead time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556 figure 286. opwmcb with trail dead time insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 7 figure 287. opwmcb with 100% duty cycle (a1 = 4 and b1 = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . 559 figure 288. opwmb mode matches and flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 figure 289. opwmb mode with 0% duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561 figure 290. opwmb mode from 100% to 0% duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561 figure 291. opwmt example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564 figure 292. opwmt with 0% duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564 figure 293. opwmt with 100% duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565 figure 294. lnput programmable filter submodule diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565 figure 295. input programmable filter example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 figure 296. time base period when running in the fastest prescaler ratio . . . . . . . . . . . . . . . . . . . . . 568 figure 297. time base generation with external clock and clear on match start . . . . . . . . . . . . . . . . . 569 figure 298. time base generation with internal clock and clear on match start . . . . . . . . . . . . . . . . . 569 figure 299. time base generation with clear on match end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570 figure 300. pit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 figure 301. pit module control register (pitmcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573 figure 302. timer load value register (ldval) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3 figure 303. current timer value register (cval) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4 figure 304. timer control register (tctrl). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575 figure 305. timer flag register (tflg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575 figure 306. stopping and starting a timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576 figure 307. modifying running timer period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577 figure 308. dynamically setting a new load value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577 RM0017 list of figures doc id 14629 rev 8 34/904 figure 309. adc implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 figure 310. normal conversion flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582 figure 311. injected sample/conversion sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3 figure 312. sampling and conversion timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585 figure 313. presampling sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588 figure 314. presampling sequence with preconv = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588 figure 315. guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589 figure 316. main configuration register (mcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597 figure 317. main status register (msr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 figure 318. interrupt status register (isr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 figure 319. channel pending register 0 (ceocfr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601 figure 320. channel pending register 1 (ceocfr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601 figure 321. channel pending register 2 (ceocfr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 figure 322. interrupt mask register (imr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 figure 323. channel interrupt mask register 0 (cimr0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603 figure 324. channel interrupt mask register 1 (cimr1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604 figure 325. channel interrupt mask register 2 (cimr2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604 figure 326. watchdog threshold interrupt status register (wtisr) . . . . . . . . . . . . . . . . . . . . . . . . . 605 figure 327. watchdog threshold interrupt mask register (wtimr). . . . . . . . . . . . . . . . . . . . . . . . . . 605 figure 328. threshold control register (trcx, x = [0..3]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 figure 329. threshold register (thrhlr[0:3]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 08 figure 330. presampling control register (pscr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 8 figure 331. presampling register 0 (psr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609 figure 332. presampling register 1 (psr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610 figure 333. presampling register 2 (psr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610 figure 334. conversion timing registers ctr[0..2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611 figure 335. normal conversion mask register 0 (ncmr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612 figure 336. normal conversion mask register 1 (ncmr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612 figure 337. normal conversion mask register 2 (ncmr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613 figure 338. injected conversion mask register 0 (jcmr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614 figure 339. injected conversion mask register 1 (jcmr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614 figure 340. injected conversion mask register 2 (jcmr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615 figure 341. decode signals delay register (dsdr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616 figure 342. power-down exit delay register (pdedr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616 figure 343. channel data register (cdr[0..95]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 17 figure 344. cross triggering unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619 figure 345. event configuration registers (ctu_evtcfgrx) (x = 0...63) . . . . . . . . . . . . . . . . . . . . 620 figure 346. flash memory architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629 figure 347. cflash and dflash module structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631 figure 348. cflash module configuration register (cflash_mcr) . . . . . . . . . . . . . . . . . . . . . . . . . 639 figure 349. cflash low/mid address space block locking register (cflash_lml). . . . . . . . . . . . 644 figure 350. cflash nonvolatile low/mid address space block locking register (cflash_nvlml) . 647 figure 351. cflash secondary low/mid address space block locking register (cflash_sll) . . . 649 figure 352. cflash nonvolatile secondary low/mid address space block locking register . . . . . . . . . . (cflash_nvsll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651 figure 353. cflash low/mid address space block select register (cflash_lms) . . . . . . . . . . . . . . 654 figure 354. cflash address register (cflash_adr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655 figure 355. cflash user test 0 register (cflash_ut0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 figure 356. cflash user test 1 register (cflash_ut1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659 figure 357. cflash user test 2 register (cflash_ut2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659 figure 358. cflash user multiple input signature register 0 (cflash_umisr0). . . . . . . . . . . . . . . 660 figure 359. cflash user multiple input signature register 1 (cflash_umisr1). . . . . . . . . . . . . . . 661 list of figures RM0017 35/904 doc id 14629 rev 8 figure 360. cflash user multiple input signature register 2 (cflash_umisr2). . . . . . . . . . . . . . . 662 figure 361. cflash user multiple input signature register 3 (cflash_umisr3). . . . . . . . . . . . . . . 663 figure 362. cflash user multiple input signature register 4 (cflash_umisr4). . . . . . . . . . . . . . . 664 figure 363. cflash nonvolatile private censorship password 0 register (nvpwd0) . . . . . . . . . . . . 665 figure 364. cflash nonvolatile private censorship password 1 register (nvpwd1) . . . . . . . . . . . . 665 figure 365. cflash nonvolatile system censorship control 0 register (nvscc0) . . . . . . . . . . . . . . . 666 figure 366. cflash nonvolatile system censorship control 1 register (nvscc1) . . . . . . . . . . . . . . . 667 figure 367. cflash nonvolatile user options register (nvusro) . . . . . . . . . . . . . . . . . . . . . . . . . . . 668 figure 368. dflash module configuration register (dflash_mcr) . . . . . . . . . . . . . . . . . . . . . . . . . 669 figure 369. dflash low/mid address space block locking register (dflash_lml). . . . . . . . . . . . 674 figure 370. dflash nonvolatile low/mid address space block locking register (dflash_nvlml) . 676 figure 371. dflash secondary low/mid address spac e block locking register (dflash_sll) . . . . 678 figure 372. dflash nonvolatile secondary low/mid address space block locking register . . . . . . . . . . (dflash_nvsll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680 figure 373. dflash low/mid address space block select register (dflash_lms). . . . . . . . . . . . . 682 figure 374. dflash address register (dflash_adr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683 figure 375. dflash user test 0 register (dflash_ut0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684 figure 376. dflash user test 1 register (dflash_ut1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686 figure 377. dflash user test 2 register (dflash_ut2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687 figure 378. dflash user multiple input signature register 0 (dflash_umisr0). . . . . . . . . . . . . . . 688 figure 379. dflash user multiple input signature register 1 (dflash_umisr1). . . . . . . . . . . . . . . 689 figure 380. dflash user multiple input signature register 2 (dflash_umisr2). . . . . . . . . . . . . . . 690 figure 381. dflash user multiple input signature register 3 (dflash_umisr3). . . . . . . . . . . . . . . 691 figure 382. dflash user multiple input signature register 4 (dflash_umisr4). . . . . . . . . . . . . . . 692 figure 383. power architecture e200z0h rpp reference platform block diagram. . . . . . . . . . . . . . . . 704 figure 384. pflash configuration register 0 (pfcr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708 figure 385. pflash configuration register 1 (pfcr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712 figure 386. pflash access protection register (pfapr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714 figure 387. nonvolatile platform flash access protection register (nvpfapr) . . . . . . . . . . . . . . . . 715 figure 388. register protection block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723 figure 389. register protection memory diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 24 figure 390. soft lock bit register (slbr n ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726 figure 391. global configuration register (gcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 27 figure 392. change lock settings directly via area #4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729 figure 393. change lock settings for 16-bit protected addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . 729 figure 394. change lock settings for 32-bit protected addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . 730 figure 395. change lock settings for mixed protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730 figure 396. enable locking via mirror module space (area #3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731 figure 397. enable locking for protected and unprotected addresses . . . . . . . . . . . . . . . . . . . . . . . 731 figure 398. swt control register (swt_cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 9 figure 399. swt interrupt register (swt_ir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740 figure 400. swt time-out register (swt_to) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741 figure 401. swt window register (swt_wn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741 figure 402. swt service register (swt_sr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 2 figure 403. swt counter output register (swt_co) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742 figure 404. processor core type register (pct) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7 figure 405. soc-defined platform revision register (rev) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747 figure 406. ips on-platform module configuration register (iopmc) . . . . . . . . . . . . . . . . . . . . . . . . 748 figure 407. miscellaneous wakeup control (mwcr) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749 figure 408. miscellaneous interrupt (mir) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 50 figure 409. miscellaneous user-defined co ntrol (mudcr) register . . . . . . . . . . . . . . . . . . . . . . . . . 751 figure 410. ecc configuration (ecr) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 52 RM0017 list of figures doc id 14629 rev 8 36/904 figure 411. ecc status register (esr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755 figure 412. ecc error generation register (eegr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756 figure 413. platform flash ecc address register (pfear) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759 figure 414. platform flash ecc master number register (pfemr) . . . . . . . . . . . . . . . . . . . . . . . . . 760 figure 415. platform flash ecc attributes register (pfeat). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760 figure 416. platform flash ecc data register (pfedr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761 figure 417. platform ram ecc address register (prear). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762 figure 418. platform ram ecc syndrome register (presr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763 figure 419. platform ram ecc master number register (premr) . . . . . . . . . . . . . . . . . . . . . . . . . 765 figure 420. platform ram ecc attributes register (preat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765 figure 421. platform ram ecc data register (predr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766 figure 422. jtag controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768 figure 423. 5-bit instruction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771 figure 424. device identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771 figure 425. shifting data through a register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772 figure 426. ieee 1149.1-2 001 tap controller finite state machine. . . . . . . . . . . . . . . . . . . . . . . . . . . 773 figure 427. e200z0 once block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777 figure 428. once command register (ocmd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778 figure 429. ndi functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780 figure 430. ndi implementation block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 81 figure 431. nexus device id (did) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785 figure 432. port configuration register (pcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786 figure 433. development control register 1 (dc1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788 figure 434. development control register 2 (dc2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789 figure 435. development status (ds) register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790 figure 436. read/write access control/status (rwcs) register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 792 figure 437. read/write access address (rwa) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793 figure 438. read/write access data (rwd) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794 figure 439. watchpoint trigger (wt) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794 figure 440. ownership trace message format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798 figure 441. error message format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799 preface RM0017 37/904 doc id 14629 rev 8 1 preface 1.1 overview the primary objective of this document is to define the functionality of the spc560bx and spc560cx microcontroller for use by software and hardware developers. the spc560bx and spc560cx is built on power architecture ? technology and integrates technologies that are important for today?s automotive vehicle body applications. the information in this book is subject to change without notice, as described in the disclaimers on the title page. as with any technical documentation, it is the reader?s responsibility to be sure he or she is using the most recent version of the documentation. to locate any published errata or updates for this document, visit the st web site at www.st.com. 1.2 audience this manual is intended for system software and hardware developers and applications programmers who want to develop products with the spc560bx and spc560cx device. it is assumed that the reader understands operating systems, microprocessor system design, basic principles of software and hardware, and basic details of the power architecture. 1.3 guide to this reference manual table 1. guide to th is reference manual chapter description functional group # title 2 introduction general overview, family description, feature list and information on how to use the reference manual in conjunction with other available documents. introductory material 3 memory map memory map of all peripherals and memory. memory map 4 signal description pinout diagrams and descriptions of all pads. signals 5 microcontroller boot boot ? boot mechanism ? describes what configuration is required by the user and what processes are involved when the microcontroller boots from flash memory or serial boot modes. ? describes censorship. ? boot assist module (bam) features of bam code and when it's used. ? system status and configuration module (sscm) reports information ab out current state and configuration of the microcontroller. RM0017 preface doc id 14629 rev 8 38/904 6 clock description ? covers configuration of all of the clock sources in the system. ? describes the clock monitor unit (cmu). clocks and power (includes operating mode configuration and how to wake up from low power mode) 7 clock generation module (mc_cgm) determines how the clock sources are used (including clock dividers) to generate the reference clocks for all of the modules and peripherals. 8 mode entry module (mc_me) determines the clock source, memory, power and peripherals that are available in each operating mode. 9 reset generation module (mc_rgm) manages the process of ent ering and exiting reset, allows reset sources to be configured (including lvd's) and provides status reporting. 10 power control unit (mc_pcu) controls the power to different power domains within the microcontroller (allowing sram to be selectively powered in standby mode). 11 voltage regulators and power supplies information on voltage regulator implementation. includes enable bit for 5 v lvd (see also mc_rgm). 12 wakeup unit (wkpu) always-active analog block. details configuration of 2 internal (api/rtc) and 30 external (pin) low power mode wakeup sources. 13 real time clock / autonomous periodic interrupt (rtc/api) details configuration and operation of timers that are predominately used for system wakeup. 14 can sampler details on how to configure the can sampler which is used to capture the identifier frame of a can message when the microcontroller is in low power mode. 15 e200z0h core overview on cores. for more details consult the core reference manuals available on www.st.com. core platform modules 16 interrupt controller (intc) provides the configuration and control of all of the external interrupts (non-core) that are then routed to the ivor4 core interrupt vector. 17 crossbar switch (xbar) describes the connections of the xbar masters and slaves on this microcontroller. 18 memory protection unit (mpu) the mpu sits on the slave side of the xbar and allows highly configurable control over all master accesses to the memory. 19 system integration unit lite (siul) how to configure the pins or ports for input or output functions including extern al interrupts and dsi serialization. ports table 1. guide to this reference manual (continued) chapter description functional group # title preface RM0017 39/904 doc id 14629 rev 8 20 inter-integrated circuit bus controller module (i 2 c) these chapters describe the configuration and operation of the various communication modules. some of these modules support edma requests to fill / empty buffer queues to minimize cpu overhead. communication modules 21 lin controller (linflex) 22 flexcan 23 deserial serial peripheral interface (dspi) 24 timers timer modules ? technical overview gives an overview of the available system timer modules showing links to other modules as well as tables detailing the external pins associated with emios timer channels. ? system timer module (stm) a simple 32-bit free running counter with 4 compare channels with interrupt on match. it can be read at any time; this is very useful for measuring execution times. ? enhanced modular io subsystem (emios) highly configurable timer module(s) supporting pwm, output compare and input capture features. includes interrupt and edma support. ? periodic interrupt timer (pit) set of 32-bit countdown timers that provide periodic events (which can trigger an interrupt) with automatic re-load. 25 analog-to-digital converter (adc) details the configuration and operation of the adc modules as well as detailing the channels that are shared between the 10-bit and 12-bit adc. the adc is tightly linked to the intc, edma, pit_rti and ctu. when used in conjunction with these other modules, the cpu overhead for an adc conversion is significantly reduced. adc system 26 cross triggering unit (ctu) the ctu allows an adc conversion to be automatically triggered based on an emios event (like a pwm output going high) or a pit_rti event with no cpu intervention. 28 flash memory details the code and data flash memory structure (with ecc), block sizes and the flash memory port configuration, including wait states, line buffer configuration and pre-fetch control. memory 27 static ram (sram) details the structure of th e sram (with ecc). there are no user configurable registers associated with the sram. table 1. guide to this reference manual (continued) chapter description functional group # title RM0017 preface doc id 14629 rev 8 40/904 1.4 register description conventions the register information for spc560bx and spc560cx is presented in: memory maps containing: ? an offset from the module?s base address ? the name and acronym/abbreviation of each register ? the page number on which each register is described register figures field-description tables associated text the register figures show the field structure using the conventions in figure 1 . 29 register protection certain registers in each peripheral can be protected from further writes using the register protection mechanism detailed in this section. registers can either be configured to be unlocked via a soft lock bit or locked unit the next reset. integrity 30 software watchdog timer (swt) the swt offers a selection of configurable modes that can be used to monitor the operation of the microcontroller and /or reset the device or trigger an interrupt if the swt is not correctly serviced. the swt is enabled out of reset. 31 error correction status module (ecsm) provides information about the last reset, general device information, system fault information and detailed ecc error information. 32 ieee 1149.1 test access port controller (jtagc) used for boundary scan as well as device debug. debug 33 nexus development interface (ndi) provides advanced debug features including non intrusive trace capabilities. a register map summarizes the registers on this microcontroller register summary revision history summarizes the changes between each successive revision of this reference manual revision history information table 1. guide to this reference manual (continued) chapter description functional group # title preface RM0017 41/904 doc id 14629 rev 8 figure 1. register figure conventions the numbering of register bits and fields on spc560bx and spc560cx is as follows: register bit numbers, shown at the top of each figure, use the standard power architecture bit ordering (0, 1, 2, ...) where bit 0 is the most significant bit (msb). multi-bit fields within a register use conventiona l bit ordering (..., 2, 1, 0) where bit 0 is the least significant bit (lsb). 1.5 references in addition to this reference manual, the following documents provide additional information on the operation of the spc560bx and spc560cx: ieee-isto 5001-2003 standard for a global embedded processor interface (nexus) ieee 1149.1-2001 standard - ieee standard test access port and boundary-scan architecture 1.6 how to use the spc560b x and spc560cx documents this section: describes how the spc560bx and spc560cx documents provide information on the microcontroller makes recommendations on how to us e the documents in a system design 1.6.1 the spc560bx and sp c560cx document set the spc560bx and spc560cx document set comprises: this reference manual (provides information on the features of the logical blocks on the device and how they are integrated with each other) the device data sheet (specifies the el ectrical characteristics of the device) the device product brief the following reference documents (available online at www.st.com) are also available to support the cpu on this device: programmer?s reference manual for book e processors variable-length encoding (vle) extension - programming interface manual r0 1 w r field1 field2 w r field w reserved bits read-only fields read/write fields rfield ww1c write 1 to clear field (field will always read 0) r0 00 w field1 field2 write-only fields RM0017 preface doc id 14629 rev 8 42/904 the aforementioned documents describe all of the functional and electrical characteristics of the spc560bx and spc560cx microcontroller. depending on your task, you may need to refer to multiple documents to make design decisions. however, in general the use of the documents can be divided up as follows: use the reference manual (this document) during software development and when allocating functions during system design. use the data sheet when designing hardware and optimizing power consumption. use the cpu reference documents when doing detailed software development in assembly language or debugging complex software interactions. 1.6.2 reference manual content the content in this document focuses on the functionality of the microcontroller rather than its performance. most chapters describe the functionality of a particular on-chip module, such as a can controller or timer. the remaining chapters describe how these modules are integrated into the memory map, how they are powered and clocked, and the pin-out of the device. in general, when an individual module is enabled for use all of the detail required to configure and operate it is contained in the dedicated chapter. in some cases there are multiple implementations of this module, however, there is only one chapter for each type of module in use. for this reason, the address of registers in each module is normally provided as an offset from a base address which can be found in 3, memory map . the benefit of this approach is that software developed for a pa rticular module can be easily reused on this device and on other related devices that use the same modules. the steps to enable a module for use varies but typically these require configuration of the integration features of the mi crocontroller. the module will norma lly have to be powered and enabled at system level, then a clock may have to be explicitly chosen and finally if required the input and output connections to the external system must be configured. the primary integration chapters of the reference manual contain most of the information required to enable the modules. there are special cases where a chapter may describe module functionality and some integration features for convenience ? for example, the microcontroller input/output (siul) module. inte gration and functional content is provided in the manual as shown in ta b l e 2 . table 2. reference manual integration and functional content chapter integration content functional content introduction ? the main features on chip ? a summary of the functions provided by each module ? memory map how the memory map is allocated, including: ? internal ram ? flash memory ? external memory-mapped resources and the location of the registers used by the peripherals (1) ? preface RM0017 43/904 doc id 14629 rev 8 1.7 using the spc5 60bx and spc560cx there are many different approaches to designing a system using the spc560bx and spc560cx so the guidance in this section is provided as an example of how the documents can be applied in this task. familiarity with the spc560bx and spc560cx mo dules can help ensure that its features are being optimally used in a system design. therefore, the current chapter is a good starting point. further information on the detailed features of a module are provided within the module chapters. these, combined with the current chapter, should provide a good introduction to the functions available on the mcu. 1.7.1 hardware design the spc560bx and spc560cx requires that certain pins are connected to particular power supplies, system functions and other voltage levels for operation. the spc560bx and spc560cx internal logic operates from 1.2 v (nominal) supplies that are normally supplied by the on-chip voltage regulator from a 5 v or 3.3 v supply. the 3.3? 5 v (10%) supply is also used to supp ly the input/output pins on the mcu. 4, signal description, describes the power supply pin names, numbers and their purpose. for more detail on the voltage supply of each pin, see 11, voltage regulators and power supplies . for specifications of the voltage ranges and limits and decoupling of the power supplies see the spc560bx and spc560cx data sheet. certain pins have dedicated functions that affect the behavior of the mcu after reset. these include pins to force test or alternate boot conditions and debug features. these are described in 4, signal description, and a hardware designer should take care that these pins are connected to allow correct operation. signal description how the signals from each of the modules are combined and brought to a particular pin on a package ? boot assist module cpu boot sequence from reset implementation of t he boot options if internal flash memory is not used clock description clocking architecture of the device (which clock is available for the system and each peripheral) description of operation of different clock sources interrupt controller interrupt vector table operation of the module mode entry module module numbering for cont rol and status operation of operating modes system integration unit lite how input signals are mapped to individual modules including external interrupt pins operation of gpio voltage regulators and power supplies power distribution to the mcu ? wakeup unit allocation of inputs to the wakeup unit operation of the wakeup feature 1. to find the address of a register in a particular module take the start address of the module given in the memory map and add the offset for the register given in the module chapter. table 2. reference manual integration and functional content (continued) chapter integration content functional content RM0017 preface doc id 14629 rev 8 44/904 beyond power supply and pins that have special functions there are also pins that have special system purposes such as oscillator and reset pins. these are also described in 4, signal description . the reset pin is bidirectional and its function is closely tied to the reset generation module [ 9, reset generation module (mc_rgm) ]. the crystal oscillator pins are dedicated to this func tion but the oscillator is not star ted automatically after reset. the oscillator module is described in 6, clock description, along with the internal clock architecture and the other oscillator sources on chip. 1.7.2 input/output pins the majority of the pins on the mcu are input/output pins which may either operate as general purpose pins or be connected to a particular on-chip module. the arrangement allows a function to be available on several pins. the system designer should allocate the function for the pin before connecting to external hardware. the software should then choose the correct function to match the hardware. the pad characteristics can vary depending on the functions on the pad. 4, signal description, describes each pad type (for example, s, m, or j). two pads may be able to carry the same function but have different pad types. the electrical specification of the pa ds is described in the data sheet dependent on the function enabled and the pad type. there are three modules that configure the various functions available: system integration unit lite (siul) wakeup unit (wkpu) 32 khz oscillator (sxosc) the siul configures the digital pin functions. each pin has a register (pcr) in the module that allows selection of the output functions that is connected to the pin. the available settings for the pcr are described in section 4.7, functional ports. inputs are selected using the psmi registers; these are described in 19, system integration unit lite (siul) . (psmi registers connect a module to one of several pins, whereas the pcr registers connect a pin to one of several modules). the wkpu provides the abilit y to cause interrupts and wake the mcu from low power modes and operates independently from the siul. in addition to digital i/o functions the sxosc is a "special function" that provides a slow external crystal. the sxosc is enabled independently from the digital i/o which means that the digital function on the pin must be di sabled when the sxosc is active. the adc functions are enabled using the pcrs. 1.7.3 software design certain modules provide system integration functions, and other modules (such as timers) provide specific functions. preface RM0017 45/904 doc id 14629 rev 8 from reset, the modules involved in configuring the system for application software are: boot assist module (bam) ? determines the selected boot source reset generation module (mc_rgm) ? determines the behavior of the mcu when various reset sources are triggered and reports the source of the reset mode entry module (mc_me) ? controls which operating mode the mcu is in and configures the peripherals and clocks and power supplies for each of the modes power control unit (mc_pcu) ? determines which power domains are active clock generation module (mc_cgm) ? chooses the clock source for the system and many peripherals after reset, the mcu w ill automatically select the appropr iate reset source and begin to execute code. at this point the system clock is the 16 mhz firc oscillator, the cpu is in supervisor mode and all the memory is availa ble. initialization is required before most peripherals may be used and before the sram can be read (since the sram is protected by ecc, the syndrome will generally be uninit ialized after reset and reads would fail the check). accessing disabled features causes error conditions or interrupts. a typical startup routine would involve initializ ing the software environment including stacks, heaps, variable initialization and so on and configuring the mcu for the application. the mc_me module enables the modules and other features like clocks. it is therefore an essential part of the initialization and oper ation software. in general, the software will configure an mc_me mode to make certain peripherals, clocks, and memory active and then switch to that mode. 6, clock description, includes a graphic of the clock architecture of the mcu. this can be used to determine how to configure the mc_c gm module. in general software will configure the module to enable the required clocks and plls and route these to the active modules. after these steps are complete it is possible to configure the input/output pins and the modules for the application. 1.7.4 other features the mc_me module manages low power modes and so it is likely that it will be used to switch into different configurations (module sets, clocks) depending on the application requirements. the mcu includes two other features to improve the integrity of the application: it is possible to enable a software watchdog (swt) immediately at reset or afterwards to help detect code runaway. individual register settings can be protected from unintended writes using the features of the register protection module. the protected registers are shown in 29, register protection . other integration functionality is provided by the system status and configuration module (sscm). RM0017 introduction doc id 14629 rev 8 46/904 2 introduction 2.1 the spc560bx and spc560c x microcontroller family the spc560bx and spc560cx represents a new generation of 32-bit microcontrollers based on the power architecture ? . it belongs to an expanding family of automotive-focused products targeted at addressing the next wave of body electronics applications within the vehicle. this document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the device. the advanced and cost-efficient host processor core of the family complies with the power architecture embedded category. it operates at speeds of up to 64 mhz and offers high performance processing optimized for low power consumption. it capitalizes on the available development infrastructure of current power architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations. see section 2.4, developer support , for more information. 2.2 features this section describes the features of the spc560bx and spc560cx. 2.2.1 spc560bx and spc560 cx family comparison ta bl e 3 and ta bl e 4 report the memory scaling of code flash and sram. ta bl e 5 provides a summary of the different members of the spc560bx and spc560cx family. this information is intended to provide an understanding of the range of functionality offered by this family. table 3. code flash memory scaling memory size start address end address 256 kb 0x00000000 0x0003ffff 384 kb 0x00000000 0x0005ffff 512 kb 0x00000000 0x0007ffff table 4. sram memory scaling memory size start address end address 24 kb 0x40000000 0x40005fff 28 kb 0x40000000 0x40006fff 32 kb 0x40000000 0x40007fff 40 kb 0x40000000 0x40009fff 48 kb 0x40000000 0x4000bfff introduction RM0017 47/904 doc id 14629 rev 8 table 5. spc560bx and spc560cx device comparison (1) feature device spc560b4 0l1 spc560b4 0l3 spc560b4 0l5 spc560c4 0l1 spc560c4 0l3 spc560b5 0l1 spc560b5 0l3 spc560b5 0l5 spc560c5 0l1 spc560c5 0l3 spc560b50 b2 cpu e200z0h execution speed (2) static ? up to 64 mhz code flash 256 kb 512 kb data flash 64 kb (4 16 kb) ram 24kb 32kb 32kb 48 kb mpu 8-entry adc 12 ch, 10- bit 28 ch, 10- bit 36 ch, 10- bit 8ch, 10-bit 28 ch, 10- bit 12 ch, 10- bit 28 ch, 10- bit 36 ch, 10- bit 8ch, 10-bit 28 ch, 10-bit 36 ch, 10-bit ctu ye s total timer i/o (3) emios 12 ch, 16- bit 28 ch, 16- bit 56 ch, 16- bit 12 ch, 16- bit 28 ch, 16- bit 12 ch, 16- bit 28 ch, 16- bit 56 ch, 16- bit 12 ch, 16- bit 28 ch, 16-bit 56 ch, 16-bit ? pwm + mc + ic/oc (4) 2 ch 5 ch 10 ch 2 ch 5 ch 2 ch 5 ch 10 ch 2 ch 5 ch 10 ch ? pwm + ic/oc (4) 10 ch 20 ch 40 ch 10 ch 20 ch 10 ch 20 ch 40 ch 10 ch 20 ch 40 ch ?ic/oc (4) 0ch 3ch 6ch 0ch 3ch 0ch 3ch 6ch 0ch 3ch 6ch sci (linflex) 3 (5) 4 spi (dspi) 2 3 2 3 2 3 2 3 can (flexcan) 2 (6) 56 3 (7) 56 i 2 c 1 32 khz oscillator yes gpio (7) 45 79 123 45 79 45 79 123 45 79 123 debug jtag nexus2+ package lqfp 64 (8) lqfp 100 lqfp 144 lqfp 64 (8) lqfp 100 lqfp 64 (8) lqfp 100 lqfp 144 lqfp 64 (8) lqfp 100 lbga 208 (9) RM0017 introduction doc id 14629 rev 8 48/904 1. feature set dependent on selected peripheral mult iplexing?table shows example implementation 2. based on 125 c ambient operating temperature 3. see the emios section of the devic e reference manual for information on the channel configuration and functions. 4. ic - input capture; oc - output compare; pwm - pulse width modulation; mc - modulus counter 5. sci0, sci1 and sci2 are avai lable. sci3 is not available. 6. can0, can1 are available. can2, can3, can4 and can5 are not available. 7. i/o count based on multiplexing with peripherals 8. all lqfp64 information is indicative and must be confirmed dur ing silicon validation. 9. lbga208 available only as development package for nexus2+ introduction RM0017 49/904 doc id 14629 rev 8 2.2.2 block diagram figure 2 shows a top-level block diagram of the spc560bx and spc560cx family. figure 2. spc560bx and spc560cx block diagram 3 x dspi fmpll nexus 2+ nexus sram siul reset control 48 kb external imux gpio and jtag pad control jtag port nexus port e200z0h interrupt requests 64-bit 2 x 3 crossbar switch 6 x flexcan peripheral bridge interrupt request interrupt request i/o clocks instructions data voltage regulator nmi swt pit stm nmi siul . . . . . . . . . . . . intc i 2 c . . . 4 x linflex 2 x emios 36 ch. adc mpu cmu sram flash code flash 512 kb data flash 64 kb mc_pcu mc_me mc_cgm mc_rgm bam ctu rtc sscm (master) (master) (slave) (slave) (slave) controller controller legend: adc analog-to-digital converter bam boot assist module flexcan controller area network cmu clock monitor unit ctu cross triggering unit dspi deserial serial peripheral interface emios enhanced modular input output system fmpll frequency-modulated phase-locked loop i 2 c inter-integrated circuit bus imux internal multiplexer intc interrupt controller jtag jtag controller linflex serial communication interface (lin support) ecsm error correction status module mc_cgm clock generation module mc_me mode entry module mc_pcu power control unit mc_rgm reset generation module mpu memory protection unit nexus nexus development interface (ndi) level nmi non-maskable interrupt pit periodic interrupt timer rtc real-time clock siul system integration unit lite sram static random-access memory sscm system status configuration module stm system timer module swt software watchdog timer wkpu wakeup unit mpu ecsm from peripheral registers blocks wkpu interrupt request with wakeup functionality RM0017 introduction doc id 14629 rev 8 50/904 2.2.3 chip-level features on-chip modules available within the family include the following features: single issue, 32-bit cpu core complex (e200z0) ? compliant with the power architecture? embedded category ? includes an instruction set enhancement allowing variable length encoding (vle) for code size footprint reduction. with the optional encoding of mixed 16-bit and 32-bit instructions, it is possible to achieve significant code size footprint reduction. up to 512 kbytes on-chip code flash supported with the flash controller up to 64 kbytes on-chip data flash supported with the flash controller up to 48 kbytes on-chip sram memory protection unit (mpu) with 8 region descriptors and 32-byte region granularity interrupt controller (intc) capable of handling 148 selectable-priority interrupt sources frequency-modulated phase-locked loop (fmpll) crossbar switch architecture for concurrent access to peripherals, flash, or sram from multiple bus masters boot assist module (bam) supports internal flash programming via a serial link (flexcan or linflex) timer supports input/output channels providing a range of 16-bit input capture, output compare, and pulse width modulation functions (emios) 10-bit analog-to-digital converter (adc) up to 3 serial peripheral interface (dspi) modules up to 4 serial communication interface (linflex) modules ? linflex 1, 2 and 3: master capable ? linflex 0: master capable and slave capable up to 6 enhanced full can (flexcan) modules with 64 configurable message buffers 1 inter-integrated circuit (i 2 c) module up to 123 configurable general purpose pins supporting input and output operations (package dependent) real time counter (rtc) with clock source from firc or sirc supporting autonomous wake-up with 1-ms resolution with max timeout of 2 seconds ? support for rtc with clock source from sxosc, supporting wake-up with 1-sec resolution and max timeout of 1 hour 6 periodic interrupt timers (pit) with 32-bit counter resolution 1 system module timer (stm) nexus development interface (ndi) per ieee-isto 5001-2003 class two plus device/board boundary scan testing supported with per joint test action group (jtag) of ieee (ieee 1149.1) on-chip voltage regulator (vreg) for regulati on of input supply for all internal levels introduction RM0017 51/904 doc id 14629 rev 8 2.3 packages spc560bx and spc560cx family members are offered in the following package types: 64-pin lqfp, 10mm x 10mm outline 100-pin lqfp, 0.5mm pitch, 14mm x 14mm outline 144-pin lqfp, 0.5mm pitch, 20mm x 20mm outline lbga208, 1mm ball pitch, 17mm x 17mm outline development package 2.4 developer support the following development support is available: automotive evaluation boards (evb) f eaturing can, lin in terfaces, and more compilers debuggers jtag and nexus interfaces the following software support is available: osek solutions will be available from multiple third parties can and lin drivers autosar package RM0017 memory map doc id 14629 rev 8 52/904 3 memory map ta bl e 6 shows the memory map for the spc560bx and spc560cx. all addresses on the device, including those that are reserved, are identified in the table. the addresses represent the physical addresses assigned to each ip block. table 6. spc560bx and spc560cx memory map start address end address size (kb) region name 0x0000_0000 0x0000_7fff 32 code flash sector 0 0x0000_8000 0x0000_bfff 16 code flash sector 1 0x0000_c000 0x0000_ffff 16 code flash sector 2 0x0001_0000 0x0001_7fff 32 code flash sector 3 0x0001_8000 0x0001_ffff 32 code flash sector 4 0x0002_0000 0x0003_ffff 128 code flash sector 5 0x0004_0000 0x0005_ffff 128 code flash sector 6 0x0006_0000 0x0007_ffff 128 code flash sector 7 0x0008_0000 0x001f_ffff 1536 reserved 0x0020_0000 0x0020_3fff 16 code flash shadow sector 0x0020_4000 0x003f_ffff 2032 reserved 0x0040_0000 0x0040_3fff 16 code flash test sector 0x0040_4000 0x007f_ffff 4080 reserved 0x0080_0000 0x0080_3fff 16 data flash array 0 0x0080_4000 0x0080_7fff 16 data flash array 1 0x0080_8000 0x0080_bfff 16 data flash array 2 0x0080_c000 0x0080_ffff 16 data flash array 3 0x0081_0000 0x00bf_ffff 4032 reserved 0x00c0_0000 0x00c0_3fff 16 data test sector 0x00c0_4000 0x00df_ffff 4080 reserved 0x0100_0000 0x1fff_ffff 507904 flash emulation mapping 0x2000_0000 0x3fff_ffff 524288 reserved for external bus interface 0x4000_0000 0x4000_bfff 48 sram 0x4000_c000 0xc3f8_7fff 2162160 reserved 0xc3f8_8000 0xc3f8_bfff 16 code flash a configuration 0xc3f8_c000 0xc3f8_ffff 16 data flash a configuration 0xc3f9_0000 0xc3f9_3fff 16 siul 0xc3f9_4000 0xc3f9_7fff 16 wkpu 0xc3f9_8000 0xc3f9_ffff 32 reserved 0xc3fa_0000 0xc3fa_3fff 16 emios_0 memory map RM0017 53/904 doc id 14629 rev 8 0xc3fa_4000 0xc3fa_7fff 16 emios_1 0xc3fa_8000 0xc3fd_7fff 192 reserved 0xc3fd_8000 0xc3fd_bfff 16 sscm 0xc3fd_c000 0xc3fd_ffff 16 mc_me 0xc3fe_0000 0xc3fe_3fff 16 mc_cgm 0xc3fe_4000 0xc3fe_7fff 16 mc_rgm 0xc3fe_8000 0xc3fe_bfff 16 mc_pcu 0xc3fe_c000 0xc3fe_ffff 16 rtc/api 0xc3ff_0000 0xc3ff_3fff 16 pit 0xc3ff4000 0xffdf_ffff 981040 reserved 0xffe0_0000 0xffe0_3fff 16 adc_0 0xffe0_4000 0xffe2_ffff 176 reserved 0xffe3_0000 0xffe3_3fff 16 i2c_0 0xffe3_4000 0xffe3_ffff 48 reserved 0xffe4_0000 0xffe4_3fff 16 linflex_0 0xffe4_4000 0xffe4_7fff 16 linflex_1 0xffe4_8000 0xffe4_bfff 16 linflex_2 0xffe4_c000 0xffe4_ffff 16 linflex_3 0xffe5_0000 0xffe6_3fff 80 reserved 0xffe6_4000 0xffe6_7fff 16 ctu 0xffe6_8000 0xffe6_ffff 32 reserved 0xffe7_0000 0xffe7_3fff 16 can sampler 0xffe7_4000 0xffe7_ffff 48 reserved 0xffe8_0000 0xffef_ffff 512 mirrore d range 0x3f80000?0xc3ffffff 0xfff0_0000 0xfff0_ffff 64 reserved 0xfff1_0000 0xfff1_3fff 16 mpu 0xfff1_4000 0xfff3_7fff 144 reserved 0xfff3_8000 0xfff3_bfff 16 swt 0xfff3_c000 0xfff3_ffff 16 stm 0xfff4_0000 0xfff4_3fff 16 ecsm 0xfff4_4000 0xfff4_7fff 16 reserved 0xfff4_8000 0xfff4_bfff 16 intc 0xfff4_c000 0xfff8_ffff 272 reserved 0xfff9_0000 0xfff9_3fff 16 dspi_0 0xfff9_4000 0xfff9_7fff 16 dspi_1 table 6. spc560bx and spc560cx memory map (continued) start address end address size (kb) region name RM0017 memory map doc id 14629 rev 8 54/904 0xfff9_8000 0xfff9_bfff 16 dspi_2 0xfff9_c000 0xfffb_ffff 144 reserved 0xfffc_0000 0xfffc_3fff 16 flexcan_0 0xfffc_4000 0xfffc_7fff 16 flexcan_1 0xfffc_8000 0xfffc_bfff 16 flexcan_2 0xfffc_c000 0xfffc_ffff 16 flexcan_3 0xfffd_0000 0xfffd_3fff 16 flexcan_4 0xfffd_4000 0xfffd_7fff 16 flexcan_5 0xfffd_8000 0xffff_bfff 144 reserved 0xffff_c000 0xffff_ffff 16 bam table 6. spc560bx and spc560cx memory map (continued) start address end address size (kb) region name signal description RM0017 55/904 doc id 14629 rev 8 4 signal description 4.1 introduction the following sections provide signal descriptions and related information about the functionality and configuration. 4.2 package pinouts the lqfp pinouts and the bga ballmap are provided in the following figures. for more information on pin mult iplexing on this device, see ta b l e 7 through ta bl e 1 0 . figure 3. lqfp 64-pin configuration (a) a. all lqfp64 information is indicative and must be confir med during silicon validation. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 pb[3] pc[9] pa [ 2 ] pa [ 1 ] pa [ 0 ] vss_hv vdd_hv vss_hv reset vss_lv vdd_lv vdd_bv pc[10] pb[0] pb[1] pc[6] pa[11] pa[10] pa [ 9 ] pa [ 8 ] pa [ 7 ] pa [ 3 ] pb[15] pb[14] pb[13] pb[12] pb[11] pb[7] pb[6] pb[5] vdd_hv_adc vss_hv_adc pc[7] pa[15] pa[14] pa [ 4 ] pa[13] pa[12] vdd_lv vss_lv xtal vss_hv extal vdd_hv pb[9] pb[8] pb[10] pb[4] pb[2] pc[8] pc[4] pc[5] ph[9] pc[0] vss_lv vdd_lv vdd_hv vss_hv pc[1] ph[10] pa [ 6 ] pa [ 5 ] pc[2] pc[3] lqfp64 top view RM0017 signal description doc id 14629 rev 8 56/904 figure 4. lqfp 100-pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 pb[3] pc[9] pc[14] pc[15] pa [ 2 ] pe[0] pa [ 1 ] pe[1] pe[8] pe[9] pe[10] pa [ 0 ] pe[11] vss_hv vdd_hv vss_hv reset vss_lv vdd_lv vdd_bv pc[11] pc[10] pb[0] pb[1] pc[6] pa[11] pa[10] pa [ 9 ] pa [ 8 ] pa [ 7 ] vdd_hv vss_hv pa [ 3 ] pb[15] pd[15] pb[14] pd[14] pb[13] pd[13] pb[12] pd[12] pb[11] pd[11] pd[10] pd[9] pb[7] pb[6] pb[5] vdd_hv_adc vss_hv_adc pc[7] pa [ 1 5 ] pa [ 1 4 ] pa [ 4 ] pa [ 1 3 ] pa [ 1 2 ] vdd_lv vss_lv xtal vss_hv extal vdd_hv pb[9] pb[8] pb[10] pd[0] pd[1] pd[2] pd[3] pd[4] pd[5] pd[6] pd[7] pd[8] pb[4] pb[2] pc[8] pc[13] pc[12] pe[7] pe[6] pe[5] pe[4] pc[4] pc[5] pe[3] pe[2] ph[9] pc[0] vss_lv vdd_lv vdd_hv vss_hv pc[1] ph[10] pa [ 6 ] pa [ 5 ] pc[2] pc[3] pe[12] lqfp100 note: availability of port pin alternate functions depends on product selection. signal description RM0017 57/904 doc id 14629 rev 8 figure 5. lqfp 144-pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 pb[3] pc[9] pc[14] pc[15] pg[5] pg[4] pg[3] pg[2] pa [ 2 ] pe[0] pa [ 1 ] pe[1] pe[8] pe[9] pe[10] pa [ 0 ] pe[11] vss_hv vdd_hv vss_hv reset vss_lv vdd_lv vdd_bv pg[9] pg[8] pc[11] pc[10] pg[7] pg[6] pb[0] pb[1] pf[9] pf[8] pf[12] pc[6] pa[11] pa[10] pa [ 9 ] pa [ 8 ] pa [ 7 ] pe[13] pf[14] pf[15] vdd_hv vss_hv pg[0] pg[1] ph[3] ph[2] ph[1] ph[0] pg[12] pg[13] pa [ 3 ] pb[15] pd[15] pb[14] pd[14] pb[13] pd[13] pb[12] pd[12] pb[11] pd[11] pd[10] pd[9] pb[7] pb[6] pb[5] vdd_hv_adc vss_hv_adc pc[7] pf[10] pf[11] pa[15] pf[13] pa[14] pa [ 4 ] pa[13] pa[12] vdd_lv vss_lv xtal vss_hv extal vdd_hv pb[9] pb[8] pb[10] pf[0] pf[1] pf[2] pf[3] pf[4] pf[5] pf[6] pf[7] pd[0] pd[1] pd[2] pd[3] pd[4] pd[5] pd[6] pd[7] pd[8] pb[4] pb[2] pc[8] pc[13] pc[12] pe[7] pe[6] ph[8] ph[7] ph[6] ph[5] ph[4] pe[5] pe[4] pc[4] pc[5] pe[3] pe[2] ph[9] pc[0] vss_lv vdd_lv vdd_hv vss_hv pc[1] ph[10] pa [ 6 ] pa [ 5 ] pc[2] pc[3] pg[11] pg[10] pe[15] pe[14] pg[15] pg[14] pe[12] lqfp144 note: availability of port pin alternate functions depends on product selection. RM0017 signal description doc id 14629 rev 8 58/904 figure 6. lbga208 configuration 4.3 pad configuration during reset phases all pads have a fixed configuration under reset. during the power-up phase, all pads are forced to tristate. 12345678910111213141516 a pc[8] pc[13] nc nc ph[8] ph[4] pc[5] pc[0] nc nc pc[2] nc pe[15] nc nc nc a b pc[9] pb[2] nc pc[12] pe[6] ph[5] pc[4] ph[9] ph[10] nc pc[3] pg[11] pg[15] pg[14] pa[11] pa[10] b c pc[14] vdd_hv pb[3] pe[7] ph[ 7] pe[5] pe[3] vss_lv pc[1] nc pa[5] nc pe[14] pe[12] pa[9] pa[8] c d nc nc pc[15] nc ph[6] pe[4] pe[2] vdd_lv vdd_hv nc pa[6] nc pg[10] pf[14] pe[13] pa[7] d e pg[4] pg[5] pg[3] pg[2] pg[1] pg[0] pf[15] vdd_hv e f pe[0] pa[2] pa[1] pe[1] ph[0] ph[1] ph[3] ph[2] f g pe[9] pe[8] pe[10] pa[0] vss_hv vss_hv vss_hv vss_hv vdd_hv nc nc mseo g h vss_hv pe[11] vdd_hv nc vss_hv vss_hv vss_hv vss_hv mdo3 mdo2 mdo0 mdo1 h j reset vss_lv nc nc vss_hv vss_hv vss_hv vss_hv nc nc nc nc j k evti nc vdd_bv vdd_lv vss_hv vss_hv vss_hv vss_hv nc pg[12] pa[3] pg[13] k l pg[9] pg[8] nc evto pb[15] pd[15] pd[14] pb[14] l m pg[7] pg[6] pc[10] pc[11] pb[13] pd[13] pd[12] pb[12] m n pb[1] pf[9] pb[0] nc nc pa[4] vss_lv extal vdd_hv pf[0] pf[4] nc pb[11] pd[10] pd[9] pd[11] n p pf[8] nc pc[7] nc nc pa[14] vdd_lv xtal pb[10] pf[1] pf[5] pd[0] pd[3] vdd_hv _adc pb[6] pb[7] p r pf[12] pc[6] pf[10] pf[11] vdd_hv pa[15] pa[13] nc osc32k _xtal pf[3] pf[7] pd[2] pd[4] pd[7] vss_hv _adc pb[5] r t nc nc nc mcko nc pf[13] pa[12] nc osc32k _extal pf[2] pf[6] pd[1] pd[5] pd[6] pd[8] pb[4] t 12345678910111213141516 note: lbga208 available only as development package for nexus 2+. nc = not connected signal description RM0017 59/904 doc id 14629 rev 8 after power-up phase, all pads are forced to tristate with the following exceptions: pa[9] (fab) is pull-down. without external strong pull-up the device starts fetching from flash. pa[8] (abs[0]) is pull-up. reset pad is driven low. this is pull- up only after phase2 reset completion. jtag pads (tck, tms and tdi) are pull-up whilst tdo remains tristate. precise adc pads (pb[7:4] and pd[11:0]) are left tristate (no output buffer available). main oscillator pads (ext al, xtal) are tristate. nexus output pads (mdo[n], mcko, evto, mseo) are forced to output. 4.4 voltage supply pins voltage supply pins are used to provide powe r to the device. two dedicated pins are used for 1.2 v regulator stabilization. table 7. voltage supply pin descriptions port pin function pin number lqfp64 lqfp100 lqfp144 lbga208 (1) 1. lbga208 available only as development package for nexus2+ vdd_hv digital supply volt age 7, 28, 56 15, 37, 70, 84 19, 51, 100, 123 c2, d9, e16, g13, h3, n9, r5 vss_hv digital ground 6, 8, 26, 55 14, 16, 35, 69, 83 18, 20, 49, 99, 122 g7, g8, g9, g10, h1, h7, h8, h9, h10, j7, j8, j9, j10, k7, k8, k9, k10 vdd_lv 1.2v decoupling pins. decoupling capacitor must be connected between these pins and the nearest v ss_lv pin. (2) 2. a decoupling capacitor must be placed between each of t he three vdd_lv/vss_lv supply pairs to ensure stable voltage (see the recommended operating conditions in the device datasheet for details). 11, 23, 57 19, 32, 85 23, 46, 124 d8, k4, p7 vss_lv 1.2v decoupling pins. decoupling capacitor must be connected between these pins and the nearest v dd_lv pin. (2) 10, 24, 58 18, 33, 86 22, 47, 125 c8, j2, n7 vdd_bv internal regulator supply voltage 12 20 24 k3 vss_hv_adc reference ground and analog ground for the adc 33 51 73 r15 vdd_hv_adc reference voltage and analog supply for the adc 34 52 74 p14 RM0017 signal description doc id 14629 rev 8 60/904 4.5 pad types in the device the following types of pads are available for system pins and functional port pins: s = slow (b) m = medium (b) (c) f = fast (b) (c) i = input only with analog feature (b) j = input/output with analog feature x = oscillator 4.6 system pins the system pins are listed in ta b l e 8 . 4.7 functional ports the functional port pins are listed in ta bl e 9 . b. see the i/o pad electrical characteri stics in the device datasheet for details. c. all medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium (see pcr.src in section pad configuration registers (pcr0?pcr122) ). table 8. system pin descriptions system pin function i/o direction pad type reset config. pin number lqfp64 lqfp100 lqfp144 lbga208 (1) 1. lbga208 available only as dev elopment package for nexus2+ reset bidirectional reset with schmitt-trigger characteristics and noise filter. i/o m input, weak pull-up only after phase2 91721j1 extal analog output of the osc illator amplifier circuit, when the oscillator is not in bypass mode. analog input for the clock generator when the oscillator is in bypass mode. (2) 2. see the relevant section of the datasheet i/o x tristate 27 36 50 n8 xtal analog input of the oscillator amplifier circuit. needs to be grounded if oscillator is used in bypass mode. (2) i x tristate 25 34 48 p8 signal description RM0017 61/904 doc id 14629 rev 8 table 9. functional port pin descriptions port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 lqfp144 lbga208 (3) pa[0] pcr[0] af0 af1 af2 af3 ? gpio[0] e0uc[0] clkout ? wkup[19] (4) siul emios_0 cgl ? wkpu i/o i/o o ? i m tristate 5 12 16 g4 pa[1] pcr[1] af0 af1 af2 af3 ? ? gpio[1] e0uc[1] ? ? nmi (5) wkup[2] (4) siul emios_0 ? ? wkpu wkpu i/o i/o ? ? i i s tristate 4 7 11 f3 pa[2] pcr[2] af0 af1 af2 af3 ? gpio[2] e0uc[2] ? ? wkup[3] (4) siul emios_0 ? ? wkpu i/o i/o ? ? i stristate359f2 pa[3] pcr[3] af0 af1 af2 af3 ? gpio[3] e0uc[3] ? ? eirq[0] siul emios_0 ? ? siul i/o i/o ? ? i stristate436890k15 pa[4] pcr[4] af0 af1 af2 af3 ? gpio[4] e0uc[4] ? ? wkup[9] (4) siul emios_0 ? ? wkpu i/o i/o ? ? i stristate202943n6 pa[5] pcr[5] af0 af1 af2 af3 gpio[5] e0uc[5] ? ? siul emios_0 ? ? i/o i/o ? ? m tristate 51 79 118 c11 pa[6] pcr[6] af0 af1 af2 af3 ? gpio[6] e0uc[6] ? ? eirq[1] siul emios_0 ? ? siul i/o i/o ? ? i s tristate 52 80 119 d11 RM0017 signal description doc id 14629 rev 8 62/904 pa[7] pcr[7] af0 af1 af2 af3 ? gpio[7] e0uc[7] lin3tx ? eirq[2] siul emios_0 linflex_3 ? siul i/o i/o o ? i s tristate 44 71 104 d16 pa[8] pcr[8] af0 af1 af2 af3 ? n/a (6) ? gpio[8] e0uc[8] ? ? eirq[3] abs[0] lin3rx siul emios_0 ? ? siul bam linflex_3 i/o i/o ? ? i i i s input, weak pull-up 45 72 105 c16 pa[9] pcr[9] af0 af1 af2 af3 n/a (6) gpio[9] e0uc[9] ? ? fab siul emios_0 ? ? bam i/o i/o ? ? i s pull-down 46 73 106 c15 pa[10] pcr[10] af0 af1 af2 af3 gpio[10] e0uc[10] sda ? siul emios_0 i2c_0 ? i/o i/o i/o ? s tristate 47 74 107 b16 pa[11] pcr[11] af0 af1 af2 af3 gpio[11] e0uc[11] scl ? siul emios_0 i2c_0 ? i/o i/o i/o ? s tristate 48 75 108 b15 pa[12] pcr[12] af0 af1 af2 af3 ? gpio[12] ? ? ? sin_0 siul ? ? ? dspi0 i/o ? ? ? i stristate223145t7 pa[13] pcr[13] af0 af1 af2 af3 gpio[13] sout_0 ? ? siul dspi_0 ? ? i/o o ? ? mtristate213044r7 pa[14] pcr[14] af0 af1 af2 af3 ? gpio[14] sck_0 cs0_0 ? eirq[4] siul dspi_0 dspi_0 ? siul i/o i/o i/o ? i mtristate192842p6 table 9. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 lqfp144 lbga208 (3) signal description RM0017 63/904 doc id 14629 rev 8 pa[15] pcr[15] af0 af1 af2 af3 ? gpio[15] cs0_0 sck_0 ? wkup[10] (4) siul dspi_0 dspi_0 ? wkpu i/o i/o i/o ? i mtristate182740r6 pb[0] pcr[16] af0 af1 af2 af3 gpio[16] can0tx ? ? siul flexcan_0 ? ? i/o o ? ? mtristate142331n3 pb[1] pcr[17] af0 af1 af2 af3 ? ? gpio[17] ? ? ? wkup[4] (4) can0rx siul ? ? ? wkpu flexcan_0 i/o ? ? ? i i stristate152432n1 pb[2] pcr[18] af0 af1 af2 af3 gpio[18] lin0tx sda ? siul linflex_0 i2c_0 ? i/o o i/o ? m tristate 64 100 144 b2 pb[3] pcr[19] af0 af1 af2 af3 ? ? gpio[19] ? scl ? wkup[11] (4) lin0rx siul ? i2c_0 ? wkpu linflex_0 i/o ? i/o ? i i stristate111c3 pb[4] pcr[20] af0 af1 af2 af3 ? gpio[20] ? ? ? gpi[0] siul ? ? ? adc i ? ? ? i itristate325072t16 pb[5] pcr[21] af0 af1 af2 af3 ? gpio[21] ? ? ? gpi[1] siul ? ? ? adc i ? ? ? i itristate355375r16 table 9. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 lqfp144 lbga208 (3) RM0017 signal description doc id 14629 rev 8 64/904 pb[6] pcr[22] af0 af1 af2 af3 ? gpio[22] ? ? ? gpi[2] siul ? ? ? adc i ? ? ? i itristate365476p15 pb[7] pcr[23] af0 af1 af2 af3 ? gpio[23] ? ? ? gpi[3] siul ? ? ? adc i ? ? ? i itristate375577p16 pb[8] pcr[24] af0 af1 af2 af3 ? ? gpio[24] ? ? ? ans[0] osc32k_xtal (7) siul ? ? ? adc sxosc i ? ? ? i i/o itristate303953r9 pb[9] pcr[25] af0 af1 af2 af3 ? ? gpio[25] ? ? ? ans[1] osc32k_extal (7) siul ? ? ? adc sxosc i ? ? ? i i/o itristate293852t9 pb[10] pcr[26] af0 af1 af2 af3 ? ? gpio[26] ? ? ? ans[2] wkup[8] (4) siul ? ? ? adc wkpu i/o ? ? ? i i jtristate314054p9 pb[11] (8) pcr[27] af0 af1 af2 af3 ? gpio[27] e0uc[3] ? cs0_0 ans[3] siul emios_0 ? dspi_0 adc i/o i/o ? i/o i jtristate385981n13 pb[12] pcr[28] af0 af1 af2 af3 ? gpio[28] e0uc[4] ? cs1_0 anx[0] siul emios_0 ? dspi_0 adc i/o i/o ? o i jtristate396183m16 table 9. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 lqfp144 lbga208 (3) signal description RM0017 65/904 doc id 14629 rev 8 pb[13] pcr[29] af0 af1 af2 af3 ? gpio[29] e0uc[5] ? cs2_0 anx[1] siul emios_0 ? dspi_0 adc i/o i/o ? o i jtristate406385m13 pb[14] pcr[30] af0 af1 af2 af3 ? gpio[30] e0uc[6] ? cs3_0 anx[2] siul emios_0 ? dspi_0 adc i/o i/o ? o i jtristate416587l16 pb[15] pcr[31] af0 af1 af2 af3 ? gpio[31] e0uc[7] ? cs4_0 anx[3] siul emios_0 ? dspi_0 adc i/o i/o ? o i jtristate426789l13 pc[0] (9) pcr[32] af0 af1 af2 af3 gpio[32] ? tdi ? siul ? jtagc ? i/o ? i ? m input, weak pull-up 59 87 126 a8 pc[1] (9) pcr[33] af0 af1 af2 af3 gpio[33] ? tdo (10) ? siul ? jtagc ? i/o ? o ? m tristate 54 82 121 c9 pc[2] pcr[34] af0 af1 af2 af3 ? gpio[34] sck_1 can4tx (11) ? eirq[5] siul dspi_1 linflex_4 ? siul i/o i/o o ? i m tristate 50 78 117 a11 pc[3] pcr[35] af0 af1 af2 af3 ? ? ? gpio[35] cs0_1 ma[0] ? can1rx can4rx (11) eirq[6] siul dspi_1 adc ? flexcan_1 flexcan_4 siul i/o i/o o ? i i i s tristate 49 77 116 b11 table 9. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 lqfp144 lbga208 (3) RM0017 signal description doc id 14629 rev 8 66/904 pc[4] pcr[36] af0 af1 af2 af3 ? ? gpio[36] ? ? ? sin_1 can3rx (11) siul ? ? ? dspi_1 flexcan_3 i/o ? ? ? i i m tristate 62 92 131 b7 pc[5] pcr[37] af0 af1 af2 af3 ? gpio[37] sout_1 can3tx (11) ? eirq[7] siul dspi1 flexcan_3 ? siul i/o o o ? i m tristate 61 91 130 a7 pc[6] pcr[38] af0 af1 af2 af3 gpio[38] lin1tx ? ? siul linflex_1 ? ? i/o o ? ? stristate162536r2 pc[7] pcr[39] af0 af1 af2 af3 ? ? gpio[39] ? ? ? lin1rx wkup[12] (4) siul ? ? ? linflex_1 wkpu i/o ? ? ? i i stristate172637p3 pc[8] pcr[40] af0 af1 af2 af3 gpio[40] lin2tx ? ? siul linflex_2 ? ? i/o o ? ? s tristate 63 99 143 a1 pc[9] pcr[41] af0 af1 af2 af3 ? ? gpio[41] ? ? ? lin2rx wkup[13] (4) siul ? ? ? linflex_2 wkpu i/o ? ? ? i i stristate222b1 pc[10] pcr[42] af0 af1 af2 af3 gpio[42] can1tx can4tx (11) ma[1] siul flexcan_1 flexcan_4 adc i/o o o o mtristate132228m3 table 9. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 lqfp144 lbga208 (3) signal description RM0017 67/904 doc id 14629 rev 8 pc[11] pcr[43] af0 af1 af2 af3 ? ? ? gpio[43] ? ? ? can1rx can4rx (11) wkup[5] (4) siul ? ? ? flexcan_1 flexcan_4 wkpu i/o ? ? ? i i i s tristate ? 21 27 m4 pc[12] pcr[44] af0 af1 af2 af3 ? gpio[44] e0uc[12] ? ? sin_2 siul emios_0 ? ? dspi_2 i/o i/o ? ? i m tristate ? 97 141 b4 pc[13] pcr[45] af0 af1 af2 af3 gpio[45] e0uc[13] sout_2 ? siul emios_0 dspi_2 ? i/o i/o o ? s tristate ? 98 142 a2 pc[14] pcr[46] af0 af1 af2 af3 ? gpio[46] e0uc[14] sck_2 ? eirq[8] siul emios_0 dspi_2 ? siul i/o i/o i/o ? i stristate ? 3 3 c1 pc[15] pcr[47] af0 af1 af2 af3 gpio[47] e0uc[15] cs0_2 ? siul emios_0 dspi_2 ? i/o i/o i/o ? mtristate ? 4 4 d3 pd[0] pcr[48] af0 af1 af2 af3 ? gpio[48] ? ? ? gpi[4] siul ? ? ? adc i ? ? ? i i tristate ? 41 63 p12 pd[1] pcr[49] af0 af1 af2 af3 ? gpio[49] ? ? ? gpi[5] siul ? ? ? adc i ? ? ? i i tristate ? 42 64 t12 table 9. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 lqfp144 lbga208 (3) RM0017 signal description doc id 14629 rev 8 68/904 pd[2] pcr[50] af0 af1 af2 af3 ? gpio[50] ? ? ? gpi[6] siul ? ? ? adc i ? ? ? i i tristate ? 43 65 r12 pd[3] pcr[51] af0 af1 af2 af3 ? gpio[51] ? ? ? gpi[7] siul ? ? ? adc i ? ? ? i i tristate ? 44 66 p13 pd[4] pcr[52] af0 af1 af2 af3 ? gpio[52] ? ? ? gpi[8] siul ? ? ? adc i ? ? ? i i tristate ? 45 67 r13 pd[5] pcr[53] af0 af1 af2 af3 ? gpio[53] ? ? ? gpi[9] siul ? ? ? adc i ? ? ? i i tristate ? 46 68 t13 pd[6] pcr[54] af0 af1 af2 af3 ? gpio[54] ? ? ? gpi[10] siul ? ? ? adc i ? ? ? i i tristate ? 47 69 t14 pd[7] pcr[55] af0 af1 af2 af3 ? gpio[55] ? ? ? gpi[11] siul ? ? ? adc i ? ? ? i i tristate ? 48 70 r14 pd[8] pcr[56] af0 af1 af2 af3 ? gpio[56] ? ? ? gpi[12] siul ? ? ? adc i ? ? ? i i tristate ? 49 71 t15 table 9. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 lqfp144 lbga208 (3) signal description RM0017 69/904 doc id 14629 rev 8 pd[9] pcr[57] af0 af1 af2 af3 ? gpio[57] ? ? ? gpi[13] siul ? ? ? adc i ? ? ? i i tristate ? 56 78 n15 pd[10] pcr[58] af0 af1 af2 af3 ? gpio[58] ? ? ? gpi[14] siul ? ? ? adc i ? ? ? i i tristate ? 57 79 n14 pd[11] pcr[59] af0 af1 af2 af3 ? gpio[59] ? ? ? gpi[15] siul ? ? ? adc i ? ? ? i i tristate ? 58 80 n16 pd[12] (8) pcr[60] af0 af1 af2 af3 ? gpio[60] cs5_0 e0uc[24] ? ans[4] siul dspi_0 emios_0 ? adc i/o o i/o ? i j tristate ? 60 82 m15 pd[13] pcr[61] af0 af1 af2 af3 ? gpio[61] cs0_1 e0uc[25] ? ans[5] siul dspi_1 emios_0 ? adc i/o i/o i/o ? i j tristate ? 62 84 m14 pd[14] pcr[62] af0 af1 af2 af3 ? gpio[62] cs1_1 e0uc[26] ? ans[6] siul dspi_1 emios_0 ? adc i/o o i/o ? i j tristate ? 64 86 l15 pd[15] pcr[63] af0 af1 af2 af3 ? gpio[63] cs2_1 e0uc[27] ? ans[7] siul dspi_1 emios_0 ? adc i/o o i/o ? i j tristate ? 66 88 l14 table 9. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 lqfp144 lbga208 (3) RM0017 signal description doc id 14629 rev 8 70/904 pe[0] pcr[64] af0 af1 af2 af3 ? ? gpio[64] e0uc[16] ? ? can5rx (11) wkup[6] (4) siul emios_0 ? ? flexcan_5 wkpu i/o i/o ? ? i i s tristate ? 6 10 f1 pe[1] pcr[65] af0 af1 af2 af3 gpio[65] e0uc[17] can5tx (11) ? siul emios_0 flexcan_5 ? i/o i/o o ? m tristate ? 8 12 f4 pe[2] pcr[66] af0 af1 af2 af3 ? gpio[66] e0uc[18] ? ? sin_1 siul emios_0 ? ? dspi_1 i/o i/o ? ? i m tristate ? 89 128 d7 pe[3] pcr[67] af0 af1 af2 af3 gpio[67] e0uc[19] sout_1 ? siul emios_0 dspi_1 ? i/o i/o o ? m tristate ? 90 129 c7 pe[4] pcr[68] af0 af1 af2 af3 ? gpio[68] e0uc[20] sck_1 ? eirq[9] siul emios_0 dspi_1 ? siul i/o i/o i/o ? i m tristate ? 93 132 d6 pe[5] pcr[69] af0 af1 af2 af3 gpio[69] e0uc[21] cs0_1 ma[2] siul emios_0 dspi_1 adc i/o i/o i/o o m tristate ? 94 133 c6 pe[6] pcr[70] af0 af1 af2 af3 gpio[70] e0uc[22] cs3_0 ma[1] siul emios_0 dspi_0 adc i/o i/o o o m tristate ? 95 139 b5 pe[7] pcr[71] af0 af1 af2 af3 gpio[71] e0uc[23] cs2_0 ma[0] siul emios_0 dspi_0 adc i/o i/o o o m tristate ? 96 140 c4 table 9. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 lqfp144 lbga208 (3) signal description RM0017 71/904 doc id 14629 rev 8 pe[8] pcr[72] af0 af1 af2 af3 gpio[72] can2tx (12) e0uc[22] can3tx (11) siul flexcan_2 emios_0 flexcan_3 i/o o i/o o m tristate ? 9 13 g2 pe[9] pcr[73] af0 af1 af2 af3 ? ? ? gpio[73] ? e0uc[23] ? wkup[7] (4) can2rx (12) can3rx (11) siul ? emios_0 ? wkpu flexcan_2 flexcan_3 i/o ? i/o ? i i i s tristate ? 10 14 g1 pe[10] pcr[74] af0 af1 af2 af3 ? gpio[74] lin3tx cs3_1 ? eirq[10] siul linflex_3 dspi_1 ? siul i/o o o ? i s tristate ? 11 15 g3 pe[11] pcr[75] af0 af1 af2 af3 ? ? gpio[75] ? cs4_1 ? lin3rx wkup[14] (4) siul ? dspi_1 ? linflex_3 wkpu i/o ? o ? i i s tristate ? 13 17 h2 pe[12] pcr[76] af0 af1 af2 af3 ? ? gpio[76] ? e1uc[19] (13) ? sin_2 eirq[11] siul ? emios_1 ? dspi_2 siul i/o ? i/o ? i i s tristate ? 76 109 c14 pe[13] pcr[77] af0 af1 af2 af3 gpio[77] sout2 e1uc[20] ? siul dspi_2 emios_1 ? i/o o i/o ? s tristate ? ? 103 d15 pe[14] pcr[78] af0 af1 af2 af3 ? gpio[78] sck_2 e1uc[21] ? eirq[12] siul dspi_2 emios_1 ? siul i/o i/o i/o ? i s tristate ? ? 112 c13 table 9. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 lqfp144 lbga208 (3) RM0017 signal description doc id 14629 rev 8 72/904 pe[15] pcr[79] af0 af1 af2 af3 gpio[79] cs0_2 e1uc[22] ? siul dspi_2 emios_1 ? i/o i/o i/o ? m tristate ? ? 113 a13 pf[0] pcr[80] af0 af1 af2 af3 ? gpio[80] e0uc[10] cs3_1 ? ans[8] siul emios_0 dspi_1 ? adc i/o i/o o ? i j tristate ? ? 55 n10 pf[1] pcr[81] af0 af1 af2 af3 ? gpio[81] e0uc[11] cs4_1 ? ans[9] siul emios_0 dspi_1 ? i i/o i/o o ? i j tristate ? ? 56 p10 pf[2] pcr[82] af0 af1 af2 af3 ? gpio[82] e0uc[12] cs0_2 ? ans[10] siul emios_0 dspi_2 ? adc i/o i/o i/o ? i j tristate ? ? 57 t10 pf[3] pcr[83] af0 af1 af2 af3 ? gpio[83] e0uc[13] cs1_2 ? ans[11] siul emios_0 dspi_2 ? adc i/o i/o o ? i j tristate ? ? 58 r10 pf[4] pcr[84] af0 af1 af2 af3 ? gpio[84] e0uc[14] cs2_2 ? ans[12] siul emios_0 dspi_2 ? adc i/o i/o o ? i j tristate ? ? 59 n11 pf[5] pcr[85] af0 af1 af2 af3 ? gpio[85] e0uc[22] cs3_2 ? ans[13] siul emios_0 dspi_2 ? adc i/o i/o o ? i j tristate ? ? 60 p11 pf[6] pcr[86] af0 af1 af2 af3 ? gpio[86] e0uc[23] ? ? ans[14] siul emios_0 ? ? adc i/o i/o ? ? i j tristate ? ? 61 t11 table 9. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 lqfp144 lbga208 (3) signal description RM0017 73/904 doc id 14629 rev 8 pf[7] pcr[87] af0 af1 af2 af3 ? gpio[87] ? ? ? ans[15] siul ? ? ? adc i/o ? ? ? i j tristate ? ? 62 r11 pf[8] pcr[88] af0 af1 af2 af3 gpio[88] can3tx (14) cs4_0 can2tx siul flexcan_3 dspi_0 flexcan_2 i/o o o o m tristate ? ? 34 p1 pf[9] pcr[89] af0 af1 af2 af3 ? ? gpio[89] ? cs5_0 ? can2rx (15) can3rx (14) siul ? dspi_0 ? flexcan_2 flexcan_3 i/o ? o ? i i s tristate ? ? 33 n2 pf[10] pcr[90] af0 af1 af2 af3 gpio[90] ? ? ? siul ? ? ? i/o ? ? ? m tristate ? ? 38 r3 pf[11] pcr[91] af0 af1 af2 af3 ? gpio[91] ? ? ? wkup[15] (4) siul ? ? ? wkpu i/o ? ? ? i s tristate ? ? 39 r4 pf[12] pcr[92] af0 af1 af2 af3 gpio[92] e1uc[25] ? ? siul emios_1 ? ? i/o i/o ? ? m tristate ? ? 35 r1 pf[13] pcr[93] af0 af1 af2 af3 ? gpio[93] e1uc[26] ? ? wkup[16] (4) siul emios_1 ? ? wkpu i/o i/o ? ? i s tristate ? ? 41 t6 pf[14] pcr[94] af0 af1 af2 af3 gpio[94] can4tx (11) e1uc[27] can1tx siul flexcan_4 emios_1 flexcan_4 i/o o i/o o m tristate ? ? 102 d14 table 9. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 lqfp144 lbga208 (3) RM0017 signal description doc id 14629 rev 8 74/904 pf[15] pcr[95] af0 af1 af2 af3 ? ? ? gpio[95] ? ? ? can1rx can4rx (11) eirq[13] siul ? ? ? flexcan_1 flexcan_4 siul i/o ? ? ? i i i s tristate ? ? 101 e15 pg[0] pcr[96] af0 af1 af2 af3 gpio[96] can5tx (11) e1uc[23] ? siul flexcan_5 emios_1 ? i/o o i/o ? m tristate ? ? 98 e14 pg[1] pcr[97] af0 af1 af2 af3 ? ? gpio[97] ? e1uc[24] ? can5rx (11) eirq[14] siul ? emios_1 ? flexcan_5 siul i/o ? i/o ? i i s tristate ? ? 97 e13 pg[2] pcr[98] af0 af1 af2 af3 gpio[98] e1uc[11] ? ? siul emios_1 ? ? i/o i/o ? ? mtristate ? ? 8 e4 pg[3] pcr[99] af0 af1 af2 af3 ? gpio[99] e1uc[12] ? ? wkup[17] (4) siul emios_1 ? ? wkpu i/o i/o ? ? i stristate ? ? 7 e3 pg[4] pcr[100] af0 af1 af2 af3 gpio[100] e1uc[13] ? ? siul emios_1 ? ? i/o i/o ? ? mtristate ? ? 6 e1 pg[5] pcr[101] af0 af1 af2 af3 ? gpio[101] e1uc[14] ? ? wkup[18] (4) siul emios_1 ? ? wkpu i/o i/o ? ? i stristate ? ? 5 e2 pg[6] pcr[102] af0 af1 af2 af3 gpio[102] e1uc[15] ? ? siul emios_1 ? ? i/o i/o ? ? m tristate ? ? 30 m2 table 9. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 lqfp144 lbga208 (3) signal description RM0017 75/904 doc id 14629 rev 8 pg[7] pcr[103] af0 af1 af2 af3 gpio[103] e1uc[16] ? ? siul emios_1 ? ? i/o i/o ? ? m tristate ? ? 29 m1 pg[8] pcr[104] af0 af1 af2 af3 ? gpio[104] e1uc[17] ? cs0_2 eirq[15] siul emios_1 ? dspi_2 siul i/o i/o ? i/o i s tristate ? ? 26 l2 pg[9] pcr[105] af0 af1 af2 af3 gpio[105] e1uc[18] ? sck_2 siul emios_1 ? dspi_2 i/o i/o ? i/o s tristate ? ? 25 l1 pg[10] pcr[106] af0 af1 af2 af3 gpio[106] e0uc[24] ? ? siul emios_0 ? ? i/o i/o ? ? s tristate ? ? 114 d13 pg[11] pcr[107] af0 af1 af2 af3 gpio[107] e0uc[25] ? ? siul emios_0 ? ? i/o i/o ? ? m tristate ? ? 115 b12 pg[12] pcr[108] af0 af1 af2 af3 gpio[108] e0uc[26] ? ? siul emios_0 ? ? i/o i/o ? ? m tristate ? ? 92 k14 pg[13] pcr[109] af0 af1 af2 af3 gpio[109] e0uc[27] ? ? siul emios_0 ? ? i/o i/o ? ? m tristate ? ? 91 k16 pg[14] pcr[110] af0 af1 af2 af3 gpio[110] e1uc[0] ? ? siul emios_1 ? ? i/o i/o ? ? s tristate ? ? 110 b14 pg[15] pcr[111] af0 af1 af2 af3 gpio[111] e1uc[1] ? ? siul emios_1 ? ? i/o i/o ? ? m tristate ? ? 111 b13 table 9. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 lqfp144 lbga208 (3) RM0017 signal description doc id 14629 rev 8 76/904 ph[0] pcr[112] af0 af1 af2 af3 ? gpio[112] e1uc[2] ? ? sin1 siul emios_1 ? ? dspi_1 i/o i/o ? ? i m tristate ? ? 93 f13 ph[1] pcr[113] af0 af1 af2 af3 gpio[113] e1uc[3] sout1 ? siul emios_1 dspi_1 ? i/o i/o o ? m tristate ? ? 94 f14 ph[2] pcr[114] af0 af1 af2 af3 gpio[114] e1uc[4] sck_1 ? siul emios_1 dspi_1 ? i/o i/o i/o ? m tristate ? ? 95 f16 ph[3] pcr[115] af0 af1 af2 af3 gpio[115] e1uc[5] cs0_1 ? siul emios_1 dspi_1 ? i/o i/o i/o ? m tristate ? ? 96 f15 ph[4] pcr[116] af0 af1 af2 af3 gpio[116] e1uc[6] ? ? siul emios_1 ? ? i/o i/o ? ? m tristate ? ? 134 a6 ph[5] pcr[117] af0 af1 af2 af3 gpio[117] e1uc[7] ? ? siul emios_1 ? ? i/o i/o ? ? s tristate ? ? 135 b6 ph[6] pcr[118] af0 af1 af2 af3 gpio[118] e1uc[8] ? ma[2] siul emios_1 ? adc i/o i/o ? o m tristate ? ? 136 d5 ph[7] pcr[119] af0 af1 af2 af3 gpio[119] e1uc[9] cs3_2 ma[1] siul emios_1 dspi_2 adc i/o i/o o o m tristate ? ? 137 c5 ph[8] pcr[120] af0 af1 af2 af3 gpio[120] e1uc[10] cs2_2 ma[0] siul emios_1 dspi_2 adc i/o i/o o o m tristate ? ? 138 a5 table 9. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 lqfp144 lbga208 (3) signal description RM0017 77/904 doc id 14629 rev 8 ph[9] (9) pcr[121] af0 af1 af2 af3 gpio[121] ? tck ? siul ? jtagc ? i/o ? i ? s input, weak pull-up ?88127b8 ph[10] (9) pcr[122] af0 af1 af2 af3 gpio[122] ? tms ? siul ? jtagc ? i/o ? i ? s input, weak pull-up ?81120b9 1. alternate functions are chosen by setting the values of the pcr.pa bitfields inside the siul module. pcr.pa = 00 af0; pcr.pa = 01 af1; pcr.pa = 10 af2; pcr.pa = 11 af3. this is intended to select the output functions; to use one of the input functions, the pcr.ibe bit mu st be written to ?1?, regardless of the values selected in the pcr.pa bitfields. for this reason, the value corresponding to an input only function is reported as ???. 2. multiple inputs are routed to all respective modules internal ly. the input of some modules must be configured by setting the values of the psmio.padselx bitfields inside the siul module. 3. lbga208 available only as dev elopment package for nexus2+ 4. all wkup pins also support external interrupt c apability. see wakeup unit chapter for further details. 5. nmi has higher priority than alternate function. w hen nmi is selected, the pcr.af field is ignored. 6. ?not applicable? because these functions are available only wh ile the device is booting. refer to bam chapter of the reference manual for details. 7. value of pcr.ibe bit must be 0 8. be aware that this pad is used on the spc560b64l3 and spc560b64l5 to provide vdd_hv_adc and vss_hv_adc1. therefore, you should be careful in ensuring compatibility between spc560bx and spc560cx and spc560b64. 9. out of reset all the functional pins except pc[0:1 ] and ph[9:10] are available to the user as gpio. pc[0:1] are available as jtag pins (tdi and tdo respectively). ph[9:10] are available as jtag pins (tck and tms respectively). if the user configures these jtag pins in gpio mode the device is no longer compliant with ieee 1149.1-2001. 10. the tdo pad has been moved into the standby domain in order to allow low-power debug handshaking in standby mode. however, no pull-resistor is active on the tdo pad while in standby mode. at this time the pad is configured as an input. when no debugger is connected the tdo pad is floating causing a dditional current consumpti on. to avoid the extra consumption tdo must be connected. an exter nal pull-up resistor in the range of 47?100 k should be added between the tdo pin and vdd. only in case the tdo pin is used as application pin and a pull-up cannot be used then a pull-down resistor with the same value should be used between tdo pin and gnd instead. 11. available only on spc560cx ve rsions and spc560b50b2 devices 12. not available on spc560b40l3 and spc560b40l5 devices 13. not available in 100 lqfp package 14. available only on spc560b50b2 devices table 9. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 lqfp144 lbga208 (3) RM0017 signal description doc id 14629 rev 8 78/904 4.8 nexus 2+ pins in the lbga208 package, eight additional debug pins are available (see ta bl e 1 0 ). table 10. nexus 2+ pin descriptions debug pin function i/o direction pad type function after reset pin number lqfp 100 lqfp 144 lbga 208 (1) 1. lbga208 available only as development package for nexus2+ mcko message clock out o f ? ? ? t4 mdo0 message data out 0 o m ? ? ? h15 mdo1 message data out 1 o m ? ? ? h16 mdo2 message data out 2 o m ? ? ? h14 mdo3 message data out 3 o m ? ? ? h13 evti event in i m pull-up ? ? k1 evto event out o m ? ? ? l4 mseo message start/end out o m ? ? ? g16 microcontroller boot RM0017 79/904 doc id 14629 rev 8 5 microcontroller boot this chapter explains the process of booting the microcontroller. the following entities are involved in the boot process: boot assist module (bam) system status and configuration module (sscm) flash memory boot sectors (see 28, flash memory ) memory management unit (mmu) 5.1 boot mechanism this section describes the configuration required by the user, and the steps performed by the microcontroller, in order to achieve a su ccessful boot from flash memory or serial download modes. there are 2 external pins on the microcontroller that are latched during reset and used to determine whether the microcon troller will boot from flash me mory or attempt a serial download via flexcan or linflex (rs232): fab (force alternate boot mode) on pin pa[9] abs (alternate boot select) on pin pa[8] ta bl e 1 1 describes the configuration options. the microcontroller has a weak pull-down on pa[9] and a weak pull-up on pa[8]. this means that if nothing external is connected to these pins, the microcontroller will enter flash memory boot mode by default. in order to change the boot behavior, you should use external pullup or pulldown resistors on pa[9] and pa[8]. if there is any external circuitry connected to either pin, you must ensure that this does not interfere with the expected value applied to the pin at reset. otherwise, the microcontroller may boot into an unexpected mode after reset. the sscm preforms a lot of the automated boot activity including reading the latched value of the fab (pa[9]) pin to determine whether to boot from flash memory or serial boot mode. this is illustrated in figure 7 . table 11. boot mode selection mode fab pin (pa[9]) abs pin (pa[8]) flash memory boot (default mode) 0 x serial boot (linflex) 1 0 serial boot (flexcan) 1 1 RM0017 microcontroller boot doc id 14629 rev 8 80/904 figure 7. boot mode selection 5.1.1 flash memory boot in order to sucessfully boot from flash memory, you must program two 32-bit fields into one of 5 possible boot blocks as detailed below. the entities to program are: 16-bit reset configuration half word (rchw), which contains: ? a boot_id field that must be correctly set to 0x5a in order to "validate" the boot sector 32-bit reset vector (this is the start address of the user code) the location and structure of the boot sectors in flash memory are shown in figure 8 . fab (pa[9]) value? fab = 0 boot from abs (pa[8]) value? serial boot (flexcan) sscm reads latched values of pa[8] and pa[9] pins flash memory serial boot (linflex) fab = 1 abs = 0 abs = 1 microcontroller boot RM0017 81/904 doc id 14629 rev 8 figure 8. boot sector structure the rchw fields are described in ta bl e 1 2 . the sscm performs a sequential search of each boot sector (starting at sector 0) for a valid boot_id within the rchw. if a valid boot_id is found, the sscm r eads the boot vector address. if a valid boot_id is not found, the sscm starts the process of putting the microcontroller into static mode. finally, the sscm sets the e200z0h core instruction pointer to the reset vector address and starts the core running. static mode if no valid boot_id within the rchw was found, the sscm sets the cpu core instruction pointer to the bam address and the core starts to execute the code to enter static mode as follows: the core executes the "wait" instruction which halts the core. 32 kb boot sector 0 16 kb 16 kb 32 kb 0x0000_0000 0x0000_8000 0x0000_c000 0x0001_0000 code flash memory 32 kb 0x0001_8000 boot sector 1 boot sector 2 boot sector 3 boot sector 4 boot sector structure bit 0 bit 31 reserved reserved 78 1516 boot_id (0x5a) 0x0 (rchw) 0x4 32-bit reset vector (points to start address of application code) 0x8 application code (from offset 0x8 and onward) table 12. rchw field descriptions field description boot_id boot identifier. if boot_id = 0x5a, the boot sector is considered valid and bootable. RM0017 microcontroller boot doc id 14629 rev 8 82/904 the sequence is illustrated in figure 9 . figure 9. flash memory boot mode sequence alternate boot sectors some applications require an alternate boot sector so that the main boot code can be erased and reprogrammed in the field. when an alternate boot is needed, you can create two bootable sectors: the valid boot sector located at the lowest address is the main boot sector. the valid boot sector located at the next available address is the alternate boot sector. this scheme ensures that there is always one active boot sector even if the main boot sector is erased. 5.1.2 serial boot mode serial boot provides a mechanism to download and then execute code into the microcontroller sram. code may be downloaded using either flexcan or linflex (rs232). after the sscm has detected that serial boot mode has been requested, execution is transferred to the bam which handles all of the serial boot mode tasks. see section 5.2, boot assist module (bam) , for more details. sscm searches flash boot sectors for valid valid boot_id found? sscm reads reset vector address yes no boot_id (0x5a) sscm transfers execution to e200z0h core which runs bam code bam code executes wait instruction system in static mode e200z0h core starts executing code at vector address (requires reset to recover) microcontroller boot RM0017 83/904 doc id 14629 rev 8 5.1.3 censorship censorship can be enabled to protect the contents of the flash memory from being read or modified. in order to achieve this, the censorship mechanism controls access to the: jtag / nexus debug interface serial boot mode (which could otherwise be used to download and execute code to query or modify the flash memory) to re-gain access to the flash memory via jtag or serial boot, a 64-bit password must be correctly entered. caution: when censorship has been enabled, the only way to regain access is with the password. if this is forgotten or not correctly configured, then there is no way back into the device. there are two 64-bit values stored in the shadow flash which control the censorship (see table 321 for a full description): nonvolatile private censorship password registers, nvpwd0 and nvpwd1 nonvolatile system censorship cont rol registers, nvscc0 and nvscc1 censorship password registers (nvpwd0 and nvpwd1) the two private password registers combine to form a 64-bit password that should be programmed to a value known only by you. after factory test these registers are programmed as shown below: nvpwd0 = 0xfeed_face nvpwd1 = 0xcafe_beef this means that even if censorship was inadvertently enabled by writing to the censorship control registers, there is an opportunity to get back into the microcontroller using the default private password of 0xfeed_face_cafe_beef. when configuring the private password, each half word (16-bit) must contain at least one "1" and one "0". some exampl es of legal and illegal passwords are shown in ta b l e 1 3 : in uncensored devices it is possible to down load code via linflex or flexcan (serial boot mode) into internal sram even if the 64-bit private password stored in the flash and provided during the boot sequence is a password that does not conform to the password rules. nonvolatile system censorship control registers (nvscc0 and nvscc1) these registers are used together to define the censorship configuration. after factory test these registers are programmed as shown below which disables censorship: nvscc0 = 0x55aa_55aa nvscc1 = 0x55aa_55aa table 13. examples of legal and illegal passwords legal (valid) passwords illegal (invalid) passwords 0x0001_0001_0001_0001 0xfffe_fffe_fffe_fffe 0x1xxx_x2xx_xx4x_xxx8 0x0000_xxxx_xxxx_xxxx 0xffff_xxxx_xxxx_xxxx RM0017 microcontroller boot doc id 14629 rev 8 84/904 each 32-bit register is split into an upper and lower 16-bit field. the upper 16 bits (the sc field) are used to control serial boot mode censorship. the lower 16 bits (the cw field) are used to control flash memory boot censorship. caution: if the contents of the shadow flash memory are erased and the nvscc0,1 registers are not re-programmed to a valid valu e, the microcontroller will be permanently censored with no way for you to regain access. a microcontroller in this state cannot be debugged or re- flashed. censorship configuration the steps to configuring censorship are: 1. define a valid 64-bit password that conforms to the password rules. 2. using the table and flow charts below, decide what level of censorship you require and configure the nvscc0,1 values. 3. re-program the shadow flash memory and nvpwd0,1 and nvscc0,1 registers with your new values. a por is required before these will take effect. caution: if (nvscc0 and nvscc1 do not match) or (either nvscc0 or nvscc1 is not set to 0x55aa) then the microcontroller will be permanently censored wit h no way to get back in. ta bl e 1 4 shows all the possible modes of censorship. the red shaded areas are to be avoided as these show the configuration for a device that is permanently locked out. if you wish to enable censorship with a private password there is only one valid configuration ? to modify the cw field in both nvscc0,1 registers so they match but do not equal 0x55aa. this will allow you to enter the private passwo rd in both serial and flash boot modes. table 14. censorship configuration and truth table boot configuration serial censorship control word (nvscc n [sc]) censorship control word (nvscc n [cw]) internal flash memory state nexus state serial password jtag password fab pin state control options 0 (flash memory boot) uncensored 0xxxxx and nvscc0 == nvscc1 0x55aa and nvscc0 == nvscc1 enabled enabled n/a private flash memory password and censored 0x55aa and nvscc0 == nvscc1 !0x55aa and nvscc0 == nvscc1 enabled enabled with password nvpwd 1,0 (sscm reads flash memory (1) ) censored with no password access (lockout) !0x55aa !0x55aa enabled disabled n/a or nvscc0 != nvscc1 microcontroller boot RM0017 85/904 doc id 14629 rev 8 the flow charts in figure 10 and figure 11 provide a way to quickl y check what will happen with different configurations of the nvscc0,1 registers as well as detailing the correct way to enter the serial password. in the password examples, assume the 64-bit password has been programmed into the shadow flash memory in the order {nvpwd0, nwpwd1} and has a value of 0x01234567_89abcdef. 1 (serial boot) private flash memory password and uncensored 0x55aa and nvscc0 == nvscc1 enabled enabled nvpwd 0,1 (bam reads flash memory 1 ) private flash memory password and censored 0x55aa and nvscc0 == nvscc1 !0x55aa and nvscc0 == nvscc1 enabled disabled nvpwd 1,0 (sscm reads flash memory 1 ) public password and uncensored !0x55aa and nvscc0 != nvscc1 0x55aa and nvscc0 != nvscc1 enabled enabled public (0xfeed_fa ce_cafe_b eef) public password and censored (lockout) !0x55aa disabled disabled public (0xfeed_fa ce_cafe_b eef) or nvscc0 != nvscc1 = microcontroller permanently locked out = not applicable 1. when the sscm reads the passwords from flash memory, the nvpwd0 and nvpwd1 password order is swapped, so you have to submit the 64-bit password as {nvpwd1, nvpwd0}. table 14. censorship configuration and truth table (continued) boot configuration serial censorship control word (nvscc n [sc]) censorship control word (nvscc n [cw]) internal flash memory state nexus state serial password jtag password fab pin state control options RM0017 microcontroller boot doc id 14629 rev 8 86/904 figure 10. censorship control in flash memory boot mode fab = 0 (flash boot mode) nvscc0 != nvscc1 ? true censored with no password access (locked out) jtag password details: enter password as {nvpwd 1 , nvpwd 0 } false false false both sc and cw != 0x55aa cw != 0x55aa ? ? true censored with no password access (locked out) true censored with private password over jtag uncensored example ? 0x89abcdef_01234567 note: sc = 0x55aa microcontroller boot RM0017 87/904 doc id 14629 rev 8 figure 11. censorship control in serial boot mode 5.2 boot assist module (bam) the bam consits of a block of rom at address 0xffff_c000 containing vle firmware. the bam provides 2 main functions: manages the serial download (flexcan or linflex protocols supported) including support for a serial password if censorship is enabled places the microcontroller into static mode if flash memory boot mode is selected and a valid boot_id is not located in one of the boot sectors by the sscm 5.2.1 bam software flow figure 12 illustrates the bam logic flow. fab = 1 (serial boot mode) nvscc0 != nvscc1 ? true censored with no password access (locked out) serial password details: enter public password 0xfeedface_cafebeef false false false both sc and cw != 0x55aa sc != 0x55aa ? ? true censored with no password access (locked out) true note: cw = 0x55aa false cw != 0x55aa ? true note: sc = 0x55aa public password, uncensored flash (private) password, censored flash (private) password, uncensored enter password as {nvpwd 1 , nvpwd 0 } example ? 0x89abcdef_01234567 enter password as {nvpwd 0 , nvpwd 1 } example ? 0x01234567_89abcdef RM0017 microcontroller boot doc id 14629 rev 8 88/904 figure 12. bam logic flow the initial (reset) device configuration is saved including the mode and clock configuration. this means that the serial download software running in the bam can make changes to the modes and clocking and then restore these to the default values before running the newly downloaded application code from the sram. the sscm_status[bmode] field indicates which boot mode is to be executed (see ta bl e 1 5 ). this field is only updated during reset. there are 2 conditions where the boot mode is not considered valid and the bam pushes the microcontroller into static mode after restoring the default configuration: bmode = 011 (flash memory boot mode). this means that the sscm has been unable to find a valid boot_id in the boot sectors so has called the bam bmode = reserved in static mode a wait instruction is executed to halt the core. for the flexcan and linflex serial boot modes, the respective area of bam code is executed to download the code to sram. no restore default configuration configuration save default bam entry 0xffff_c000 boot mode valid? download new code and save in sram restore default configuration execute new code static mode ye s check boot mode at sscm_status[bmode] microcontroller boot RM0017 89/904 doc id 14629 rev 8 after the code has been downloaded to sram, the bam code restores the initial device configuration and then transfers execution to the start address of the downloaded code. bam resources the bam uses/initializes the following mcu resources: mc_me and mc_cgm to initialize mode and clock sources flexcan_0, linflex _0 and the respective i/ o pins when performing serial boot mode sscm and shadow flash memory (nvpwd0,1 and nvscc0,1) during password check sscm to check the boot mode (see ta b l e 1 5 ) 4?16 mhz fast external crystal oscillator the system clock is selected directly from t he 4?16 mhz fast external crystal oscillator. thus, the external oscillator fr equency defines the baud rates used for serial download (see ta bl e 1 6 ). download and execute the new code from a high level perspective, the download protocol follows these steps: 1. send the 64-bit password. 2. send the start address, size of code to be downloaded (in bytes) and the vle bit (d) . 3. download the code. each step must be completed before the next step starts. after the download is complete (the specified number of bytes is downloaded), the code executes from the start address. table 15. sscm_status[bmode] values as used by bam bmode value corresponding boot mode 000 reserved 001 flexcan_0 serial boot loader 010 linflex_0 (rs232 /uart) serial boot loader 011 flash memory boot mode 100?111 reserved table 16. serial boot mode ? baud rates fxosc frequency (mhz) linflex baud rate (baud) can bit rate (bit/s) f fxosc f fxosc /833 f fxosc /40 8 9600 200k 12 14400 300k 16 19200 400k d. since the device supports only vle code and not b ook e code, this flag is used only for backward compatibility. RM0017 microcontroller boot doc id 14629 rev 8 90/904 the communication is done in half duplex ma nner, whereby the transmission from the host is followed by the microcontroller transmission mirroring the transmission back to the host: host sends data to th e microcontroller and waits for a response. mcu echoes to host the data received. host verifies if echo is correct: ? if data is correct, the host can continue to send data. ? if data is not correct, the host stops transmission and the microcontroller enters static mode. all multi-byte data structures are sent with msb first. a more detailed description of these steps follows. censorship mode detection and serial password validation before the serial download can commence, the bam code must determine which censorship mode the microcontroller is in and which password to use. it does this by reading the pub and sec fields in the sscm status register (see section , system status register (sscm_status) ) as shown in ta b l e 1 7 . when censorship is enabled, the flash memory cannot be read by application code running in the bam or in the sram. this means that the private password in the shadow flash memory cannot be read by the bam code. in this case the sscm is used to obtain the private password from the flash memory of the censored device. when the sscm reads the private password it inverts the order of {nvpwd 0 , nwpwd 1 } so the password entered over the serial download needs to be {nvpwd 1 , nvpwd 0 }. table 17. bam censorship mode detection sscm_status register fields mode password comparison pub sec 1 0 uncensored, public pass word 0xfeed_face_cafe_beef 0 0 uncensored, private password nvpwd 0,1 from flash memory via bam 0 1 censored, private password nvpwd 1,0 from flash memory via sscm microcontroller boot RM0017 91/904 doc id 14629 rev 8 figure 13. bam censorship mode detection the first thing to be downloaded is the 64-bit password. if the password does not match the stored password, then the bam code pushes the microcontroller into static mode. the way the password is compared with either the public or private password (depending on mode) varies depending on whether censorship is enabled as described in the following subsections. censorship disabled (private or public passwords): 1. if the public password is used, the bam code does a direct comparison between the serial password and 0xfeed_face_cafe_beef. 2. if the private password is used, the bam code does a direct comparison between the serial password and the private password in flash memory, {nvpwd 0 , nvpwd 1 }. 3. if the password does not match, the bam code immediately terminates the download and pushes the microcontroller into static mode. yes bam code is being executed (serial boot mode) no no pub = 1 ? yes start serial download with password sscm_status register pub and sec bits are read sec = 1 ? public password, uncensored, bam can directly check password private password, censored, sscm needed to check password private password, uncensored, bam can directly check password public password mode is censorship enabled bam tasks applicable password ? ? RM0017 microcontroller boot doc id 14629 rev 8 92/904 censorship enabled (private password) 1. since the flash is secured, the sscm is required to read the private password. 2. the bam code writes the serial password to the sscm_pwcmph and sscm_pwcmpl registers. 3. the bam code then continues with the serial download (start address, data size and data) until all the data has been copied to the sram. 4. in the meantime the sscm has compared the private password in flash with the serial download password the bam code wrote into sscm_pwcmph and sscm_pwcmpl. 5. if the sscm obtains a match in the passwords, the censorship is temporarily disabled (until the next reset). 6. the sscm updates the status of the security (sec) bit to reflect whether the passwords matched (sec = 0) or not (sec = 1) 7. finally, the bam code reads sec. if sec = 0, execution is transferred to the code in the sram. if sec = 1, the bam code forces the microcontroller into static mode. figure 14 shows this in more detail. microcontroller boot RM0017 93/904 doc id 14629 rev 8 figure 14. bam serial boot mode flow fo r censorship enabled and private password with linflex, any receive error will result in static mode. with flexcan, the host will re- transmit data if there has been no acknowledgment from the microcontroller. however there could be a situation where the receiver configuration has an error which would result in static mode entry. censorship enabled, private password, bam running yes bam reads sscm_status[sec] serial password received is sec bit cleared bam tasks sscm tasks serial boot mode bam writes received password to sscm registers upper 32-bits to sscm_pwcmph lower 32-bits to sscm_pwcmpl start address and data data download received and copied to sram ? bam code pushes microcontroller into static mode if any frame is received incorrectly, bam code pushes device into static mode if passwords match, un-censor device until next por update sscm_status[sec] bit with censorship state sscm compares registers to private password in flash sscm_pwcmph to nvpwd1 sscm_pwcmpl to nvpwd0 no bam code transfers execution to user code in sram length received RM0017 microcontroller boot doc id 14629 rev 8 94/904 note: in a censored device booting with serial boot mode, it is possible to read the content of the four 32-bit flash memory locations that make up the boot sector. for example, if the rchw is stored at address 0x0000_0000, the reads at address 0x0000_0000, 0x0000_0004, 0x0000_0008 and 0x0000_000c will return a correct value. no other flash memory locations can be read. download start address, vle bit and code size the next 8 bytes received by the microcontroller contain a 32-bit start address, the vle mode bit and a 31-bit code length as shown in figure 15 . the vle bit (variable length instruction) is used to indicate whether the code to be downloaded is book vle or book iii-e. this device family supports only vle = 1; the bit is used for backward compatibility. the start address defines where the received data will be stored and where the mcu will branch after the download is finished. the start address is 32-bit word aligned and the 2 least significant bits are ignored by the bam code. note: the start address is configurable, but most not lie within the 0x4000_0000 to 0x4000_00ff address range. the length defines how many data bytes have to be loaded. download data each byte of data received is stored in the microcontroller?s sram, starting from the address specified in the previous protocol step. the address increments until the number of bytes of data received matches the number of bytes specified by the code length. since the sram is protected by 32-bit wide error correction code (ecc), the bam code always writes bytes into sram grouped into 32-bit words. if the last byte received does not fall onto a 32-bit boundary, the bam code fills any additional bytes with 0x0. since the ecc on the sram has not been initialized (except for the bytes of data that have just been downloaded), an additional dummy word of 0x0000_0000 is written at the end of the downloaded data block to avoid any ecc errors during core prefetch. execute code the bam code waits for the last data byte to be received. if the operating mode is censored with a private password, then the bam reads the sscm status register to determine start_address[31:16] start_address[15:0] vle code_length[30:16] code_length[15:0] figure 15. start address, vle bit and download size in bytes microcontroller boot RM0017 95/904 doc id 14629 rev 8 whether the serial password matched the private password. if there was a password match then the bam code restores the initial configuration and transfers execution to the downloaded code start address in sram. if the passwords did not match, the bam code forces a static mode entry. note: the watchdog is disabled at the start of bam code execution. in the case of an unexpected issue during bam code execution, the microcontroller may be stalled and an external reset required to recover the microcontroller. 5.2.2 linflex (rs232) boot configuration boot according to the linflex boot mode download protocol (see section , protocol ) is performed by the linflex_0 module in uart (rs232) mode. pins used are: lin0tx mapped on pb[2] lin0rx mapped on pb[3] boot from linflex uses the system clock driv en by the 4?16 mhz external crystal oscillator (fxosc). the linflex controller is configured to operate at a baud rate = system clock frequency/833, using an 8-bit data frame without parity bit and 1 stop bit. figure 16. linflex bit timing in uart mode protocol ta bl e 1 8 summarizes the protocol and bam action during this boot mode. d1 d2 d3 d4 d5 d6 d7 d0 byte field start bit stop bit table 18. uart boot mode download protocol protocol step host sent message bam response message action 1 64-bit password (msb first) 64-bit password password checked for validity and compared against stored password. 2 32-bit store address 32-bit store addres s load address is stored for future use. 3 vle bit + 31-bit number of bytes (msb first) vle bit + 31-bit number of bytes (msb first) size of download are stored for future use. verify if vle bit is set to 1 RM0017 microcontroller boot doc id 14629 rev 8 96/904 5.2.3 flexcan boot configuration boot according to the flexcan boot mode download protocol (see section , protocol ) is performed by the flexcan_0 module. pins used are: can0tx mapped on pb[0] can0rx mapped on pb[1] note: when the serial download via flexcan is selected and the device is part of a can network, the serial download may stop unexpectedly if there is any other traffic on the network. to avoid this situation, ensure that no other ca n device on the network is active during the serial download process. boot from flexcan uses the system clock driven by the 4?16 mhz fast external crystal oscillator. the flexcan controller is configured to operate at a baud rate = system clock frequency/40 (see ta b l e 1 6 for examples of baud rate). it uses the standard 11-bit identifier format detailed in flexcan 2.0a specification. flexcan controller bit timing is programmed with 10 time quanta, and the sample point is 2 time quanta before the end, as shown in figure 17 . 4 8 bits of raw binary data 8 bits of raw binary data 8-bit data are packed into a 32-bit word. this word is saved into sram starting from the ?load address?. ?load address? increments until the number of data received and stored matches the size as specified in the previous step. 5 none none branch to downloaded code table 18. uart boot mode download protocol protocol step host sent message bam response message action microcontroller boot RM0017 97/904 doc id 14629 rev 8 figure 17. flexcan bit timing protocol ta bl e 1 9 summarizes the protocol and bam action during this boot mode. all data are transmitted byte wise. sync_seg time segment 1 time segment 2 sample point nrz signal transmit point 1 time quantum time quanta time quanta 7 2 1 bit time 1 time quantum = 4 system clock periods table 19. flexcan boot mode download protocol protocol step host sent message bam response message action 1 can id 0x011 + 64-bit password can id 0x001 + 64-bit password password checked for validity and compared against stored password 2 can id 0x012 + 32- bit store address + vle bit + 31-bit number of bytes can id 0x002 + 32- bit store address + vle bit + 31-bit number of bytes load address is stored for future use. size of download are stored for future use. verify if vle bit is set to 1 3 can id 0x013 + 8 to 64 bits of raw binary data can id 0x003 + 8 to 64 bits of raw binary data 8-bit data are packed into 32-bit words. these words are saved into sram starting from the ?load address?. ?load address? increments until the number of data received and stored matches the size as specified in the previous step. 5 none none branch to downloaded code RM0017 microcontroller boot doc id 14629 rev 8 98/904 5.3 system status and co nfiguration module (sscm) 5.3.1 introduction the primary purpose of the sscm is to provide information about the current state and configuration of the system that may be useful for configuring application software and for debug of the system. on microcontrollers with a separate standby power domain, the system status block is part of that domain. figure 18. sscm block diagram 5.3.2 features the sscm includes these features: system configuration and status ? memory sizes/status ? microcontroller mode and security status (including censorship and serial boot information) ? search code flash for bootable sector ? determine boot vector device identification information (mcu id registers) debug status port enable and selection bus and peripheral abort enable/disable bus system status and configuration module interface password comparator revid hardmacro core logic system status peripheral interface bus microcontroller boot RM0017 99/904 doc id 14629 rev 8 5.3.3 modes of operation the sscm operates identically in all system modes. 5.3.4 memory map and register description ta bl e 2 0 shows the memory map for the sscm. note that all addresses are offsets; the absolute address may be calculated by adding the specified offset to the base address of the sscm. all registers are accessible via 8-bit, 16-bit or 32-bit accesses. however, 16-bit accesses must be aligned to 16-bit boundaries, and 32-bit accesses must be aligned to 32-bit boundaries. as an example, the sscm_status register is accessible by a 16-bit read/write to address ?base + 0x0002?, bu t performing a 16-bit access to ?base + 0x0003? is illegal. system status register (sscm_status) the system status register is a read-only regi ster that reflects the current state of the system. table 20. sscm memory map address offset register location 0x00 system status register (sscm_status) on page 5-99 0x02 system memory configuration register (sscm_memconfig) on page 5-100 0x04 reserved 0x06 error configuration (sscm_error) on page 5-101 0x08 debug status port register (sscm_debugport) on page 5-102 0x0a reserved 0x0c password comparison register high word (sscm_pwcmph) on page 5-104 0x10 password comparison register low word (sscm_pwcmpl) on page 5-104 figure 19. system status register (sscm_status) offset:0x00 access: read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r0 0 0 0 nxen pub sec 0 bmode 0 0 0 0 0 w reset000000000/10/10/10 0000 table 21. sscm_status allowed register accesses access type 8-bit 16-bit 32-bit (1) 1. all 32-bit accesses must be aligned to 32-b it addresses (i.e., 0x0, 0x4, 0x8 or 0xc). read allowed allowed allowed write not allowed not allowed not allowed RM0017 microcontroller boot doc id 14629 rev 8 100/904 system memory configuration register (sscm_memconfig) the system memory configuration register is a read-only register that reflects the memory configuration of the system. table 22. sscm_status field descriptions field description nxen nexus enabled pub public serial access status. this bit indicates whether serial boot mode with public password is allowed. 1serial boot mode with public password is allowed 0serial boot mode with private flash memory password is allowed sec security status. this bit reflects the cu rrent security state of the flash memory. 1the flash memory is secured. 0the flash memory is not secured. bmode device boot mode 000 reserved 001 flexcan_0 serial boot loader 010 linflex_0 serial boot loader 011 single chip 100 reserved 101 reserved 110 reserved 111 reserved this field is only updated during reset. offset: 0x02 access: read 0123456789101112131415 r 0 0 0 0 0 prsz pvlb dtsz dvld w resetxxxxxxxxxx1xxxx1 figure 20. system memory configur ation register (sscm_memconfig) microcontroller boot RM0017 101/904 doc id 14629 rev 8 error configuration (sscm_error) the error configuration register is a read-write register that controls the error handling of the system. table 23. sscm_memconfig field descriptions field description prsz code flash size 10000 128 kb 10001 256 kb 10010 384 kb 10011 512 kb pvlb code flash available this bit identifies whether or not the on-chip code fl ash is available in the system memory map. the flash may not be accessible due to security limitati ons, or because there is no flash in the system. 1 code flash is available 0 code flash is not available dtsz data flash size 0000 no data flash 0011 64 kb dvld data flash valid this bit identifies whethe r or not the on-chip data flash is vi sible in the system memory map. the flash may not be accessible due to security limitati ons, or because there is no flash in the system. 1 data flash is visible 0 data flash is not visible table 24. sscm_memconfig allowed register accesses access type 8-bit 16-bit 32-bit read allowed allowed allowed (also reads sscm_status register) write not allowed not allowed not allowed offset: 0x06 access: read/write 0123456789101112131415 r00000000000000 pa e r a e w reset0000000000000000 figure 21. error configuration (sscm_error) RM0017 microcontroller boot doc id 14629 rev 8 102/904 debug status port register (sscm_debugport) the debug status port register is used to (optionally) provide debug data on a set of pins. table 25. sscm_error field descriptions field description pa e peripheral bus abort enable this bit enables bus aborts on any access to a peripheral slot that is not used on the device. this feature is intended to aid in debugging when developing application code. 1 illegal accesses to non-existing peripherals produce a prefetch or data abort exception 0 illegal accesses to non-existing peripherals do not produce a prefetch or data abort exception rae register bus abort enable this bit enables bus aborts on illegal accesses to off-platform peripherals. illegal accesses are defined as reads or writes to reserved addresses within the address space for a particular peripheral. this feature is intended to aid in debugging when developing application code. 1 illegal accesses to peripherals produce a prefetch or data abort exception 0 illegal accesses to peripherals do not produce a prefetch or data abort exception transfers to peripheral bus resources may be aborted even before they reach the peripheral bus (that is, at the pbridge level). in this case, bits pae and rae will have no effect on the abort. table 26. sscm_error allowed register accesses access type 8-bit 16-bit 32-bit read allowed allowed allowed write allowed allowed not allowed offset: 0x08 access: read/write 0123456789101112131415 r0000000000000 debug_mode w reset0000000000000000 figure 22. debug status port register (sscm_debugport) microcontroller boot RM0017 103/904 doc id 14629 rev 8 pin[0..7] referred to in ta b l e 2 8 equates to pc[2..9] (pad 34..41). table 27. sscm_debugport field descriptions field description debug_mode debug status port mode this field selects the alternate debug functionality for the debug status port. 000 no alternate functionality selected 001 mode 1 selected 010 mode 2 selected 011 mode 3 selected 100 mode 4 selected 101 mode 5 selected 110 mode 6 selected 111 mode 7 selected ta b l e 2 8 describes the functionality of the debug status port in each mode. table 28. debug status port modes pin (1) 1. all signals are active high, unless otherwise noted mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 0 sscm_status [0] sscm_status [8] sscm_memconfig [0] sscm_memconfig [8] reserved reserved reserved 1 sscm_status [1] sscm_status [9] sscm_memconfig [1] sscm_memconfig [9] reserved reserved reserved 2 sscm_status [2] sscm_status [10] sscm_memconfig [2] sscm_memconfig [10] reserved reserved reserved 3 sscm_status [3] sscm_status [11] sscm_memconfig [3] sscm_memconfig [11] reserved reserved reserved 4 sscm_status [4] sscm_status [12] sscm_memconfig [4] sscm_memconfig [12] reserved reserved reserved 5 sscm_status [5] sscm_status [13] sscm_memconfig [5] sscm_memconfig [13] reserved reserved reserved 6 sscm_status [6] sscm_status [14] sscm_memconfig [6] sscm_memconfig [14] reserved reserved reserved 7 sscm_status [7] sscm_status [15] sscm_memconfig [7] sscm_memconfig [15] reserved reserved reserved table 29. sscm_debugport allowed register accesses access type 8-bit 16-bit 32-bit (1) 1. all 32-bit accesses must be aligned to 32-b it addresses (i.e., 0x0, 0x4, 0x8 or 0xc). read allowed allowed not allowed write allowed allowed not allowed RM0017 microcontroller boot doc id 14629 rev 8 104/904 password comparison registers these registers provide a means for the bam c ode to unsecure the device via the sscm if the password has been provided via serial download. figure 23. password comparison register high word (sscm_pwcmph) offset: 0x0c access: read/write 0123456789101112131415 r0000000000000000 w pwd_hi[31:16] reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w pwd_hi[15:0] reset0000000000000000 figure 24. password comparison register low word (sscm_pwcmpl) offset: 0x10 access: read/write 0123456789101112131415 r0000000000000000 w pwd_lo[31:16] reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w pwd_lo[15:0] reset0000000000000000 table 30. password comparison register field descriptions field description pwd_hi upper 32 bits of the password pwd_lo lower 32 bits of the password microcontroller boot RM0017 105/904 doc id 14629 rev 8 in order to unsecure the device, the password n eeds to be written as follows: first the upper word to the sscm_pwcmph register, then the lower word to the sscm_pwcmpl register. the sscm compares the 64-bit password entered into the sscm_pwcmph / sscm_pwcmpl registers with the nvpwm[1,0] private password stored in the shadow flash. if the passwords match then the sscm temporarily uncensors the microcontroller. table 31. sscm_pwcmph/l allowed register accesses access type 8-bit 16-bit 32-bit (1) 1. all 32-bit accesses must be aligned to 32-b it addresses (i.e., 0x0, 0x4, 0x8 or 0xc). read allowed allowed allowed write not allowed not allowed allowed RM0017 clock description doc id 14629 rev 8 106/904 6 clock description this chapter describes the clock architectural implementation for spc560bx and spc560cx. 6.1 clock architecture system clocks are generated from three sources: fast external crystal oscillator 4-16 mhz (fxosc) fast internal rc oscillator 16 mhz (firc) frequency modulated phase locked loop (fmpll) additionally, there are tw o low power oscillators: slow internal rc oscillator 128 khz (sirc) slow external crystal oscillator 32 khz (sxosc) the clock architecture is shown in figure 25 . clock description RM0017 107/904 doc id 14629 rev 8 figure 25. spc560bx and spc560cx system clock generation 6.2 clock gating the spc560bx and spc560cx provides the user with the possibility of gating the clock to the peripherals. ta bl e 3 2 describes for each peripheral the associated gating register address. see the me_pctln section in this reference manual. additionally, peripheral set (1, 2 or 3) frequency can be configured to be an integer (1 to 16) divided version of the main system clock. see the cgm_sc_dc0 section in this reference manual for details. fxosc firc clock monitor unit sirc reset system clock selector fmpll fxosc_div firc_div fmpll (e.g. 64 mhz) sysclk core platform peripheral set 1 peripheral set 2 swt api/rtc sxosc sxosc (32 khz) /1 to /16 /1 to /16 sxosc_div sirc_div sirc sirc firc fxosc clkout (pa0) /1, /2, /4, /8 fmpll firc fxosc clkout selector peripheral set 3 /1 to /16 /1 to /32 /1 to /32 firc_div /1 to /32 /1 to /32 sirc_clk_div sxosc_div (128 khz) (4?16 mhz) (16 mhz) safe interrupt me_ RM0017 clock description doc id 14629 rev 8 108/904 6.3 fast external crystal osc illator (fxosc) digital interface the fxosc digital interface controls the operation of the 4?16 mhz fast external crystal oscillator (fxosc). it holds control and st atus registers accessible for application. 6.3.1 main features oscillator powerdown control and stat us reporting through mc_me block oscillator clock available interrupt oscillator bypass mode output clock division factors ranging from 1, 2, 3....32 6.3.2 functional description the fxosc circuit includes an internal oscillator driver and an external crystal circuitry. it provides an output clock that can be provided to the fmpll or used as a reference clock to specific modules depending on system needs. the fxosc can be controlled by the mc_me module. the me_xxx_mc[fxoscon] bit controls the powerdown of the oscillator based on the current device mode while me_gs[s_xosc] register provides th e oscillator clock available status. after system reset, the oscillator is put into powerdown state an d software has to switch on when required. whenever the crystal oscillator is switched on from the off state, the osccnt counter starts and when it reaches the value eocv[7:0]512, the oscillator clock table 32. spc560bx and spc560cx ? peripheral clock sources peripheral register gating address offset (base = 0xc3fdc0c0) (1) 1. see the me_pctl section in th is reference manual for details. peripheral set (2) 2. ??? means undivided system clock. rpp_z0h platform none (managed through me mode) ? dspi_n 4+n (n = 0..2) 2 flexcan_n 16+n (n = 0..5) 2 adc 32 3 i 2 c441 linflex_n 48+n(n = 0..3) 1 ctu 57 3 cans 60 ? siul 68 ? wkup 69 ? emios_n 72+n (n = 0..1) 3 rtc/api 91 ? pit 92 ? cmu 104 ? clock description RM0017 109/904 doc id 14629 rev 8 is made available to the system. also, an inte rrupt pending fxosc_ctl[i_osc] bit is set. an interrupt is generated if the interrupt mask bit m_osc is set. the oscillator circuit can be bypassed by setting fxosc_ct l[oscbyp]. this bit can only be set by software. a system reset is needed to reset this bit. in this bypass mode, the output clock has the same polarity as the external clock applied on the extal pin and the oscillator status is forced to ?1?. the bypass configuration is indepe ndent of the powerdown mode of the oscillator. ta bl e 3 3 shows the truth table of diff erent oscillator configurations. the fxosc clock can be further divided by a configurable factor in the range 1 to 32 to generate the divided clock to match system requirements. this division factor is specified by fxosc_ctl[oscdiv] field. 6.3.3 register description table 33. truth table of crystal oscillator me_xxx_mc[fxoscon] fxosc_ctl[oscbyp] xtal extal fxosc oscillator mode 00 no crystal, high z no crystal, high z 0 powerdown, iddq x 1 x ext clock extal bypass, osc disabled 10 crystal crystal extal normal, osc enabled gnd ext clock extal normal, osc enabled figure 26. fast external crystal osc illator control register (fxosc_ctl) address: 0xc3fe_0000 access: special read/write 0123456789101112131415 r oscbyp (1) 1. you can read this field, and you can write a value of ?1? to it. writing a ?0? has no effect. a reset will also clear this bi t. 0000000 eocv w reset: 0000000010000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r m_osc 00 oscdiv i_osc (2) 2. you can write a value of "0" or "1" to th is field. however, writing a "1" will cl ear this field, and writing "0" will have no effect on the field value. 0000000 w reset: 0000000000000000 RM0017 clock description doc id 14629 rev 8 110/904 6.4 slow external crystal oscilla tor (sxosc) digital interface 6.4.1 introduction the sxosc digital interface controls the operation of the 32 khz slow external crystal oscillator (sxosc). it holds control and status regist ers accessible for application. 6.4.2 main features oscillator powerdown control and status oscillator bypass mode output clock division factors ranging from 1 to 32 6.4.3 functional description the sxosc circuit includes an in ternal oscillator driver and an external crystal circuitry. it can be used as a reference clock to specific modules depending on system needs. the sxosc can be controlled via the sxosc_ct l register. the oscon bit controls the powerdown while bit s_osc provides the oscillator clock available status. after system reset, the oscillator is put to powerdown state an d software has to switch on when required. whenever the sxosc is switched on from off state, the osccnt counter starts and when it reaches t he value eocv[7:0]512, the oscillator clock is made available to the system. table 34. fxosc_ctl field descriptions field description oscbyp crystal oscillator bypass. this bit specifies whether the osc illator should be bypassed or not. 0 oscillator output is used as root clock 1 extal is used as root clock eocv end of count value. these bits specify the end of coun t value to be used for comparison by the oscillator stabilization counter osccnt after reset or whenever it is switched on from the off state (osccnt runs on the fxosc). this counting period ensures that exte rnal oscillator clock signal is stable before it can be selected by the system. when oscillator counter reaches the value eocv 512, the crystal oscillator clock interrupt (i_osc) request is generated. the osccnt counter will be kept under reset if oscillator bypass mode is selected. m_osc crystal oscillator clock interrupt mask. 0 crystal oscillator clock interrupt is masked. 1 crystal oscillator clock interrupt is enabled. oscdiv crystal oscillator cl ock division factor. this field specifies the crystal osci llator output clock division factor. the output clock is divided by the factor oscdiv+1. i_osc crystal oscillator clock interrupt. this bit is set by hardware when osccnt counter reaches the count value eocv 512. 0 no oscillator clock interrupt occurred. 1 oscillator clock interrupt pending. clock description RM0017 111/904 doc id 14629 rev 8 the oscillator circuit can be by passed by writing sxosc_ctl[o scbyp] bit to ?1?. this bit can only be set by software. a system reset is n eeded to reset this bit. in this bypass mode, the output clock has the same polarity as the external clock applied on the osc32k_extal pin and the oscillator status is forced to ?1?. the bypass configuration is independent of the powerdown mode of the oscillator. ta bl e 3 5 shows the truth table of differen t configurations of the oscillator. the sxosc clock can be further divided by a configurable factor in the range 1 to 32 to generate the divided clock to match system requirements. this division factor is specified by sxosc_ctl[oscdiv] field. 6.4.4 register description table 35. sxosc truth table sxosc_ctl fields osc32k_xtal osc32k_extal sxosc oscillator mode oscon oscbyp 0 0 no crystal, high z no crystal, high z 0 powerdown, iddq x 1 x external clock osc32k_extal bypass, osc disabled 10 crystal crystal osc32k_extal normal, osc enabled ground external clock osc32k_extal normal, osc enabled figure 27. slow external crystal oscillator control register (sxosc_ctl) address: 0xc3fe_0040 access: special read/write 0123456789101112131415 r oscbyp (1) 1. you can read this field, and you can write a value of ?1? to it. writing a ?0? has no effect. a reset will also clear this bi t. 0000000 eocv w reset: 0000000010000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 0 oscdiv 000000 s_osc oscon w reset: 0000000000000000 RM0017 clock description doc id 14629 rev 8 112/904 note: the 32 khz slow external cr ystal oscillator is by default always on, but can be configured off in standby by setting the oscon bit. 6.5 slow internal rc oscillator (sirc) digital interface 6.5.1 introduction the sirc digital interface contro ls the 128 khz slow internal rc oscillator (si rc). it holds control and status registers accessible for application. 6.5.2 functional description the sirc provides a low frequency (f sirc ) clock of 128 khz requiring very low current consumption. this clock can be used as the reference clock when a fixed base time is required for specific modules. sirc is always on in all device modes exce pt standby mode. in standby mode, it is controlled by sirc_ctl[sircon_stdby] bit. the clock source status is updated in sirc_ctl[s_sirc] bit. the sirc clock can be further divided by a configurable division factor in the range from 1 to 32 to generate the divided clock to match system requirements. this division factor is specified by sirc_ctl[sircdiv] bits. the sirc output frequency can be trimmed using sirc_ctl[sirctrim]. after a power-on reset, the sirc is trimmed using a factory test value stored in test flash memory. however, after a power-on reset the test flash memory value is not visible at sirc_ctl[sirctrim] table 36. sxosc_ctl field descriptions field description oscbyp crystal oscillator bypass. this bit specifies whether the osc illator should be bypassed or not. 0 oscillator output is used as root clock. 1 osc32k_extal is us ed as root clock. eocv end of count value. this field specifies the end of count value to be used for comparison by the oscillator stabilization counter osccnt after reset or whenever it is switc hed on from the off state. this counting period ensures that external oscillator clock signal is stable before it can be selected by the system. when oscillator counter reaches the value eocv 5 12, the crystal oscillator status (s_osc) is set. the osccnt counter will be kept under re set if oscillator bypass mode is selected. oscdiv crystal oscillator cl ock division factor. this field specifies the crystal oscillator output clock division factor. the output clock is divided by the factor oscdiv + 1. s_osc crystal oscillator status. 0 crystal oscillator out put clock is not stable. 1 crystal oscillator is providing a stable clock. oscon crystal oscillator enable. 0 crystal oscillator is switched off. 1 crystal oscillator is switched on. clock description RM0017 113/904 doc id 14629 rev 8 and this field shows a value of zero. therefore, be aware that the sirc_ctl[sirctrim] does not reflect the current trim value until you have written to this field. pay particular attention to this feature when you initiate a read-modify-write operation on sirc_ctl, because a sirctrim value of zero may be unintentionally written back and this may alter the sirc frequency. in this case, you should calibrate the sirc using the cmu or be sure that you only write to the upper 16 bits of this sirc_ctl. in this oscillator, two's comple ment trimming method is implemented. so the trimming code increases from ?16 to 15. as the trimming code increases, the internal time constant increases and frequency reduces. please refer to device datasheet for average frequency variation of the trimming step. 6.5.3 register description figure 28. low power rc control register (sirc_ctl) address: 0xc3fe_0080 access: read/write 0123456789101112131415 r00000000000 sirctrim w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 0 sircdiv 000 s_sirc 000 sircon_stdby w reset: 0000001100000000 table 37. sirc_ctl field descriptions field description sirctrim sirc trimming bits. this field corresponds (via two?s complement) to a trim factor of ?16 to +15. a +1 change in sirctrim decreases the current frequency by sirctrim (see the device data sheet). a ?1 change in sirctrim increases the current frequency by sirctrim (see the device data sheet). sircdiv sirc clock division factor. this field specifies the sirc oscillator output clock division factor. the output clock is divided by the factor sircdiv+1. RM0017 clock description doc id 14629 rev 8 114/904 6.6 fast internal rc oscill ator (firc) digital interface 6.6.1 introduction the firc digital interface controls the 16 mhz fast internal rc oscillator (firc). it holds control and status registers accessible for application. 6.6.2 functional description the firc provides a high frequency (f firc ) clock of 16 mhz. this clock can be used to accelerate the exit from reset and wakeup sequence from low power modes of the system. it is controlled by the mc_me module based on the current device mode. the clock source status is updated in me_gs[s_rc]. please refer to the mc_me chapter for further details. the firc can be further divided by a configurable division factor in the range from 1 to 32 to generate the divided clock to match system requirements. this division factor is specified by rc_ctl[rcdiv] bits. the firc output frequency can be trimmed using firc_ctl[firctrim]. after a power-on reset, the firc is trimmed using a factory test value stored in test flash memory. however, after a power-on reset the test flash memory value is not visible at firc_ctl[firctrim], and this field will show a value of zero. therefore, be aware that the firc_ctl[firctrim] field does not reflect the current trim value until you have written to it. pay particular attention to this feature when you initiate a read-modify-write operation on firc_ctl, because a firctrim value of zero may be unintentionally written back and this may alter the firc frequency. in this case, you should calibrate the firc using the cmu or ensure that you write only to the upper 16 bits of this firc_ctl. in this oscillator, two's comple ment trimming method is implemented. so the trimming code increases from ?32 to 31. as the trimming code increases, the internal time constant increases and frequency reduces. please refer to device datasheet for average frequency variation of the trimming step. during standby mode entry process, the firc is controlled based on me_standby_mc[rcon] bit. this is the last step in the standby entry sequence. on any system wake-up event, the device exits standby mode and switches on the firc. the actual powerdown status of the firc when the device is in standby is provided by rc_ctl[fircon_stdby] bit. s_sirc sirc clock status. 0 sirc is not providing a stable clock. 1 sirc is providing a stable clock. sircon_stdby sirc control in standby mode. 0 sirc is switched off in standby mode. 1 sirc is switched on in standby mode. table 37. sirc_ctl field descriptions (continued) field description clock description RM0017 115/904 doc id 14629 rev 8 6.6.3 register description 6.7 frequency-modul ated phase-locked loop (fmpll) 6.7.1 introduction this section describes the features and functions of the fmpll module implemented in the device. 6.7.2 overview the fmpll enables the generation of high speed system clocks from a common 4?16 mhz input clock. further, the fmpll supports programmable frequency modulation of the system clock. the fmpll multiplication factor and output clock divider ratio are all software configurable. spc560bx and spc560cx has one fmpll that can generate the system clock and takes advantage of the fm mode. figure 29. firc oscillator co ntrol register (firc_ctl) address: 0xc3fe_0060 access: read/write 0123456789101112131415 r0000000000 firctrim w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 0 fircdiv 00000000 w reset: 0000000000000000 table 38. firc_ctl field descriptions field description firctrim firc trimming bits. this field corresponds (via two?s complement) to a trim factor of ?16 to +15. a +1 change in firctrim decreases the current frequency by firctrim (see the device data sheet). a ?1 change in sirctrim increases the current frequency by firctrim (see the device data sheet). fircdiv firc clock division factor. this field specifies the firc osc illator output clock division factor. the output clock is divided by the factor fircdiv+1. RM0017 clock description doc id 14629 rev 8 116/904 note: the user must take care not to program device with a frequency higher than allowed (no hardware check). the fmpll block diagram is shown in figure 30 . figure 30. fmpll block diagram 6.7.3 features the fmpll has the following major features: input clock frequency 4 mhz ? 16 mhz voltage controlled oscillator (vco ) range from 256 mhz to 512 mhz frequency divider (fd) for reduced frequency operation without forcing the fmpll to relock frequency modulated fmpll ? modulation enabled/disabled through software ? triangle wave modulation programmable modulation depth ? 0.25% to 4% deviation from center spread frequency (e) ? ? 0.5% to +8% deviation from down spread frequency ? programmable modulation frequency dependent on reference frequency self-clocked mode (scm) operation 4 available modes ? normal mode ? progressive clock switching ? normal mode with frequency modulation ? powerdown mode 6.7.4 memory map (f) ta bl e 3 9 shows the memory map of the fmpll. buffer charge pump low pass filter vco idf ndiv loop frequency divider odf phi fxosc e. spread spectrum should be programmed in line with maximum datasheet frequency figures. f. fmpll_x are mapped through the me_cgm register slot clock description RM0017 117/904 doc id 14629 rev 8 6.7.5 register description the fmpll operation is controlled by two registers. those registers can be accessed and written in supervisor mode only. control register (cr) table 39. fmpll memory map base address: 0xc3fe_00a0 address offset register location 0x0 control register (cr) on page 6-117 0x4 modulation register (mr) on page 6-119 figure 31. control register (cr) offset: 0x0 access: supe rvisor read/write 0123456789101112131415 r 0 0 idf odf 0 ndiv w reset0000001001000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000 en_pll_sw 0 unlock_once 0 i_lock s_lock pll_fail_mask pll_fail_flag 1 w w1c w1c reset0000000000000001 table 40. cr field descriptions field description idf the value of this field sets the fmpll input division factor as described in table 41. odf the value of this field sets the fmpll output division factor as described in ta bl e 4 2 . ndiv the value of this field sets the fmpll loop division factor as described in ta b l e 4 3 . en_pll_sw this bit is used to enable progressive clock switching. after the pll locks, the pll output initially is divided by 8, and then progressive ly decreases until it reaches divide-by-1. 0 progressive clock switching disabled. 1 progressive clock switching enabled. note: note: progressive clock switching should not be used if a non-changing clock is needed, such as for serial communications, until the division has finished. RM0017 clock description doc id 14629 rev 8 118/904 unlock_once this bit is a sticking indication of fmpll loss of lock condition. unlock_once is set when the fmpll loses lock. whenever the fmpll reacquires lock, unlock_once remains set. only a power-on reset clears this bit. i_lock this bit is set by hardware whenever there is a lock/unlock event. s_lock this bit is an indication of wh ether the fmpll has acquired lock. 0: fmpll unlocked 1: fmpll locked note: pll_fail_mask this bit is used to mask the pll_fail output. 0 pll_fail not masked. 1 pll_fail masked. pll_fail_flag this bit is asynchronously set by hardware whenever a loss of lock event occurs while fmpll is switched on. it is cleared by software writing ?1?. table 41. input divide ratios idf[3:0] input divide ratios 0000 divide by 1 0001 divide by 2 0010 divide by 3 0011 divide by 4 0100 divide by 5 0101 divide by 6 0110 divide by 7 0111 divide by 8 1000 divide by 9 1001 divide by 10 1010 divide by 11 1011 divide by 12 1100 divide by 13 1101 divide by 14 1110 divide by 15 1111 clock inhibit table 40. cr field descriptions (continued) field description clock description RM0017 119/904 doc id 14629 rev 8 modulation register (mr) table 42. output divide ratios odf[1:0] output divide ratios 00 divide by 2 01 divide by 4 10 divide by 8 11 divide by 16 table 43. loop divide ratios ndiv[6:0] loop divide ratios 0000000?0011111 ? 0100000 divide by 32 0100001 divide by 33 0100010 divide by 34 ... ... 1011111 divide by 95 1100000 divide by 96 1100001?1111111 ? figure 32. modulation register (mr) offset: 0x4 access: supervisor read/write 0123456789101112131415 r strb_bypass 0 sprd_sel mod_period w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r fm_en inc_step w reset: 0000000000000000 RM0017 clock description doc id 14629 rev 8 120/904 6.7.6 functional description normal mode in normal mode the fmpll inputs are driven by the cr. this means that, when the fmpll is in lock state, the fmpll output clock (phi) is derived by the reference clock (xosc) through this relation: table 44. mr field descriptions field description strb_bypass strobe bypass. the strb_bypass signal is used to bypass the strobe signal used inside fmpll to latch the correct values for control bits (i nc_step, mod_period and sprd_sel). 0 strobe is used to latch fmpll modulation control bits 1 strobe is bypassed. in this case control bits need to be static. the control bits must be changed only when fmpll is in powerdown mode. sprd_sel spread type selection. the sprd_sel controls the spread type in frequency modulation mode. 0 center spread 1 down spread mod_period modulation period. the mod_period field is the binary equivalent of the value modperiod derived from following formula: where: f ref : represents the frequency of the feedback divider f mod : represents the modulation frequency fm_en frequency modulation enable. the fm_en enables the frequency modulation. 0 frequency modulation disabled 1 frequency modulation enabled inc_step increment step. the inc_step field is the binary equivalent of the value incstep derived from following formula: where: md : represents the peak modulation depth in percentage (center spread -- pk-pk=+/-md, downspread -- pk-pk=-2md) mdf : represents the nominal value of loop divider (cr[ndiv]) modperiod f ref 4f mod -------------------- - = incstep round 2 15 1 ? () md mdf 100 5 modperiod ----------------------------------------------------------------- ?? ?? = phi clkin ndiv ? idf odf ? -------------------------------- - = clock description RM0017 121/904 doc id 14629 rev 8 where the value of idf, ndiv and odf are set in the cr and can be derived from ta bl e 4 1 , ta bl e 4 2 and ta bl e 4 3 . progressive clock switching progressive clock switching allows to switch the system clock to fmpll output clock stepping through different division factors. this means that the current consumption gradually increases and, in turn, volt age regulator response is improved. this feature can be enabled by programming cr[en_pll_sw] bit. when enabled, the system clock is switched to divided phi. the fmpll_clk divider is then progressively decreased to the target divider as shown in ta bl e 4 6 . figure 33. fmpll output clock division flow during progressive switching table 45. fmpll lookup table crystal frequency (mhz) fmpll output frequency (mhz) cr field values vco frequency (mhz) idf odf ndiv 8 32 0 2 32 256 64 0 2 64 512 80 0 1 40 320 16 32 1 2 32 256 64 1 2 64 512 80 1 1 40 320 40 32 4 2 32 256 64 4 2 64 512 80 3 1 32 320 table 46. progressive clock switching on pll_select rising edge number of fmpll output clock cycles fmpll_clk frequency (fmpll output clock frequency) 8 (fmpll output clock frequency)/8 16 (fmpll output cl ock frequency)/4 32 (fmpll output cl ock frequency)/2 onward fmpll output clock frequency fmpll output clock fmpll_clk division factors of 8, 4, 2 or 1 RM0017 clock description doc id 14629 rev 8 122/904 normal mode with frequency modulation the fmpll default mode is without frequency modulation enabled. when frequency modulation is enabled, however, two parameters must be set to generate the desired level of modulation: the period, and the step. the modulation waveform is always a triangle wave and its shape is not programmable. fm mode is activated in two steps: 1. configure the fm mode characteristics: mod_period, inc_step. 2. enable the fm mode by programming bit fm_en of the mr to ?1?. fm mode can only be enabled when fmpll is in lock state. there are two ways to latch these values inside the fmpll, depending on the value of bit strb_bypass in the mr. if strb_bypass is low, the modulation parame ters are latched in the fmpll only when the strobe signal goes high for at least two cycles of clkin clock. the strobe signal is automatically generated in the fmpll digital interface when the modulation is enabled (fm_en goes high) if the fmpll is locked (s_lock = 1) or when the modulation has been enabled (fm_en = 1) and fmpll enters lock state (s_lock goes high). if strb_bypass is high, the strobe signal is bypassed. in this case, control bits (mod_period[12:0], inc_step[14:0], spread_control) need to be static or hardwired to constant values. the control bits must be changed only when the fmpll is in powerdown mode. the modulation depth in % is note: the user must ensure that the product of inctep and modperiod is less than (2 15 -1). figure 34. frequency modulation modulationdepth 100 5 incstepxmodperiod 2 15 1 ? () mdf ------------------------------------------------------------------------------------------------- ?? ?? = clock description RM0017 123/904 doc id 14629 rev 8 powerdown mode to reduce consumption, the fmpll can be switched off when not required by programming the registers me_x_mc on the mc_me module. 6.7.7 recommendations to avoid any unpredictable behavior of the fmpll clock, it is recommended to follow these guidelines: the fmpll vco frequency should reside in the range 256 mhz to 512 mhz. care is required when programming the multiplication and division factors to respect this requirement. the user must change the multiplication, division factors only when the fmpll output clock is not selected as system clock. use progressive clock switching if system clock changes are required while the pll is being used as the system clock source. mod_period, inc_step, spread_sel bits should be modified before activating the fm mode. then strobe has to be generated to enable the new settings. if strb_byp is set to ?1? th en mod_period, inc_step and spread_sel can be modified only when fmpll is in powerdown mode. use progressive clock switching (fmpll output clock can be changed when it is the system clock, but only when using progressive clock switching). 6.8 clock monitor unit (cmu) 6.8.1 introduction the clock monitor unit (cmu), also referred to as clock quality checker or clock fault detector, serves two purposes. the main task is to permanently supervise the integrity of the various clock sources, for example a crys tal oscillator or fmpll. in case the fmpll leaves an upper or lower frequency boundary or the crystal oscillator fa ils it can detect and forward these kind of events towards the mc_me and mc_cgm. the clock management unit in turn can then switch to a safe mode where it uses the default safe clock source (firc), reset the device or generate the interrupt according to the system needs. it can also monitor the external crystal osc illator clock, which mu st be greater than the internal rc clock divided by a division factor given by cmu_csr[rcdiv], and generates a system clock transition request or an interrupt when enabled. the second task of the cmu is to provide a frequency meter, which allows to measure the frequency of one clock source vs. a reference clock. this is useful to allow the calibration of the on-chip rc oscillator(s), as well as being able to correct/calculate th e time deviation of a counter which is clocke d by the rc oscillator. 6.8.2 main features firc, sirc, sxosc oscillator frequency measurement using fx osc as reference clock external oscillator clock monitoring with respect to firc_clk/n clock fmpll clock frequency monitoring for a high and low frequency range with firc as reference clock event generation for various failures detected inside monitoring unit RM0017 clock description doc id 14629 rev 8 124/904 6.8.3 block diagram figure 35. clock monitor unit diagram cmu_mdr xosc supervisor fxosc < firc / n cmu_hfrefr cmu_lfrefr frequency meter cmu_fdr fmpll supervisor olr_evt fhh_fll_or_evt_a xxosc on/off from mc_me fmpll on/off from mc_me mux1 cksel1[1:0] 00 01 10 11 firc_clk firc_clk sirc_clk sxosc_clk fxosc_clk fmpll fmpll > hfref or fmpll < lfref olr_evt : it is the event signalling xosc failure when asserted. when th is signal is asserted, rgm may generate reset, interrupt or safe request based on the rgm configuration. fhh_fll_or_evt_a : it is the event signalling fmpll failure when asserted. based on the cmu_hfrefr and cmu_lfrefr configuration, if the fmpll is greater than hign frequency ra nge or less than the low frequency range configuration, this signa l is generated. when this signal is asserted, rgm may generate reset, interrupt or safe request based on the rgm configuration . clock description RM0017 125/904 doc id 14629 rev 8 6.8.4 functional description the clock and frequency names referenced in this block are defined as follows: fxosc_clk: clock coming from the fast external crystal oscillator sxosc_clk: clock coming from the slow external crystal oscillator sirc_clk: clock coming from the slow (low frequency) internal rc oscillator firc_clk: clock coming from the fast (high frequency) internal rc oscillator fmpll_clk: clock coming from the fmpll f fxosc_clk: frequency of fast extern al crystal oscillator clock f sxosc_clk : frequency of slow external crystal oscillator clock f sirc_clk : frequency of slow (low frequ ency) internal rc oscillator f firc_clk : frequency of fast (high freq uency) internal rc oscillator f fmpll_clk : frequency of fmpll clock crystal clock monitor if f fxosc_clk is less than f firc_clk divided by 2 rcdiv bits of the cmu_csr and the fxosc_clk is ?on? as signalled by the mc_me then: an event pending bit olri in cmu_isr is set. a failure event olr is signalled to the mc_r gm which in turn can automatically switch to a safe fallback clock and generate an interrupt or reset. fmpll clock monitor the f fmpll_clk can be monitored by programming bit cme of the cmu_csr register to ?1?. the fmpll_clk monitor starts as soon as bit cme is set. this monitor can be disabled at any time by writing bit cme to ?0?. if f fmpll_clk is greater than a reference value determined by bits hfref[11:0] of the cmu_hfrefr and the fmpll_ clk is ?on?, as signalle d by the mc_me, then: an event pending bit fhhi in cmu_isr is set. a failure event is signalled to the mc_rgm which in turn can generate an interrupt or safe mode request or functional reset depending on the programming model. if f fmpll_clk is less than a reference value determined by bits lfref[11:0] of the cmu_lfrefr and the fmpll_clk is ?on?, as signaled by the mc_me, then: an event pending bit fl li in cmu_isr is set. a failure event fll is signalled to the mc_rgm which in turn can generate an interrupt or safe mode request or functional reset depending on the programming model. note: the internal rc oscillator is used as reliable reference cloc k for the clock supervision. in order to avoid false events, proper programming of the dividers is required. these have to take into account the accura cy and frequency deviation of the internal rc oscillator. note: if pll frequency goes out of range, the cmu shall generate fmpll fll/fhh event. it takes approximately 5 s to generate this event. RM0017 clock description doc id 14629 rev 8 126/904 frequency meter the purpose of the frequency meter is twofold: to measure the frequency of th e oscillators sirc, firc or sxosc to calibrate an internal rc oscillator (sirc or firc) using a known frequency hint: this value can then be stored into the flash so that application software can reuse it later on. the reference clock is always the fxosc_clk. the frequency meter returns a precise value of frequencies f sxosc_clk , f firc_clk or f sirc_clk according to cksel1 bi t value. the measure starts when bit sfm (start frequency measure) in the cmu_csr is set to ?1?. the measurement duration is given by the cmu_mdr in numbers of clock cycles of the selected clock source with a width of 20 bits. bit sfm is reset to ?0? by hardware once the frequency measurement is done and the count is loaded in the cmu_fdr. the frequency f x (g) can be derived from the value loaded in the cmu_fdr as follows: equation 1 f x = (f fxosc md) / n where n is the value in the cmu_fdr and md is the value in the cmu_mdr. the frequency meter by default evaluates f firc_clk , but software can swap to f sirc_clk or f sxosc_clk by programming the cksel bits in the cmu_csr. 6.8.5 memory map and register description the memory map of the cmu is shown in ta b l e 4 7 . g. x = firc,sirc or sxosc table 47. cmu memory map base address: 0xc3fe_0100 register name address offset reset value location control status register (cmu_csr) 0x00 0x00000006 on page 6-127 frequency display register (cmu_fdr) 0x04 0x00000000 on page 6-128 high frequency reference register fmpll (cmu_hfrefr) 0x08 0x00000fff on page 6-128 low frequency reference register fmpll (cmu_lfrefr) 0x0c 0x00000000 on page 6-129 interrupt status register (cmu_isr) 0x10 0x00000000 on page 6-129 reserved 0x14 0x00000000 ? measurement duration register (cmu_mdr) 0x18 0x00000000 on page 6-130 clock description RM0017 127/904 doc id 14629 rev 8 control status register (cmu_csr) figure 36. control status register (cmu_csr) offset: 0x00 access: read/write 0123456789101112131415 r0000000 0 sfm (1) 1. you can read this field, and you can write a value of "1" to it. writing a "0" has no effect. a reset will also clear this bi t. 000 0 000 w reset000000000 0000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000 cksel1 00000 rcdiv cme_a w reset000000000 0000110 table 48. cmu_csr field descriptions field description sfm start frequency measure. the software can only set this bit to start a clock frequency measure. it is reset by hardware when the measure is ready in the cmu_fdr register. 0 frequency measurement comp leted or not yet started. 1 frequency measurement not completed. cksel1 clock oscillator selection bit. cksel1 selects the clock to be m easured by the frequency meter. 00 firc_clk selected. 01 sirc_clk selected. 10 sxosc_clk selected. 11 firc_clk selected. rcdiv rc clock division factor . these bits specify the rc clock division factor. the output clock is firc_clk divided by the factor 2 rcdiv . this output clock is used to compare with fx osc_clk for crystal clock monitor feature.the clock division coding is as follows. 00 clock divided by 1 (no division) 01 clock divided by 2 10 clock divided by 4 11 clock divided by 8 cme_a fmpll_0 clock monitor enable. 0 fmpll_0 monitor disabled. 1 fmpll_0 monitor enabled. RM0017 clock description doc id 14629 rev 8 128/904 frequency display register (cmu_fdr) . high frequency reference register fmpll (cmu_hfrefr) figure 37. frequency display register (cmu_fdr) offset: 0x04 access: read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r0000000 0 0 0 0 0 fd[19:16] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rfd[15:0] w reset0000000000000000 table 49. cmu_fdr field descriptions field description fd measured frequency bits. this register displays the measured frequency f x with respect to f fxosc . the measured value is given by the following formula: f x = (f fxosc md) / n, where n is the value in cmu_fdr register. note: x = firc, sirc or sxosc. figure 38. high frequency reference register fmpll (cmu_hfrefr) offset: 0x08 access: read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000 hfref w reset00001111 11111111 table 50. cmu_hfrefr field descriptions field description hfref high frequency reference value. this field determines the high reference value for the fmpll clock. the reference value is given by: (hfref 16) (f firc 4). clock description RM0017 129/904 doc id 14629 rev 8 low frequency reference register fmpll (cmu_lfrefr) interrupt status register (cmu_isr) figure 39. low frequency referenc e register fmpll (cmu_lfrefr) offset: 0x0c access: read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000 lfref w reset00000000 00000000 table 51. cmu_lfrefr field descriptions field description lfref low frequency reference value. this field determines the low reference value for the fmpll. the reference value is given by: (lfref 16) (f firc 4). figure 40. interrupt status register (cmu_isr) offset: 0x10 access: read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000 0 00000 fhhi flli olri w w1c w1c w1c reset00000000 00000000 table 52. cmu_isr field descriptions field description fhhi fmpll clock frequency higher than high reference interrupt. this bit is set by hardware when f fmpll_clk becomes higher than hfref value and fmpll_clk is ?on? as signalled by the mc_me. it can be cleared by software by writing ?1?. 0 no fhh event. 1 fhh event is pending. RM0017 clock description doc id 14629 rev 8 130/904 measurement duration register (cmu_mdr) flli fmpll clock frequency lower than low reference event. this bit is set by hardware when f fmpll_clk becomes lower than lfref value and fmpll_clk is ?on? as signalled by the mc_me. it can be cleared by software by writing ?1?. 0 no fll event. 1 fll event is pending. olri oscillator frequency lower than rc frequency event. this bit is set by hardware when f fxosc_clk is lower than firc_clk/2 rcdiv frequency and fxosc_clk is ?on? as signalled by the mc_me. it can be cleared by software by writing ?1?. 0 no olr event. 1 olr event is pending. table 52. cmu_isr field descriptions (continued) figure 41. measurement duration register (cmu_mdr) offset: 0x18 access: read/write 0123456789101112131415 r0000000 0 0000 md[19:16] w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r md[15:0] w reset00000000 00000000 table 53. cmu_mdr field descriptions field description md measurement duration bits. this field displays the measurement duration in numbers of clock cycles of the selected clock source. this value is loaded in the frequency meter downcounter. when cmu_csr[sfm] = 1, the downcounter starts counting. clock generation module (mc_cgm) RM0017 131/904 doc id 14629 rev 8 7 clock generation module (mc_cgm) 7.1 overview the clock generation module (mc_cgm) generates reference clocks for all soc blocks. the mc_cgm selects one of the system clock sour ces to supply the system clock. the mc_me controls the system clock selection (see the mc_me chapter for more details). a set of mc_cgm registers controls the clock dividers which are utilized for divided system and peripheral clock generation. the memory spaces of system and peripheral clock sources which have addressable memory spaces, are accessed through the mc_cgm memory space. the mc_cgm also selects and generates an output clock. figure 42 depicts the mc_cgm block diagram. RM0017 clock generation module (mc_cgm) doc id 14629 rev 8 132/904 output clock selector/divider registers platform interface core mc_cgm figure 42. mc_cgm block diagram mc_me system clock multiplexer/divider fxosc fmpll firc mapped modules interface mapped peripherals peripherals pa [ 0 ] mc_rgm clock generation module (mc_cgm) RM0017 133/904 doc id 14629 rev 8 7.2 features the mc_cgm includes the following features: generates system and peripheral clocks selects and enables/disables the system clock supply from system clock sources according to mc_me control contains a set of registers to control clock dividers for divided clock generation supports multiple clock sources and maps their address spaces to its memory map generates an output clock guarantees glitch-less clock transitions when changing the system clock selection supports 8-, 16- and 32-bit wide read/write accesses 7.3 modes of operation this section describes the basic functional modes of the mc_cgm. 7.3.1 normal and reset modes of operation during normal and reset modes of operation, the clock selection for the system clock is controlled by the mc_me. 7.4 external signal description the mc_cgm delivers an output clock to the pa[0] pin for off-chip use and/or observation. 7.5 memory map and register definition note: any access to unused registers as well as write accesses to read-only registers will: ? not change register content ? cause a transfer error table 54. mc_cgm register description address name description size access location supervisor 0xc3fe_0370 cgm_oc_en output clock enable word read/write on page 7-138 0xc3fe_0374 cgm_ocds_sc output clock division select byte read/write on page 7-138 0xc3fe_0378 cgm_sc_ss system clock select status byte read on page 7-139 0xc3fe_037c cgm_sc_dc0 system clock div ider configuration 0 byte read/write on page 7-140 0xc3fe_037d cgm_sc_dc1 system clock div ider configuration 1 byte read/write on page 7-140 0xc3fe_037e cgm_sc_dc2 system clock div ider configuration 2 byte read/write on page 7-140 RM0017 clock generation module (mc_cgm) doc id 14629 rev 8 134/904 table 55. mc_cgm memory map address name 01232756789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0xc3fe_ 0000 ? 0xc3fe_ 001c fxosc registers 0xc3fe_ 0020 ? 0xc3fe_ 003c reserved 0xc3fe_ 0040 ? 0xc3fe_ 005c sxosc registers 0xc3fe_ 0060 ? 0xc3fe_ 007c firc registers 0xc3fe_ 0080 ? 0xc3fe_ 009c sirc registers 0xc3fe_ 00a0 ? 0xc3fe_ 00bc fmpll registers 0xc3fe_ 00c0 ? 0xc3fe_ 00dc reserved 0xc3fe_ 00e0 ? 0xc3fe_ 00fc reserved 0xc3fe_ 0100 ? 0xc3fe_ 011c cmu registers clock generation module (mc_cgm) RM0017 135/904 doc id 14629 rev 8 0xc3fe_ 0120 ? 0xc3fe_ 013c reserved 0xc3fe_ 0140 ? 0xc3fe_ 015c reserved 0xc3fe_ 0160 ? 0xc3fe_ 017c reserved 0xc3fe_ 0180 ? 0xc3fe_ 019c reserved 0xc3fe_ 01a0 ? 0xc3fe_ 01bc reserved 0xc3fe_ 01c0 ? 0xc3fe_ 01dc reserved 0xc3fe_ 01e0 ? 0xc3fe_ 01fc reserved 0xc3fe_ 0200 ? 0xc3fe_ 021c reserved 0xc3fe_ 0220 ? 0xc3fe_ 023c reserved table 55. mc_cgm memory map (continued) address name 01232756789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RM0017 clock generation module (mc_cgm) doc id 14629 rev 8 136/904 0xc3fe_ 0240 ? 0xc3fe_ 025c reserved 0xc3fe_ 0260 ? 0xc3fd _c27c reserved 0xc3fe_ 0280 ? 0xc3fe_ 029c reserved 0xc3fe_ 02a0 ? 0xc3fe_ 02bc reserved 0xc3fe_ 02c0 ? 0xc3fe_ 02dc reserved 0xc3fe_ 02e0 ? 0xc3fe_ 02fc reserved 0xc3fe_ 0300 ? 0xc3fe_ 031c reserved 0xc3fe_ 0320 ? 0xc3fe_ 033c reserved 0xc3fe_ 0340 ? 0xc3fe_ 035c reserved table 55. mc_cgm memory map (continued) address name 01232756789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 clock generation module (mc_cgm) RM0017 137/904 doc id 14629 rev 8 7.5.1 register descriptions all registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. the bytes are ordered according to big endian. for example, the cgm_oc_en register may be accessed as a word at address 0xc3fe_0370, as a half-word at address 0xc3fe_0372, or as a byte at address 0xc3fe_0373. 0xc3fe_ 0360 ? 0xc3fe_ 036c reserved 0xc3fe_ 0370 cgm_oc_en r0000000000000000 w r000000000000000 en w 0xc3fe_ 0374 cgm_ocds_s c r0 0 seldiv selctl 00000000 w r0000000000000000 w 0xc3fe_ 0378 cgm_sc_ss r0000 selstat 00000000 w r0000000000000000 w 0xc3fe_ 037c cgm_sc_dc0 ?2 r de0 000 div0 de1 000 div1 w r de2 000 div2 00000000 w 0xc3fe_ 0400 ? 0xc3fe_ 3ffc reserved table 55. mc_cgm memory map (continued) address name 01232756789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RM0017 clock generation module (mc_cgm) doc id 14629 rev 8 138/904 output clock enable register (cgm_oc_en) this register is used to enable and disable the output clock. output clock division select register (cgm_ocds_sc) this register is used to select the current output clock source and by which factor it is divided before being delivered at the output clock. figure 43. output clock enable register (cgm_oc_en) address 0xc3fe_0370 access: supervisor read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000000000 en w reset0000000000000000 table 56. output clock enable regi ster (cgm_oc_en) field descriptions field description en output clock enable control 0 output clock is disabled 1 output clock is enabled figure 44. output cloc k division select register (cgm_ocds_sc) address 0xc3fe_0374 access: supervisor read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r0 0 seldiv selctl 00000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 clock generation module (mc_cgm) RM0017 139/904 doc id 14629 rev 8 system clock select status register (cgm_sc_ss) this register provides the current cloc k source selection for the following clocks: undivided: system clock divided by system clock divider 0: peripheral set 1 clock divided by system clock divider 1: peripheral set 2 clock divided by system clock divider 2: peripheral set 3 clock see figure 47 for details. table 57. output clock division select register (cgm_ocds_sc) field descriptions field description seldiv output clock division select 00 output selected output clock without division 01 output selected output clock divided by 2 10 output selected output clock divided by 4 11 output selected output clock divided by 8 selctl output clock source selection control ? this value selects the current source for the output clock. 0000 4-16 mhz ext. xtal osc. 0001 16 mhz int. rc osc. 0010 freq. mod. pll 0011 reserved 0100 reserved 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved figure 45. system clock select status register (cgm_sc_ss) address 0xc3fe_0378 access: supervisor read 0123456789101112131415 r0000 selstat 00000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 RM0017 clock generation module (mc_cgm) doc id 14629 rev 8 140/904 system clock divider configuration registers (cgm_sc_dc0 ? 2) these registers control the system clock dividers. table 58. system clock select status register (cgm_sc_ss) field descriptions field description selstat system clock source selection status ? this value indicates the current source for the system clock. 0000 16 mhz int. rc osc. 0001 div. 16 mhz int. rc osc. 0010 4-16 mhz ext. xtal osc. 0011 div. ext. xtal osc. 0100 freq. mod. pll 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 system clock is disabled figure 46. system clock divider conf iguration registers (cgm_sc_dc0?2) address 0xc3fe_037c access: supervisor read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r de0 000 div0 de1 000 div1 w reset1000000010000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r de2 000 div2 00000000 w reset1000000000000000 table 59. system clock divide r configuration registers (cgm _sc_dc0?2) field descriptions field description de0 divider 0 enable 0 disable system clock divider 0 1 enable system clock divider 0 div0 divider 0 division value ? the resultant peripheral set 1 clock will have a period div0 + 1 times that of the system clock. if the de0 is set to ?0? (divider 0 is disabled), any write access to the div0 field is ignored and the peripheral set 1 clock remains disabled. de1 divider 1 enable 0 disable system clock divider 1 1 enable system clock divider 1 clock generation module (mc_cgm) RM0017 141/904 doc id 14629 rev 8 7.6 functional description 7.6.1 system clock generation figure 47 shows the block diagram of the system clock generation logic. the mc_me provides the system clock select and switch mask (see mc_me chapter for more details), and the mc_rgm provides the safe clock requ est (see mc_rgm chapter for more details). the safe clock request forces the selector to select the 16 mhz int. rc osc. as the system clock and to ignore the system clock select. system clock source selection during normal operation, the system clock selection is controlled on a safe mode or reset event, by the mc_rgm otherwise, by the mc_me system clock disable during normal operation, the system clock can be disabled by the mc_me. system clock dividers the mc_cgm generates three derived clocks from the system clock. dividers functional description dividers are utilized for the generation of divided system and peripheral clocks. the mc_cgm has the following control registers for built-in dividers: section system clock divider config uration registers (cgm_sc_dc0?2) the reset value of all counters is ?1?. if a divider has its de bit in the respective configuration register set to ?0? (the divider is disabled), any value in its divn field is ignored. 7.6.2 output clock multiplexing the mc_cgm contains a multiplexing function for a number of clock sources which can then be utilized as output cl ock sources. the selection is done via the cgm_ocds_sc register. div1 divider 1 division value ? the resultant peripheral set 2 clock will have a period div1 + 1 times that of the system clock. if the de1 is set to ?0? (divider 1 is disabled), any write access to the div1 field is ignored and the peripheral set 2 clock remains disabled. de2 divider 2 enable 0 disable system clock divider 2 1 enable system clock divider 2 div2 divider 2 division value ? the resultant peripheral set 3 clock will have a period div2 + 1 times that of the system clock. if the de2 is set to ?0? (divider 2 is disabled), any write access to the div2 field is ignored and the peripheral set 3 clock remains disabled. table 59. system clock divider configuration registers (cgm_s c_dc0?2) field descriptions field description RM0017 clock generation module (mc_cgm) doc id 14629 rev 8 142/904 figure 47. mc_cgm system clock generation overview 16 mhz int. rc osc. 4-16 mhz ext. xtal osc. 2 div. ext. xtal osc. 3 freq. mod. pll 4 div. 16 mhz int. rc osc. 1 0 system clock ?0? system clock is disabled if me_ clock generation module (mc_cgm) RM0017 143/904 doc id 14629 rev 8 7.6.3 output clock division selection the mc_cgm provides the following output signals for the output clock generation: pa[0] (see figure 48 ). this signal is generated by utilizing one of the 3-stage ripple counter outputs or the selected signal witho ut division. the non-divided signal is not guaranteed to be 50% duty cycle by the mc_cgm. the mc_cgm also has an output clock enable register (see section output clock enable register (cgm_oc_en) ) which contains the output clock enable/disable control bit. cgm_ocds_sc.selctl cgm_ocds_sc.seldiv 0 1 2 3 register register figure 48. mc_cgm output clock multiplexer and pa[0] generation 4-16 mhz ext. xtal osc. 0 16 mhz int. rc osc. 1 freq. mod. pll 2 pa [ 0 ] ?0? cgm_oc_en register RM0017 mode entry module (mc_me) doc id 14629 rev 8 144/904 8 mode entry module (mc_me) 8.1 introduction 8.1.1 overview the mc_me controls the soc mode and mode transition sequences in all functional states. it also contains configuration, control and status registers accessible for the application. figure 49 depicts the mc_me block diagram. mode entry module (mc_me) RM0017 145/904 doc id 14629 rev 8 registers platform interface core mc_me figure 49. mc_meblock diagram mc_rgm fxosc fmpll firc mc_cgm mc_pcu peripherals flashes vreg device mode state machine wkpu RM0017 mode entry module (mc_me) doc id 14629 rev 8 146/904 8.1.2 features the mc_me includes the following features: control of the available modes by the me_me register definition of various device mode configurations by the me_ mode entry module (mc_me) RM0017 147/904 doc id 14629 rev 8 8.2 external signal description the mc_me has no connections to any external pins. 8.3 memory map and register definition the mc_me contains registers for: mode selection and status reporting mode configuration mode transition interrupts status and mask control scalable number of peripheral sub-mode selection and status reporting test this is a chip-wide service mode which is intended to provide a control environment for device self-test. it may enable the application to run its own self-test like flash checksum, memory bist etc. software request from drun system reset assertion, drun via software run0?3 these are software running modes where most processing activity is done. these various run modes allow to enable different clock & power configurations of the system with respect to each other. software request from drun , interrupt event from halt , interrupt or wakeup event from stop system reset assertion, safe via software or hardware failure, other run0?3 modes, halt , stop , standby via software halt this is a reduced-activity low-power mode during which the clock to the core is disabled. it can be configured to switch off analog peripherals like pll, flash, main regulator etc. for efficient power management at the cost of higher wakeup latency. software request from run0?3 system reset assertion, safe on hardware failure, run0?3 on interrupt event stop this is an advanced low-power mode during which the clock to the core is disabled. it may be configured to switch off most of the peripherals including oscillator for efficient power management at the cost of higher wakeup latency. software request from run0?3 system reset assertion, safe on hardware failure, run0?3 on interrupt event or wakeup event standby this is a reduced-leakage low-power mode during which power supply is cut off from most of the device. wakeup from this mode takes a relatively long time, and content is lost or must be restored from backup. software request from run0?3 , drun modes system reset assertion, drun on wakeup event table 60. mc_me mode descriptions (continued) name description entry exit table 61. mc_me register description address name description size access location supervisor 0xc3fd_c000 me_gs global status word read on page 8-155 0xc3fd_c004 me_mctl mode control word read/write on page 8-157 RM0017 mode entry module (mc_me) doc id 14629 rev 8 148/904 0xc3fd_c008 me_me mode enable word read/write on page 8-158 0xc3fd_c00c me_is interrupt status word read/write on page 8-160 0xc3fd_c010 me_im interrupt mask word read/write on page 8-161 0xc3fd_c014 me_imts invalid mode transition status word read/write on page 8-162 0xc3fd_c018 me_dmts debug mode transtion status word read on page 8-163 0xc3fd_c020 me_reset_mc reset mode configuration word read on page 8-165 0xc3fd_c024 me_test_mc test mode configuration word read/write on page 8-166 0xc3fd_c028 me_safe_mc safe mode configuration word read/write on page 8-166 0xc3fd_c02c me_drun_mc drun mode configuration word read/write on page 8-167 0xc3fd_c030 me_run0_mc run0 mode configuration word read/write on page 8-167 0xc3fd_c034 me_run1_mc run1 mode configuration word read/write on page 8-167 0xc3fd_c038 me_run2_mc run2 mode configuration word read/write on page 8-167 0xc3fd_c03c me_run3_mc run3 mode configuration word read/write on page 8-167 0xc3fd_c040 me_halt_mc halt mode configuration word read/write on page 8-168 0xc3fd_c048 me_stop_mc stop mode configuration word read/write on page 8-168 0xc3fd_c054 me_standby_mc standby mode configuration word read/write on page 8-169 0xc3fd_c060 me_ps0 peripheral status 0 word read on page 8-171 0xc3fd_c064 me_ps1 peripheral status 1 word read on page 8-171 0xc3fd_c068 me_ps2 peripheral status 2 word read on page 8-172 0xc3fd_c06c me_ps3 peripheral status 3 word read on page 8-172 0xc3fd_c080 me_run_pc0 run peripheral configuration 0 word read/write on page 8-173 0xc3fd_c084 me_run_pc1 run peripheral configuration 1 word read/write on page 8-173 ? 0xc3fd_c09c me_run_pc7 run periphera l configuration 7 word read/write on page 8-173 0xc3fd_c0a0 me_lp_pc0 low-power peripheral configuration 0 word read/write on page 8-174 0xc3fd_c0a4 me_lp_pc1 low-power peripheral configuration 1 word read/write on page 8-174 ? 0xc3fd_c0bc me_lp_pc7 low-power peripheral configuration 7 word read/write on page 8-174 0xc3fd_c0c4 me_pctl4 dspi0 control byte read/write on page 8-175 0xc3fd_c0c5 me_pctl5 dspi1 control byte read/write on page 8-175 0xc3fd_c0c6 me_pctl6 dspi2 control byte read/write on page 8-175 table 61. mc_me register description (continued) address name description size access location supervisor mode entry module (mc_me) RM0017 149/904 doc id 14629 rev 8 note: any access to unused registers as well as write accesses to read-only registers will: ? not change register content ? cause a transfer error 0xc3fd_c0d0 me_pctl16 flexcan0 control byte read/write on page 8-175 0xc3fd_c0d1 me_pctl17 flexcan1 control byte read/write on page 8-175 0xc3fd_c0d2 me_pctl18 flexcan2 control byte read/write on page 8-175 0xc3fd_c0d3 me_pctl19 flexcan3 control byte read/write on page 8-175 0xc3fd_c0d4 me_pctl20 flexcan4 control byte read/write on page 8-175 0xc3fd_c0d5 me_pctl21 flexcan5 control byte read/write on page 8-175 0xc3fd_c0e0 me_pctl32 adc0 control byte read/write on page 8-175 0xc3fd_c0ec me_pctl44 i2c0 control byte read/write on page 8-175 0xc3fd_c0f0 me_pctl48 linfle x0 control byte read/write on page 8-175 0xc3fd_c0f1 me_pctl49 linfle x1 control byte read/write on page 8-175 0xc3fd_c0f2 me_pctl50 linfle x2 control byte read/write on page 8-175 0xc3fd_c0f3 me_pctl51 linfle x3 control byte read/write on page 8-175 0xc3fd_c0f9 me_pctl57 ctu control byte read/write on page 8-175 0xc3fd_c0fc me_pctl60 cansampler control byte read/write on page 8-175 0xc3fd_c104 me_pctl68 siul control byte read/write on page 8-175 0xc3fd_c105 me_pctl69 wkpu control byte read/write on page 8-175 0xc3fd_c108 me_pctl72 emios0 control byte read/write on page 8-175 0xc3fd_c109 me_pctl73 emios1 control byte read/write on page 8-175 0xc3fd_c11b me_pctl91 rtc_api control byte read/write on page 8-175 0xc3fd_c11c me_pctl92 pit_rti control byte read/write on page 8-175 0xc3fd_c128 me_pctl104 cmu control byte read/write on page 8-175 table 61. mc_me register description (continued) address name description size access location supervisor RM0017 mode entry module (mc_me) doc id 14629 rev 8 150/904 table 62. mc_me memory map address name 0 1 2 3 27567891011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0xc3fd_ c000 me_gs r s_current_mode s_mtrans s_dc 00 s_pdo 00 s_mvr s_dfla s_cfla w r s_fmpll s_fxosc s_firc s_sysclk w 0xc3fd_ c004 me_mctl r ta r g e t _ m o d e 0000000 00000 w r1 0 1 0 0101000 01111 w key 0xc3fd_ c008 me_me r0 0 0 0 0000000 00000 w r0 0 standby 00 stop 0 halt run3 run2 run1 run0 drun safe test reset w 0xc3fd_ c00c me_is r0 0 0 0 0000000 00000 w r0 0 0 0 0000000 0 i_iconf i_imode i_safe i_mtc w w1c w1c w1c w1c 0xc3fd_ c010 me_im r0 0 0 0 0000000 00000 w r0 0 0 0 0000000 0 m_iconf m_imode m_safe m_mtc w 0xc3fd_ c014 me_imts r0 0 0 0 0000000 00000 w r0 0 0 0 0000000 s_mti s_mri s_dma s_nma s_sea w w1c w1c w1c w1c w1c mode entry module (mc_me) RM0017 151/904 doc id 14629 rev 8 0xc3fd_ c018 me_dmts r0 0 0 0 0000 mph_busy 00 pmc_prog core_dbg 00 smr w r0 fmpll_sc fxosc_sc firc_sc sysclk_sw dflash_sc cflash_sc cdp_prph_0_143 00 cdp_prph_96_127 cdp_prph_64_95 cdp_prph_32_63 cdp_prph_0_31 w 0xc3fd_ c01c reserved 0xc3fd_ c020 me_reset_m c r0 0 0 0 0000 pdo 00 mvron dflaon cflaon w r fmpllon fxoscon fircon sysclk w 0xc3fd_ c024 me_test_mc r0 0 0 0 0000 pdo 00 mvron dflaon cflaon w r0 0 0 0 00000 fmpllon fxoscon fircon sysclk w 0xc3fd_ c028 me_safe_mc r0 0 0 0 0000 pdo 00 mvron dflaon cflaon w r fmpllon fxoscon fircon sysclk w 0xc3fd_ c02c me_drun_m c r0 0 0 0 0000 pdo 00 mvron dflaon cflaon w table 62. mc_me memory map (continued) address name 0 1 2 3 27567891011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RM0017 mode entry module (mc_me) doc id 14629 rev 8 152/904 r0 0 0 0 00000 fmpllon fxoscon fircon sysclk w 0xc3fd_ c030 ? 0xc3fd_ c03c me_run0?3_ mc r0 0 0 0 0000 pdo 00 mvron dflaon cflaon w r0 0 0 0 00000 fmpllon fxoscon fircon sysclk w 0xc3fd_ c040 me_halt_mc r0 0 0 0 0000 pdo 00 mvron dflaon cflaon w r0 0 0 0 00000 fmpllon fxoscon fircon sysclk w 0xc3fd_ c044 reserved 0xc3fd_ c048 me_stop_mc r0 0 0 0 0000 pdo 00 mvron dflaon cflaon w r0 0 0 0 00000 fmpllon fxoscon fircon sysclk w 0xc3fd_ c04c ? 0xc3fd_ c050 reserved 0xc3fd_ c054 me_standby _mc r0 0 0 0 0000 pdo 00 mvron dflaon cflaon w r fmpllon fxoscon fircon sysclk w table 62. mc_me memory map (continued) address name 0 1 2 3 27567891011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 mode entry module (mc_me) RM0017 153/904 doc id 14629 rev 8 0xc3fd_ c058 ? 0xc3fd_ c05c reserved 0xc3fd_ c060 me_ps0 r s_flexcan5 s_flexcan4 s_flexcan3 s_flexcan2 s_flexcan1 s_flexcan0 w r s_dspi2 s_dspi1 s_dspi0 w 0xc3fd_ c064 me_ps1 r s_cansampler s_ctu s_linflex3 s_linflex2 s_linflex1 s_linflex0 w r s_i2c0 s_adc0 w 0xc3fd_ c068 me_ps2 r s_pit_rti s_rtc_api w r s_emios1 s_emios0 s_wkpu s_siul w 0xc3fd_ c06c me_ps3 r w r s_cmu w 0xc3fd_ c070 reserved table 62. mc_me memory map (continued) address name 0 1 2 3 27567891011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RM0017 mode entry module (mc_me) doc id 14629 rev 8 154/904 8.3.1 register description unless otherwise noted, all registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. the bytes are ordered according to big endian. for example, the me_run_pc0 register may be accessed as a word at address 0xc3fd_c080, as a half-word at address 0xc3fd_c082, or as a byte at address 0xc3fd_c083. 0xc3fd_ c074 ? 0xc3fd_ c07c reserved 0xc3fd_ c080 ? 0xc3fd_ c09c me_run_pc0 ?7 r0 0 0 0 0000000 00000 w r0 0 0 0 0000 run3 run2 run1 run0 drun safe test reset w 0xc3fd_ c0a0 ? 0xc3fd_ c0bc me_lp_pc0? 7 r0 0 0 0 0000000 00000 w r0 0 standby 00 stop 0 halt 00000000 w 0xc3fd_ c0c0 ? 0xc3fd_ c14c me_pctl0?1 43 r0 dbg_f lp_cfg run_cfg 0 dbg_f lp_cfg run_cfg w r0 dbg_f lp_cfg run_cfg 0 dbg_f lp_cfg run_cfg w 0xc3fd_ c150 ? 0xc3fd_ fffc reserved table 62. mc_me memory map (continued) address name 0 1 2 3 27567891011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 mode entry module (mc_me) RM0017 155/904 doc id 14629 rev 8 global status register (me_gs) this register contains global mode status. figure 50. global status register (me_gs) address 0xc3fd_c000 access: supervisor read 0123456789101112131415 r s_current_mode s_mtrans s_dc 00 s_pdo 00 s_mvr s_dfla s_cfla w reset0000110000011111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r s_fmpll s_fxosc s_firc s_sysclk w reset0000000000010000 table 63. global status register (me_gs) field descriptions field description s_current _mode current device mode status 0000 reset 0001 test 0010 safe 0011 drun 0100 run0 0101 run1 0110 run2 0111 run3 1000 halt 1001 reserved 1010 stop 1011 reserved 1100 reserved 1101 standby 1110 reserved 1111 reserved s_mtrans mode transition status 0 mode transition process is not active 1 mode transition is ongoing s_dc device current consumption status 0 device consumption is low enough to allow powering down of main voltage regulator 1 device consumption requires main voltage regulator to remain powered regardless of mode configuration RM0017 mode entry module (mc_me) doc id 14629 rev 8 156/904 s_pdo output power-down status ? this bit specifies output power-down status of i/os. this bit is asserted whenever outputs of pads are forced to high impedance state or the pads power sequence driver is switched off. 0 no automatic safe gating of i/os used and pads power sequence driver is enabled 1in safe / test modes, outputs of pads are forced to high impedance state and pads power sequence driver is disabled. the inputs are level unchanged. in stop mode, only pad power sequence driver is disabled but the state of the output is kept. in standby mode, the power sequence driver and all pads except those mapped on wakeup lines are not powered and therefore high impedance. wakeup lines configuration remains unchanged s_mvr main voltage regulator status 0 main voltage regulator is not ready 1 main voltage regulator is ready for use s_dfla data flash availability status 00 data flash is not available 01 data flash is in power-down mode 10 data flash is in low-power mode 11 data flash is in normal mode and available for use s_cfla code flash availability status 00 code flash is not available 01 code flash is in power-down mode 10 code flash is in low-power mode 11 code flash is in normal mode and available for use s_fmpll frequency modulated phase locked loop status 0 frequency modulated phase locked loop is not stable 1 frequency modulated phase locked loop is providing a stable clock s_fxosc fast external crystal oscillator (4-16 mhz) status 0 fast external crystal oscillator (4-16 mhz) is not stable 1 fast external crystal oscillator (4-16 mhz) is providing a stable clock s_firc fast internal rc oscillator (16 mhz) status 0 fast internal rc oscillator (16 mhz) is not stable 1 fast internal rc oscillator (16 mhz) is providing a stable clock s_sysclk system clock switch status ? these bits specify the system cl ock currently used by the system. 0000 16 mhz int. rc osc. 0001 div. 16 mhz int. rc osc. 0010 4-16 mhz ext. xtal osc. 0011 div. ext. xtal osc. 0100 freq. mod. pll 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 system clock is disabled table 63. global status register (m e_gs) field descriptions (continued) field description mode entry module (mc_me) RM0017 157/904 doc id 14629 rev 8 mode control register (me_mctl) this register is used to trigger software-controlled mode changes. depending on the modes as enabled by me_me register bits, configurations corresponding to unavailable modes are reserved and access to me_ RM0017 mode entry module (mc_me) doc id 14629 rev 8 158/904 mode enable register (me_me) this register allows a way to disable the device modes which are not required for a given device. reset , safe , drun , and run0 modes are always enabled. table 64. mode control register (me_mctl) field descriptions field description ta r g e t _ m ode target device mode ? these bits provide the target device mode to be entered by software programming. the mechanism to enter into any mode by software requires the write operation twice: first time with key, and second time with in verted key. these bits ar e automatically updated by hardware while entering safe on hardware request. also, while exiting from the halt and stop modes on hardware exit events, these are updated with the appropriate run0?3 mode value. 0000 reset 0001 test 0010 safe 0011 drun 0100 run0 0101 run1 0110 run2 0111 run3 1000 halt 1001 reserved 1010 stop 1011 reserved 1100 reserved 1101 standby 1110 reserved 1111 reserved key control key ? these bits enable write access to this register. any write access to the register with a value different from the keys is ignored. read access will always return inverted key. key: 0101101011110000 (0x5af0) inverted key: 1010010100001111 (0xa50f) figure 52. mode enable register (me_me) address 0xc3fd_c008 access: supervisor read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 standby 00 stop 0 halt run3 run2 run1 run0 drun safe test reset w reset0000000000011101 mode entry module (mc_me) RM0017 159/904 doc id 14629 rev 8 table 65. mode enable regist er (me_me) field descriptions field description standby standby mode enable 0 standby mode is disabled 1 standby mode is enabled stop stop mode enable 0 stop mode is disabled 1 stop mode is enabled halt halt mode enable 0 halt mode is disabled 1 halt mode is enabled run3 run3 mode enable 0 run3 mode is disabled 1 run3 mode is enabled run2 run2 mode enable 0 run2 mode is disabled 1 run2 mode is enabled run1 run1 mode enable 0 run1 mode is disabled 1 run1 mode is enabled run0 run0 mode enable 0 run0 mode is disabled 1 run0 mode is enabled drun drun mode enable 0 drun mode is disabled 1 drun mode is enabled safe safe mode enable 0 safe mode is disabled 1 safe mode is enabled test test mode enable 0 test mode is disabled 1 test mode is enabled reset reset mode enable 0 reset mode is disabled 1 reset mode is enabled RM0017 mode entry module (mc_me) doc id 14629 rev 8 160/904 interrupt status register (me_is) this register provides the current interrupt status. figure 53. interrupt st atus register (me_is) address 0xc3fd_c00c access: supervisor read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000000 i_iconf i_imode i_safe i_mtc w w1c w1c w1c w1c reset0000000000000000 table 66. interrupt status register (me_is) field descriptions field description i_iconf invalid mode configuration interrupt ? this bit is set whenever a write operation to me_ mode entry module (mc_me) RM0017 161/904 doc id 14629 rev 8 interrupt mask register (me_im) this register controls whether an event generates an interrupt or not. figure 54. interrupt mask register (me_im) address 0xc3fd_c010 access: supervisor read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000000 m_iconf m_imode m_safe m_mtc w reset0000000000000000 table 67. interrupt mask regist er (me_im) field descriptions field description m_iconf invalid mode configuration interrupt mask 0 invalid mode interrupt is masked 1 invalid mode interrupt is enabled m_imode invalid mode interrupt mask 0 invalid mode interrupt is masked 1 invalid mode interrupt is enabled m_safe safe mode interrupt mask 0 safe mode interrupt is masked 1 safe mode interrupt is enabled m_mtc mode transition comp lete interrupt mask 0 mode transition complete interrupt is masked 1 mode transition complete interrupt is enabled RM0017 mode entry module (mc_me) doc id 14629 rev 8 162/904 invalid mode transition status register (me_imts) this register provides the status bits for each cause of invalid mode interrupt. figure 55. invalid mode transition status register (me_imts) address 0xc3fd_c014 access: supervisor read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000000000 s_mti s_mri s_dma s_nma s_sea w w1cw1cw1cw1cw1c reset0000000000000000 table 68. invalid mode transition status register (me_imts) field descriptions field description s_mti mode transition illegal status ? this bit is set whenever a new mode is requested while some other mode transition process is active ( s_mtrans is ?1?). please refer to section 8.4.5 mode transition interrupts for the exceptions to this behavior. it is cleared by writing a ?1? to this bit. 0 mode transition requested is not illegal 1 mode transition requested is illegal s_mri mode request illegal status ? this bit is set whenever the target mode requested is not a valid mode with respect to current mode. it is cleared by writing a ?1? to this bit. 0 target mode requested is not illegal with respect to current mode 1 target mode requested is illegal with respect to current mode s_dma disabled mode access status ? this bit is set whenever the target mode requested is one of those disabled modes determined by me_me register. it is cleared by writing a ?1? to this bit. 0 target mode requested is not a disabled mode 1 target mode requested is a disabled mode s_nma non-existing mode access status ? this bit is set whenever the target mode requested is one of those non existing modes determined by me_me register. it is cleared by writing a ?1? to this bit. 0 target mode requested is an existing mode 1 target mode requested is a non-existing mode s_sea safe event active status ? this bit is set whenever the device is in safe mode, safe event bit is pending and a new mode requested other than reset / safe modes. it is cleared by writing a ?1? to this bit. 0 no new mode requested other than reset / safe while safe event is pending 1 new mode requested other than reset / safe while safe event is pending mode entry module (mc_me) RM0017 163/904 doc id 14629 rev 8 debug mode transition status register (me_dmts) this register provides the status of different factors which influence mode transitions. it is used to give an indication of why a mode transition indicated by me_gs.s_mtrans may be taking longer than expected. note: the me_dmts register does not indicate whether a mode transition is ongoing. therefore, some me_dmts bits may still be asserted after the mode transition has completed. figure 56. debug mode transition status register (me_dmts) address 0xc3fd_c018 access: supervisor read/write 0123456789101112131415 r00000000 mph_busy 00 pmc_prog core_dbg 00 smr w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 fmpll_sc fxosc_sc firc_sc 0 sysclk_sw dflash_sc cflash_sc cdp_prph_0_143 000 cdp_prph_96_127 cdp_prph_64_95 cdp_prph_32_63 cdp_prph_0_31 w reset0000000000000000 table 69. debug mode transition status register (me_dmts) field descriptions field description mph_busy mc_me/mc_pcu handshake busy indicator ? this bit is set if the mc_me has requested a mode change from the mc_pcu and the mc_pcu has not yet responded. it is cleared when the mc_pcu has responded. 0 handshake is not busy 1 handshake is busy pmc_prog mc_pcu mode change in progress indicator ? this bit is set if the mc_pcu is in the process of powering up or down power domains. it is cleared when all power-up/down processes have completed. 0 power-up/down transition is not in progress 1 power-up/down transition is in progress core_dbg processor is in debug mode indicator ? this bit is set while the processor is in debug mode. 0 the processor is not in debug mode 1 the processor is in debug mode RM0017 mode entry module (mc_me) doc id 14629 rev 8 164/904 smr safe mode request from mc_rgm is active in dicator ? this bit is set if a hardware safe mode request has been triggered. it is cleared when the hardware safe mode request has been cleared. 0 a safe mode request is not active 1 a safe mode request is active fmpll_sc fmpll state change during mode transition indicator ? this bit is set when the frequency modulated phase locked loop is reques ted to change its power up/down state. it is cleared when the frequency modulated phase locked loop has completed its state change. 0 no state change is taking place 1 a state change is taking place fxosc_sc fxosc state change during mode transition indicator ? this bit is set when the fast external crystal oscillator (4-16 mhz) is requ ested to change its power up/down state. it is cleared when the fast external crystal os cillator (4-16 mhz) has completed its state change. 0 no state change is taking place 1 a state change is taking place firc_sc firc state change during mode transition indicator ? this bit is set when the fast internal rc oscillator (16 mhz) is request ed to change its power up/down state. it is cleared when the fast internal rc oscillato r (16 mhz) has completed its state change. 0 no state change is taking place 1 a state change is taking place sysclk_sw system clock switching pending status ? 0 no system clock source switching is pending 1 a system clock source switching is pending dflash_sc dflash state change during mode transitio n indicator ? this bit is set when the dflash is requested to change its power up/d own state. it is cleared when the dflash has completed its state change. 0 no state change is taking place 1 a state change is taking place cflash_sc cflash state change during mode transitio n indicator ? this bit is set when the cflash is requested to change its power up/d own state. it is cleared when the dflash has completed its state change. 0 no state change is taking place 1 a state change is taking place cdp_prph_0_143 clock disable process pending status for peripherals 0?143 ? this bit is set when any peripheral has been requested to have its cl ock disabled. it is cleared when all the peripherals which have been requested to have their clocks disabled have entered the state in which their clocks may be disabled. 0 no peripheral clock disabling is pending 1 clock disabling is pending for at least one peripheral cdp_prph_96_127 clock disable process pending status for peripherals 96?127 ? this bit is set when any peripheral appearing in me_ps3 has been requested to have its clock disabled. it is cleared when all these peripherals which have been requested to have their clocks disabled have entered the state in which their clocks may be disabled. 0 no peripheral clock disabling is pending 1 clock disabling is pending for at least one peripheral table 69. debug mode transition status register (me_dmts) field descriptions (continued) field description mode entry module (mc_me) RM0017 165/904 doc id 14629 rev 8 reset mode configuration register (me_reset_mc) this register configures system behavior during reset mode. please refer to ta b l e 7 0 for details. cdp_prph_64_95 clock disable process pending status for peripherals 64?95 ? this bit is set when any peripheral appearing in me_ps2 has been requested to have its clock disabled. it is cleared when all these peripherals which have been requested to have their clocks disabled have entered the state in which their clocks may be disabled. 0 no peripheral clock disabling is pending 1 clock disabling is pending for at least one peripheral cdp_prph_32_63 clock disable process pending status for peripherals 32?63 ? this bit is set when any peripheral appearing in me_ps1 has been requested to have its clock disabled. it is cleared when all these peripherals which have been requested to have their clocks disabled have entered the state in which their clocks may be disabled. 0 no peripheral clock disabling is pending 1 clock disabling is pending for at least one peripheral cdp_prph_0_31 clock disable process pending status for peripherals 0?31 ? this bit is set when any peripheral appearing in me_ps0 has been requested to have its clock disabled. it is cleared when all these peripherals which have been requested to have their clocks disabled have entered the state in which their clocks may be disabled. 0 no peripheral clock disabling is pending 1 clock disabling is pending for at least one peripheral table 69. debug mode transition status register (me_dmts) field descriptions (continued) field description figure 57. invalid mode transition status register (me_imts) address 0xc3fd_c020 access: supervisor read/write 0123456789101112131415 r00000000pdo00 mvron dflaon cflaon w reset0000000000011111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000 fmpllon fxoscon fircon sysclk w reset0000000000010000 RM0017 mode entry module (mc_me) doc id 14629 rev 8 166/904 test mode configuration register (me_test_mc) this register configures system behavior during test mode. please refer to ta b l e 7 0 for details. note: byte and half-word write accesses are not allowed to this register. safe mode configuration register (me_safe_mc) this register configures system behavior during safe mode. please refer to ta b l e 7 0 for details. note: byte and half-word write accesses are not allowed to this register. figure 58. test mode configuration register (me_test_mc) address 0xc3fd_c024 access: supervisor read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r00000000 pdo 00 mvron dflaon cflaon w reset0000000000011111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000 fmpllon fxoscon fircon sysclk w reset0000000000010000 figure 59. safe mode configuration register (me_safe_mc) address 0xc3fd_c028 access: supervisor read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r00000000 pdo 00 mvron dflaon cflaon w reset0000000010011111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000 fmpllon fxoscon fircon sysclk w reset0000000000010000 mode entry module (mc_me) RM0017 167/904 doc id 14629 rev 8 drun mode configuration register (me_drun_mc) this register configures system behavior during drun mode. please refer to ta bl e 7 0 for details. note: byte and half-word write accesses are not allowed to this register. note: the values of fxoscon , cflaon and dflaon are retained through standby mode. run0?3 mode configuration registers (me_run0 ? 3_mc) this register configures system behavior during run0?3 modes. please refer to ta bl e 7 0 for details. figure 60. drun mode configuration register (me_drun_mc) address 0xc3fd_c02c access: supervisor read/write 0123456789101112131415 r00000000pdo00 mvron dflaon cflaon w reset0000000000011111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000 fmpllon fxoscon fircon sysclk w reset0000000000010000 figure 61. run0?3 mode configuration registers (me_run0?3_mc) address 0xc3fd_c030 - 0xc3fd_c03c access: supervisor read/write 0123456789101112131415 r00000000pdo00 mvron dflaon cflaon w reset0000000000011111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000 fmpllon fxoscon fircon sysclk w reset0000000000010000 RM0017 mode entry module (mc_me) doc id 14629 rev 8 168/904 note: byte and half-word write accesses are not allowed to this register. halt mode configuration register (me_halt_mc) this register configures system behavior during halt mode. please refer to ta b l e 7 0 for details. note: byte and half-word write accesses are not allowed to this register. stop mode configuration register (me_stop_mc) this register configures system behavior during stop mode. please refer to ta b l e 7 0 for details. note: byte and half-word write accesses are not allowed to this register. figure 62. halt mode configuration register (me_halt_mc) address 0xc3fd_c040 access: supervisor read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r00000000pdo00 mvron dflaon cflaon w reset0000000000011010 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000 fmpllon fxoscon fircon sysclk w reset0000000000010000 figure 63. stop mode configuration register (me_stop_mc) address 0xc3fd_c048 access: supervisor read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r00000000 pdo 00 mvron dflaon cflaon w reset0000000000010101 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000 fmpllon fxoscon fircon sysclk w reset0000000000010000 mode entry module (mc_me) RM0017 169/904 doc id 14629 rev 8 standby mode configuration register (me_standby_mc) this register configures system behavior during standby mode. please refer to ta b l e 7 0 for details. note: byte and half-word write accesses are not allowed to this register. figure 64. standby mode configuration register (me_standby_mc) address 0xc3fd_c054 access: supervisor read/write 0123456789101112131415 r00000000pdo00 mvron dflaon cflaon w reset0000000010000101 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000 fmpllon fxoscon fircon sysclk w reset0000000000011111 table 70. mode configuration registers (me_< mode >_mc) field descriptions field description pdo i/o output power-down control ? this bit controls the output power-down of i/os. 0 no automatic safe gating of i/os used an d pads power sequence driver is enabled 1in safe / test modes, outputs of pads are forced to high impedance state and pads power sequence driver is disabled. th e inputs are level unchanged. in stop mode, only pad power sequence driver is disabled but the state of the output is kept. in standby mode, power sequence driver and all pads except those mapped on wakeup lines are not powered and therefore high impedance. wakeup line configuration remains unchanged. mvron main voltage regulator control ? this bit specifies whether main voltage regulator is switched off or not while entering this mode. 0 main voltage regulator is switched off 1 main voltage regulator is switched on dflaon data flash power-down control ? this bit specifies the operating mode of the data flash after entering this mode. 00reserved 01 data flash is in power-down mode 10 data flash is in low-power mode 11 data flash is in normal mode note: if the flash memory is to be powered down in any mode, then your software must ensure that reset sources are configured as long resets in the rgm_fess register (see section , functional event short se quence register (rgm_fess) ). RM0017 mode entry module (mc_me) doc id 14629 rev 8 170/904 cflaon code flash power-down control ? this bit specifies the operating mode of the program flash after entering this mode. 00 reserved 01 code flash is in power-down mode 10 code flash is in low-power mode 11 code flash is in normal mode fmpllon frequency modulated phase locked loop control 0 frequency modulated phase locked loop is switched off 1 frequency modulated phase locked loop is switched on fxoscon fast external crystal oscillator (4-16 mhz) control 0 fast external crystal oscillator (4-16 mhz) is switched off 1 fast external crystal oscillator (4-16 mhz) is switched on fircon fast internal rc oscill ator (16 mhz) control 0 fast internal rc oscillator (16 mhz) is switched off 1 fast internal rc oscillator (16 mhz) is switched on sysclk system clock switch control ? these bits specify the system clock to be used by the system. 0000 16 mhz int. rc osc. 0001 div. 16 mhz int. rc osc. 0010 4-16 mhz ext. xtal osc. 0011 div. ext. xtal osc. 0100 freq. mod. pll 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 system clock is disabled table 70. mode configuration registers (me_< mode >_mc) field descriptions (continued) field description mode entry module (mc_me) RM0017 171/904 doc id 14629 rev 8 peripheral status register 0 (me_ps0) this register provides the status of the peripherals. please refer to ta b l e 7 1 for details. peripheral status register 1 (me_ps1) this register provides the status of the peripherals. please refer to ta b l e 7 1 for details. figure 65. peripheral status register 0 (me_ps0) address 0xc3fd_c060 access: supervisor read 0123456789101112131415 r0000000000 s_flexcan5 s_flexcan4 s_flexcan3 s_flexcan2 s_flexcan1 s_flexcan0 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000 s_dspi2 s_dspi1 s_dspi0 0000 w reset0000000000000000 figure 66. peripheral status register 1 (me_ps1) address 0xc3fd_c064 access: supervisor read 0123456789101112131415 r0 0 0 s_cansampler 00 s_ctu 00000 s_linflex3 s_linflex2 s_linflex1 s_linflex0 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 0 s_i2c0 00000000000 s_adc0 w reset0000000000000000 RM0017 mode entry module (mc_me) doc id 14629 rev 8 172/904 peripheral status register 2 (me_ps2) this register provides the status of the peripherals. please refer to ta b l e 7 1 for details. peripheral status register 3 (me_ps3) this register provides the status of the peripherals. please refer to ta b l e 7 1 for details. figure 67. peripheral status register 2 (me_ps2) address 0xc3fd_c068 access: supervisor read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r0 0 0 s_pit_rti s_rtc_api 00000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000 s_emios1 s_emios0 00 s_wkpu s_siul 0000 w reset0000000000000000 figure 68. peripheral status register 3 (me_ps3) address 0xc3fd_c06c access: supervisor read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000 s_cmu 00000000 w reset0000000000000000 mode entry module (mc_me) RM0017 173/904 doc id 14629 rev 8 run peripheral configuration registers (me_run_pc0 ? 7) these registers configure eight different types of peripheral behavior during run modes. table 71. peripheral status regist ers 0?4 (me_ps0?4) field descriptions field description s_ RM0017 mode entry module (mc_me) doc id 14629 rev 8 174/904 low-power peripheral configur ation registers (me_lp_pc0 ? 7) these registers configure eight different types of peripheral behavior during non-run modes. safe peripheral control during safe 0 peripheral is frozen with clock gated 1 peripheral is active test peripheral control during test 0 peripheral is frozen with clock gated 1 peripheral is active reset peripheral cont rol during reset 0 peripheral is frozen with clock gated 1 peripheral is active table 72. run peripheral configuration regi sters (me_run_pc0?7) field descriptions field description figure 70. low-power peripheral conf iguration registers (me_lp_pc0?7) address 0xc3fd_c0a0 - 0xc3fd_c0bc access: supervisor read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 standby 00 stop 0 halt 00000000 w reset0000000000000000 table 73. low-power peripheral configurati on registers (me_lp_pc0 ?7) field descriptions field description standby peripheral control during standby 0 peripheral is frozen with clock gated 1 peripheral is active stop peripheral control during stop 0 peripheral is frozen with clock gated 1 peripheral is active halt peripheral control during halt 0 peripheral is frozen with clock gated 1 peripheral is active mode entry module (mc_me) RM0017 175/904 doc id 14629 rev 8 peripheral control registers (me_pctl0 ? 143) these registers select the configurations during run and non-run modes for each peripheral. figure 71. peripheral control registers (me_pctl0?143) address 0xc3fd_c0c0 - 0xc3fd_c14f access: supervisor read/write 01234567 r 0 dbg_f lp_cfg run_cfg w reset00000000 table 74. peripheral control registers (me_pctl0?143) field descriptions field description dbg_f peripheral control in debug mode ? this bit controls the state of the peripheral in debug mode. 0 peripheral state depends on run_cfg / lp_cfg bits and the device mode. 1 peripheral is frozen if not already frozen in device modes. note: this feature is useful to freeze the peripheral state while entering debug. for example, this may be used to prevent a reference timer from running while making a debug accesses. lp_cfg peripheral configuration select for non-run modes ? these bits associate a configuration as defined in the me_lp_pc0?7 registers to the peripheral. 000 selects me_lp_pc0 configuration 001 selects me_lp_pc1 configuration 010 selects me_lp_pc2 configuration 011 selects me_lp_pc3 configuration 100 selects me_lp_pc4 configuration 101 selects me_lp_pc5 configuration 110 selects me_lp_pc6 configuration 111 selects me_lp_pc7 configuration run_cfg peripheral configuration select for run modes ? these bits associate a configuration as defined in the me_run_pc0?7 registers to the peripheral. 000 selects me_run_pc0 configuration 001 selects me_run_pc1 configuration 010 selects me_run_pc2 configuration 011 selects me_run_pc3 configuration 100 selects me_run_pc4 configuration 101 selects me_run_pc5 configuration 110 selects me_run_pc6 configuration 111 selects me_run_pc7 configuration table 75. peripheral control registers by peripheral peripheral me_pctln adc_0 32 can sampler 60 cmu 104 ctu 57 RM0017 mode entry module (mc_me) doc id 14629 rev 8 176/904 8.4 functional description 8.4.1 mode transition request the transition from one mode to another mode is normally handled by software by accessing the mode control me_mctl register. but in case of special events, mode transition can be automatically managed by hardware. in order to switch from one mode to another, the application should access me_mctl register twice by writing the first time with the value of the key (0x5af0) into the key bit field and the required target mode into the target_mode bit field, and the second time with the inverted value of the key (0xa50f) into the key bit field and the required target mode into the target_mode bit field. once a valid mode transition request is detected, the target mode configuration information is loaded from the corresponding me_ mode entry module (mc_me) RM0017 177/904 doc id 14629 rev 8 should check the s_current_mode bit field and the s_mtrans bit of the global status register me_gs to verify when the mode has been correctly entered and the transition process has completed. for a description of valid mode requests, please refer to section 8.4.5 mode transition interrupts . any modification of the mode co nfiguration register of the cu rrently selected mode will not be taken into account immediately but on the next request to enter this mode. this means that transition requests such as run0?3 run0?3 , drun drun , safe safe , and test test are considered valid mode transition requests. as soon as the mode request is accepted as valid, the s_mtrans bit is set till the status in the me_gs register matches the configuration programmed in the respective me_ RM0017 mode entry module (mc_me) doc id 14629 rev 8 178/904 8.4.2 modes details reset mode the device enters this mode on the following events: from safe , drun , run0?3 , or test mode when the target_mode bit field of the me_mctl register is written with ?0000? from any mode due to a system reset by the mc_rgm because of some non- recoverable hardware failure in the system (see the mc_rgm chapter for details) transition to this mode is instantaneous, and the system remains in this mode until the reset sequence is finished. the mode configuration information for this mode is provided by the me_reset_mc register. this mode has a pre-defined configuration, and the 16 mhz int. rc osc. is selected as the system clock. all power domains are made active in this mode. drun mode the device enters this mode on the following events. automatically from reset mode after completion of the reset sequence from run0?3 , safe , or test mode when the target_mode bit field of the me_mctl register is written with ?0011? from the standby mode after an external wakeup event or internal wakeup alarm (e.g. rtc/api event) as soon as any of the above events has occurred, a drun mode transition request is generated. the mode configuration information for this mode is provided by the me_drun_mc register. in this mode, the flashes, all clock sources, and the system clock configuration can be controlled by software as required. after system reset, the software execution starts with the default configurat ion selecting the 16 mhz int. rc osc. as the system clock. this mode is intended to be used by software to initialize all registers as per the system needs to execute small routines in a ?ping-pong? with the standby mode when this mode is entered from standby after a wakeup event, the me_drun_mc register content is restored to its pre- standby values, and the mode starts in that configuration. all power domains are active when this mode is entered due to a system reset sequence initiated by a destructive reset event. in other cases of entry, such as the exit from standby after a wakeup event, a functional reset event like an external reset or a software request from run0?3 , safe , or test mode, active power domains are determined by the power configuration register pcu_pconf2 of the mc_pcu. all power domains except power domains #0 and #1 are configurable in this mode (see the mc_pcu chapter for details). note: as flashes can be configured in low-power or power-down state in this mode, software must ensure that the code executes from sram before changing to this mode. mode entry module (mc_me) RM0017 179/904 doc id 14629 rev 8 safe mode the device enters this mode on the following events: from drun , run0?3 , or test mode when the target_mode bit field of the me_mctl register is written with ?0010? from any mode except reset due to a safe mode request generated by the mc_rgm because of some potentially recoverable hardware failure in the system (see the mc_rgm chapter for details) as soon as any of the above events has occurred, a safe mode transition request is generated. the mode configuration information for this mode is provided by the me_safe_mc register. this mode has a pre-defined configuration, and the 16 mhz int. rc osc. is selected as the system clock. all power domains are made active in this mode. if the safe mode is requested by software while some other mode transition process is ongoing, the new target mode becomes the safe mode regardless of other pending requests. in this case, the new mode request is not interpreted as an invalid request. note: if software requests to change to the safe mode and then requests to change back to the parent mode before the mode transition is completed, the device?s final mode after mode transition will be the parent mode. however, th is is not recommended software behavior. it is recommended for software to wait until the s_mtrans bit is cleared after requesting a change to safe before requesting another mode change. as long as a safe event is active, the system remains in the safe mode and no write access is allowed to the me_mctl register. this mode is intended to be used by software to assess the severity of the cause of failure and then to either ? re-initialize the device via the drun mode, or ? completely reset the device via the reset mode. if the outputs of the system i/os need to be forced to a high impedance state upon entering this mode, the pdo bit of the me_safe_mc register should be set. in this case, the pads? power sequence driver cell is also disabled. the input levels remain unchanged. test mode the device enters this mode on the following events: from the drun mode when the target_mode bit field of the me_mctl register is written with ?0001? as soon as any of the above events has occurred, a test mode transition request is generated. the mode configuration information for this mode is provided by the me_test_mc register. except for the main voltag e regulator, all reso urces of the system are configurable in this mode. the system clock to the whole system can be stopped by programming the sysclk bit field to ?1111?, and in this case, the only way to exit this mode is via a device reset. this mode is intended to be used by software to execute on-chip test routines all power domains except power domains #0 and #1 are configurable in this mode. active power domains are determined by the power configuration register pcu_pconf2 of the mc_pcu. RM0017 mode entry module (mc_me) doc id 14629 rev 8 180/904 note: as flash modules can be configured to a low-power or power-down state in these modes, software must ensure that the code will execute from sram befo re it changes to this mode. run0?3 modes the device enters one of these modes on the following events: from the drun another run0?3 mode when the target_mode bit field of the me_mctl register is written with ?0100?0111? from the halt mode by an interrupt event from the stop mode by an interrupt or wakeup event as soon as any of the above events occur, a run0?3 mode transition request is generated. the mode configuration information for these modes is provided by me_run0?3_mc registers. in these modes, the flashes, all clock sources, and the system clock configuration can be controlled by software as required. these modes are intended to be used by software to execute application routines all power domains except power domains #0 and #1 are configurable in these modes in order to reduce leakage consumption. active power domains are determined by the power configuration register pcu_pconf2 of the mc_pcu. note: as flash modules can be configured to a low-power or power-down state in these modes, software must ensure that the code will execute from sram befo re it changes to this mode. halt mode the device enters this mode on the following events: from one of the run0?3 modes when the target_mode bit field of the me_mctl register is written with ?1000?. as soon as any of the above events occur, a halt mode transition request is generated. the mode configuration information for this mode is provided by me_halt_mc register. this mode is quite configurable, and the me_halt_mc register should be programmed according to the system needs. the main voltage regulator and the flashes can be put in power-down mode as needed. if there is a halt mode request while an interrupt request is active, the device mode does not change, and an invalid mode interrupt is not generated. this mode is intended as a first level low-power mode with the core clock frozen only a few peripherals running and to be used by software to wait until it is required to do something and then to react quickly (i.e. within a few system clock cycles of an interrupt event) all power domains except power domains #0 and #1 are configurable in this mode in order to reduce leakage consumption. active power domains are determined by the power configuration register pcu_pconf2 of the mc_pcu. mode entry module (mc_me) RM0017 181/904 doc id 14629 rev 8 stop mode the device enters this mode on the following events: from one of the run0?3 modes when the target_mode bit field of the me_mctl register is written with ?1010?. as soon as any of the above events occur, a stop mode transition request is generated. the mode configuration information for this mode is provided by the me_stop_mc register. this mode is fully configurable, and the me_stop_mc register should be programmed according to the system needs. the fmpll is switched off in this mode. the main voltage regulator and the flashes can be put in power-down mode as needed. if there is a stop mode request while any interrupt or wakeup event is active, the device mode does not change, and an invalid mode interrupt is not generated. this can be used as an advanced low-power mode with the core clock frozen and almost all peripherals stopped. this mode is intended as an advanced low-power mode with the core clock frozen almost all peripherals stopped and to be used by software to wait until it is required to do something with no need to react quickly (e.g. allow for system clock source to be re-started) if the pads? power sequence driver cell needs to be disabled while entering this mode, the pdo bit of the me_stop_mc register should be set. the state of the outputs is kept. this mode can be used to stop all clock sources, thus preserving the device status. when exiting the stop mode, the fast internal rc oscillato r (16 mhz) clock is selected as the system clock until the target clock is available. all power domains except power domains #0 and #1 are configurable in this mode in order to reduce leakage consumption. active power domains are determined by the power configuration register pcu_pconf2 of the mc_pcu. standby mode the device enters this mode on the following events: from the drun or one of the run0?3 modes when the target_mode bit field of the me_mctl register is written with ?1101?. as soon as any of the above events occur, a standby mode transition request is generated. the mode configuration information for this mode is provided by the me_standby_mc register. in this mode, the power supply is turned off for most of the device. the only parts of the device that are still powered during this mode are pads mapped on wakeup lines and power domain #0 which contains the mc_rgm, mc_pcu, wkpu, 8k ram, rtc_api, cansampler, sirc, firc, sxosc, and device and user option bits. the firc can be optionally switched off. this is the lowest power consumption mode possible on the device. this mode is intended as an extreme low-power mode with the core, the flashes, and almost all peripherals and memories powered down RM0017 mode entry module (mc_me) doc id 14629 rev 8 182/904 and to be used by software to wait until it is required to do something with no need to react quickly (i.e. allow for system power-up and system cl ock source to be re-started) the exit sequence of this mode is similar to the reset sequence. however, in addition to booting from the default location, the device can also be configured to boot from the backup sram (see the rgm_stdby register description in the mc_rgm chapter for details). in the case of booting from backup sram, it is also possible to keep the flashes disabled by writing ?01? to the cflaon and dflaon fileds in the me_drun_mc register prior to standby entry. if there is a standby mode request while any wakeup event is active, the device mode does not change. all power domains except power domain #0 are configurable in this mode in order to reduce leakage consumption. active power domains are determined by the power configuration register pcu_pconf2 of the mc_pcu. 8.4.3 mode transition process the process of mode transition follows the following steps in a pre-defined manner depending on the current device mode and the requested target mode. in many cases of mode transition, not all steps need to be executed based on the mode control information, and some steps may not be valid acco rding to the mode definition itself. target mode request the target mode is requested by accessing the me_mctl register with the required keys. this mode transition request by software must be a valid request satisfying a set of pre- defined rules to initiate the process. if the request fails to satisfy these rules, it is ignored, and the target_mode bit field is not updated. an optional interrupt can be generated for invalid mode requests. refer to section 8.4.5 mode transition interrupts for details. in the case of mode transitions occurring because of hardware events such as a reset, a safe mode request, or interrupt requests and wakeup events to exit from low-power modes, the target_mode bit field of the me_mctl register is automatically updated with the appropriate target mode. the mode change process start is indicated by the setting of the mode transition status bit s_mtrans of the me_gs register. a reset mode requested via the me_mctl register is passed to the mc_rgm, which generates a global system reset and initiates the reset sequence. the reset mode request has the highest priority, and the mc_me is kept in the reset mode during the entire reset sequence. the safe mode request has the next highest priority after reset which can be generated by software via the me_mctl register from all software running modes including drun , run0?3 , and test or by the mc_rgm after the detection of system hardware failures, which may occur in any mode. target mode configuration loading on completion of the target mode request , the target mode configuration from the me_ mode entry module (mc_me) RM0017 183/904 doc id 14629 rev 8 peripheral clocks disable on completion of the target mode request , the mc_me requests each peripheral to enter its stop mode when: the peripheral is configured to be disabled via the target mode, the peripheral configuration registers me_run_pc0?7 and me_lp_pc0?7 , and the peripheral control registers me_pctl0?143 caution: the mc_me does not automatically request peripherals to enter their stop modes if the power domains in which they are residing are to be turned off due to a mode change. therefore, it is software?s re sponsibility to ensure that thos e peripherals th at are to be powered down are configured in the mc_me to be frozen. each peripheral acknowledges its stop mode request after closing its internal activity. the mc_me then disables the corresponding clock(s) to this peripheral. in the case of a safe mode transition request, the mc_me does not wait for the peripherals to acknowledge the stop requests. the safe mode clock gating configuration is applied immediately regardless of the status of the peripherals? stop acknowledges. please refer to section 8.4.6 peripheral clock gating for more details. each peripheral that may block or disrupt a communication bus to which it is connected ensures that these outputs are forced to a safe or recessive state when the device enters the safe mode. table 76. mc_me resource control overview resource mode reset test safe drun run0?3 halt stop standby firc ? on on on on on on on on fxosc ??? off off offoffoffoffoff off fmpll ?? off off offoffoffoff off off cflash ??? normal normal normal normal normal low-power power- down power- down dflash ??? normal normal normal normal normal low-power power- down power- down mvreg ? on on on on on on on off pdo ? off off on off off off off on RM0017 mode entry module (mc_me) doc id 14629 rev 8 184/904 processor low-power mode entry if, on completion of the peripheral clocks disable , the mode transition is to the halt mode, the mc_me requests the processor to enter its halted state. the processor acknowledges its halt state request after completing all outstanding bus transactions. if, on completion of the peripheral clocks disable , the mode transition is to the stop or standby mode, the mc_me requests the processor to enter its stopped state. the processor acknowledges its stop state request after completing all outstanding bus transactions. processor and system memory clock disable if, on completion of the processor low-power mode entry , the mode transition is to the halt , stop , or standby mode and the processor is in its appropriate halted or stopped state, the mc_me disables the processor and system memory clocks to achieve further power saving. the clocks to the processor and system memories are unaffected for all transitions between software running modes including drun , run0?3 , and safe . caution: clocks to the whole device including the processor and system memories can be disabled in test mode. clock sources switch-on on completion of the processor low-power mode entry , the mc_me controls all clock sources that affect the system clock based on the mode entry module (mc_me) RM0017 185/904 doc id 14629 rev 8 configuration, as the main voltage regulator requires the 16 mhz int. rc osc. during power- up in order to generate the voltage status. during the standby exit sequence, the mc_pcu alone manages the power-up of the main voltage regulator, and the mc_me is kept in reset or shut off (depending on the power domain #1 status). flash modules switch-on on completion of the main voltage regulator switch-on , if a flash module needs to be switched to normal mode from its low-power or power-down mode based on the cflaon and dflaon bit fields of the me_ RM0017 mode entry module (mc_me) doc id 14629 rev 8 186/904 mc_me may assert the peripheral clock enables of the peripherals residing in those power domains. processor and memory clock enable if the mode transition is from any of the low-power modes halt or stop to run0?3 , the clocks to the processor and system memories are enabled. the process of enabling these clocks is executed only after the flash modules switch-on process is completed. processor low-power mode exit if the mode transition is from any of the low-power modes halt , stop , or standby to run0?3 , the mc_me requests the processor to exit from its halted or stopped state. this step is executed only after the processor and memory clock enable process is completed. system clock switching based on the sysclk bit field of the me_ mode entry module (mc_me) RM0017 187/904 doc id 14629 rev 8 power domain #2 switch-off based on the device mode and the mc_pcu?s power configuration register pcu_pconf2 , the power domain #2 is controlled by the mc_pcu. if a mode change translates to a power-down of the power domain, then the mc_pcu starts the power-down sequence. the mc_pcu acknowledges the completion of the power-down sequence with respect to the new mode, and the mc_me uses this information to update the mode transition status. this step is executed only after the peripheral clocks disable process has completed. pad switch-off if the pdo bit of the me_ RM0017 mode entry module (mc_me) doc id 14629 rev 8 188/904 and updates its ava ilability status bit s_fmpll of the me_gs register to ?0?. this step is executed only after the system clock switching process is completed. clock sources switch-off based on the device mode and the mode entry module (mc_me) RM0017 189/904 doc id 14629 rev 8 current mode update the current mode status bit field s_current_mode of the me_gs register is updated with the target mode bit field target_mode of the me_mctl register when: all the updated status bits in the me_gs register match the configuration specified in the me_ RM0017 mode entry module (mc_me) doc id 14629 rev 8 190/904 power domain switch-on power domain switch-off pll switch-on pll switch-off end target mode request write me_mctl register safe mode request interrupt/wakeup event peripheral clocks disable clock sources switch-on system clock switching main vreg switch-on flash switch-on pad processor low-power processor & pad peripheral clocks enable flash switch-off clock sources switch-off s_mtrans = ?1? analog on digital control analog off current mode update start s_mtrans = ?0? outputs -on outputs -off entry processor low-power exit clock disable memory processor & clock enable memory figure 73. mc_me transition diagram target standby standby request ny main vreg switch-off mode entry module (mc_me) RM0017 191/904 doc id 14629 rev 8 8.4.4 protection of mode configuration registers while programming the mode configuration registers me_ RM0017 mode entry module (mc_me) doc id 14629 rev 8 192/904 me_imts register is set. this condition is detected regardless of whether the proper key mechanism is followed while writing the me_mctl register. if some of the device modes are disabled as programmed in the me_me register, their respective configurations are cons idered reserved, and any access to the me_mctl register with those values results in an invalid mode transition request. when such a disabled mode is requested, the s_dma bit of the me_imts register is set. this condition is detected regardless of whether the proper key mechanism is followed while writing the me_mctl register. if the target mode is not a valid mode with respect to current mode, the mode request illegal status bit s_mri of the me_imts register is set. this co ndition is detected only when the proper key mechanism is followed while writing the me_mctl register. otherwise, the write operation is ignored. if further new mode requests occur while a mode transition is in progress (the s_mtrans bit of the me_gs register is ?1?), the mode transition illegal status bit s_mti of the me_imts register is set. this condition is detected only when the proper key mechanism is followed while writing the me_mctl register. otherwise, the write operation is ignored. note: as the causes of invalid mode transitions may overlap at the same time, the priority implemented for invalid mode transition status bits of the me_imts register in the order from highest to lowest is s_sea , s_nma , s_dma , s_mri , and s_mti . as an exception, the mode transition request is not considered as invalid under the following conditions: a new request is allowed to enter the reset or safe mode irrespective of the mode transition status. as the exit of halt and stop modes depends on the interrupts of the system which can occur at any instant, these requests to return to run0?3 modes are always valid. in order to avoid any unwanted lockup of the device modes, software can abort a mode transition by requesting the parent mode if, for example, the mode transition has not completed after a software determined ?reasonable? amount of time for whatever reason. the parent mode is the device mode before a valid mode request was made. self-transition requests (e.g. run0 run0 ) are not considered as invalid even when the mode transition process is active (i.e. s_mtrans is ?1?). during the low-power mode exit process, if the system is not able to enter the respective run0?3 mode properly (i.e. all status bits of the me_gs register match with configuration bits in the me_ mode entry module (mc_me) RM0017 193/904 doc id 14629 rev 8 pending bit is not set when the safe mode is entered by a software request (i.e. programming of me_mctl register). mode transition complete interrupt whenever the system completes a mode transition fully (i.e. the s_mtrans bit of me_gs register transits from ?1? to ?0?), the interrupt pending bit i_mtc of the me_is register is set, and interrupt request is generated if the mask bit m_mtc of the me_im register is ?1?. the interrupt bit i_mtc is not set when entering low-power modes halt and stop in order to avoid the same event requesting the exit of these low-power modes. 8.4.6 peripheral clock gating during all device modes, each peripheral can be associated with a particular clock gating policy determined by two groups of peripheral configuration registers. the run peripheral configuration registers me_run_pc0?7 are chosen only during the software running modes drun , test , safe , and run0?3. all configurations are programmable by software according to the needs of application. each configuration register contains a mode bit which determines wh ether or not a peripheral clock is to be gated. run configuration selection for each peripheral is done by the run_cfg bit field of the me_pctl0?143 registers. the low-power peripheral configuration registers me_lp_pc0?7 are chosen only during the low-power modes halt , stop , and standby . all configurations are programmable by software according to the needs of the application. each configuration register contains a mode bit which determines whether or not a peripheral clock is to be gated. low-power configuration selection for each peripheral is done by the lp_cfg bit field of the me_pctl0?143 registers. any modifications to the me_run_pc0?7 , me_lp_pc0?7 , and me_pctl0?143 registers do not affect the clock gating behavior until a new mode transition request is generated. whenever the processor enters a debug session during any mode, the following occurs for each peripheral: the clock is gated if the dbg_f bit of the associated me_pctl0?143 register is set. otherwise, the peripheral clock gating status depends on the run_cfg and lp_cfg bits. any further modifications of the me_run_pc0?7 , me_lp_pc0?7 , and me_pctl0?143 registers during a debug session will take affect immediately without requiring any new mode request. 8.4.7 application example figure 74 shows an example application flow for requesting a mode change and then waiting until the mode transition has completed. RM0017 mode entry module (mc_me) doc id 14629 rev 8 194/904 figure 74. mc_me application example flow diagram start of mode change config for target mode okay? write me_ reset generation module (mc_rgm) RM0017 195/904 doc id 14629 rev 8 9 reset generation module (mc_rgm) 9.1 introduction 9.1.1 overview the reset generation module (mc_rgm) centralizes the different reset sources and manages the reset sequence of the device. it provides a register interface and the reset sequencer. the different registers are available to monitor and control the device reset sequence. the reset sequencer is a state ma chine which controls the different phases (phase0, phase1, phase2, phase3, and idle) of the reset s equence and control the reset signals generated in the system. figure 75 depicts the mc_rgm block diagram. RM0017 reset generation module (mc_rgm) doc id 14629 rev 8 196/904 pa[8] and pa[9] reset registers platform interface core mc_rgm figure 75. mc_rgm block diagram mc_me power-on 1.2 v low-voltage detected (power domain #0) 1.2 v low-voltage detected (power domain #1) software watchdog timer 2.7 v low-voltage detected jtag initiated reset debug control core reset software reset checkstop reset fmpll fail fxosc frequency lower than reference cmu clock frequency higher/lower than reference 4.5 v low-voltage detected code or data flash fatal error functional reset filter boot mode capture destructive reset filter reset state machine sscm peripherals mc_cgm reset generation module (mc_rgm) RM0017 197/904 doc id 14629 rev 8 9.1.2 features the mc_rgm contains the functionality for the following features: ?destructive? resets management ?functional? resets management signalling of reset events after each reset sequence (reset status flags) conversion of reset events to safe mode or interrupt request events (for further mode details, please see the mc_me chapter) short reset sequence configuration bidirectional reset behavior configuration selection of alternate boot via the backup sram on standby mode exit (for further mode details, please see the mc_me chapter) boot mode capture on reset deassertion 9.1.3 modes of operation the different reset sources are organized into two families: ?destructive? and ?functional?. a ?destructive? reset source is associated with an event related to a critical - usually hardware - error or dysfunction. when a ?destructive? reset event occurs, the full reset sequence is applied to the de vice starting from phase0. th is resets the full device ensuring a safe start-up state for both digital and analog modules. ?destructive? resets are ? power-on reset ? 1.2 v low-voltage detected (power domain #0) ? 1.2 v low-voltage detected (power domain #1) ? software watchdog timer ? 2.7 v low-voltage detected a ?functional? reset source is associated with an event related to a less-critical - usually non-hardware - error or dysfunction. when a ?functional? reset event occurs, a partial reset sequence is applied to the device starting from phase1. in this case, most digital modules are reset normally, while analog modules or specific digital modules? (e.g. debug modules, flash modules) state is preserved. ?functional? resets are ? external reset ? jtag initiated reset ? debug control core reset ? software reset ? checkstop reset ?fmpll fail ? fxosc frequency lower than reference ? cmu clock frequency higher/lower than reference ? 4.5 v low-voltage detected ? code or data flash fatal error when a reset is triggered, the mc_rgm state machine is activated and proceeds through the different phases (i.e. phasen states). each phase is associated with a particular device reset being provided to the system. a phase is completed when all corresponding phase completion gates from either the system or internal to the mc_rgm are acknowledged. the RM0017 reset generation module (mc_rgm) doc id 14629 rev 8 198/904 device reset associated with the phase is then released, and the state machine proceeds to the next phase up to entering the idle phase. during this entire process, the mc_me state machine is held in reset mode. only at the end of the reset sequence, when the idle phase is reached, does the mc_me enter the drun mode. alternatively, it is possible for software to configure some reset source events to be converted from a reset to either a safe mode request issued to the mc_me or to an interrupt issued to the core (see section destructive event reset disable register (rgm_derd) and section destructive event altern ate request register (rgm_dear) for ?destructive? resets and section functional event reset disable register (rgm_ferd) and section functional event alternate request register (rgm_fear) for ?functional? resets). 9.2 external sign al description the mc_rgm interfaces to the bidirectional reset pin reset and the boot mode pins pa[8] and pa[9]. 9.3 memory map and register definition note: any access to unused registers as well as write accesses to read-only registers will: ? not change register content ? cause a transfer error table 78. mc_rgm register description address name description size access location supervisor 0xc3fe_4000 rgm_fes functional ev ent status half-word read/write 1 on page 9-201 0xc3fe_4002 rgm_des destructive ev ent status half-word read/write (1) 1. individual bits cl eared on writing ?1? on page 9-202 0xc3fe_4004 rgm_ferd functional event reset disable half-word read/write (2) 2. write once: ?0? = disable, ?1? = enable. on page 9-204 0xc3fe_4006 rgm_derd destructive event reset disable half-word read on page 9-205 0xc3fe_4010 rgm_fear functional event alternate request half-word read/write on page 9-206 0xc3fe_4012 rgm_dear destructive event alternate request half-word read on page 9-208 0xc3fe_4018 rgm_fess functional event short sequence half-word read/write on page 9-209 0xc3fe_401a rgm_stdby standby reset sequence half-word read/write on page 9-210 0xc3fe_401c rgm_fbre functional bidirectional reset enable half-word read/write on page 9-211 reset generation module (mc_rgm) RM0017 199/904 doc id 14629 rev 8 table 79. mc_rgm memory map address name 01232756789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0xc3fe_ 4000 rgm_f es / rgm_d es r f_exr 000000 f_flash f_lvd45 f_cmu_fhl f_cmu_olr f_fmpll f_chkstop f_soft f_core f_jtag ww1c w1c w1c w1c w1c w1c w1c w1c w1c w1c r f_por 00000000000 f_lvd27 f_swt f_lvd12_pd1 f_lvd12_pd0 ww1c w1cw1cw1cw1c 0xc3fe_ 4004 rgm_f erd / rgm_d erd r d_exr 000000 d_flash d_lvd45 d_cmu_fhl d_cmu_olr d_fmpll d_chkstop d_soft d_core d_jtag w r000000000000 d_lvd27 d_swt d_lvd12_pd1 d_lvd12_pd0 w 0xc3fe_ 4008 ? 0xc3fe_ 400c reserved 0xc3fe_ 4010 rgm_f ear / rgm_d ear r ar_exr 000000 ar_flash ar_lvd45 ar_cmu_fhl ar_cmu_olr ar_fmpll ar_chkstop ar_soft ar_core ar_jtag w r000000000000 ar_lvd27 ar_swt ar_lvd12_pd1 ar_lvd12_pd0 w 0xc3fe_ 4014 reserved RM0017 reset generation module (mc_rgm) doc id 14629 rev 8 200/904 9.3.1 register descriptions unless otherwise noted, all registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. the bytes are ordered according to big endian. for example, the rgm_stdby register may be accessed as a word at address 0xc3fe_4018, as a half-word at address 0xc3fe_401a, or as a byte at address 0xc3fe_401b. 0xc3fe_ 4018 rgm_f ess / rgm_s tdby r ss_exr 000000 ss_flash ss_lvd45 ss_cmu_fhl ss_cmu_olr ss_fmpll ss_chkstop ss_soft ss_core ss_jtag w r00000000 boot_from_bkp_ram 0000000 w 0xc3fe_ 401c rgm_f bre r be_exr 000000 be_flash be_lvd45 be_cmu_fhl be_cmu_olr be_fmpll be_chkstop be_soft be_core be_jtag w 0xc3fe_ 4020 ? 0xc3fe_ 7ffc reserved table 79. mc_rgm memory map (continued) address name 01232756789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reset generation module (mc_rgm) RM0017 201/904 doc id 14629 rev 8 functional event status register (rgm_fes) this register contains the status of the last asserted functional reset sources. it can be accessed in read/write on either supervisor mode or test mode. register bits are cleared on write ?1?. figure 76. functional event status register (rgm_fes) address 0xc3fe_4000 access: supervisor read/write 0123456789101112131415 r f_exr 000000 f_flash f_lvd45 f_cmu_fhl f_cmu_olr f_fmpll f_chkstop f_soft f_core f_jtag ww1c w1c w1c w1c w1c w1c w1c w1c w1c w1c por0000000000000000 table 80. functional event status re gister (rgm_fes) field descriptions field description f_exr flag for external reset 0 no external reset event has occurred since either the last clear or the last destructive reset assertion 1 an external reset event has occurred f_flash flag for code or da ta flash fatal error 0 no code or data flash fatal error event has occu rred since either the last clear or the last destructive reset assertion 1 a code or data flash fatal error event has occurred f_lvd45 flag for 4.5 v low-voltage detected 0 no 4.5 v low-voltage detected event has occurr ed since either the last clear or the last destructive reset assertion 1 a 4.5 v low-voltage detected event has occurred f_cmu_fhl flag for cmu clock frequency higher/lower than reference 0 no cmu clock frequency higher/lower than referenc e event has occurred since either the last clear or the last destructive reset assertion 1 a cmu clock frequency higher/lower than reference event has occurred f_cmu_olr flag for fxosc frequenc y lower than reference 0 no fxosc frequency lower than reference event ha s occurred since either the last clear or the last destructive reset assertion 1 a fxosc frequency lower than reference event has occurred f_fmpll flag for fmpll fail 0 no fmpll fail event has occurred since either the last clear or the last destructive reset assertion 1 a fmpll fail event has occurred RM0017 reset generation module (mc_rgm) doc id 14629 rev 8 202/904 destructive event status register (rgm_des) this register contains the status of the last asserted destructive reset sources. it can be accessed in read/write on either supervisor mode or test mode. register bits are cleared on write ?1?. f_chkstop flag for checkstop reset 0 no checkstop reset event has occurred since either the last clear or the last destructive reset assertion 1 a checkstop reset event has occurred f_soft flag for software reset 0 no software reset event has occurred since either the last clear or the last destructive reset assertion 1 a software reset event has occurred f_core flag for debug control core reset 0 no debug control core reset event has occurred sinc e either the last clear or the last destructive reset assertion 1 a debug control core reset event has occurred; this event can only be asserted when the dbcr0[rst] field is set by an external debugger . see the "debug support" chapter of the core reference manual for more details. f_jtag flag for jtag initiated reset 0 no jtag initiated reset event has occurred since either the last clear or the last destructive reset assertion 1 a jtag initiated re set event has occurred table 80. functional event status register (rgm_fes) field descriptions (continued) field description figure 77. destructive event status register (rgm_des) address 0xc3fe_4002 access: supervisor read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r f_por 00000000000 f_lvd27 f_swt f_lvd12_pd1 f_lvd12_pd0 ww1c w1c w1c w1c w1c por1000000000000000 reset generation module (mc_rgm) RM0017 203/904 doc id 14629 rev 8 note: the f_por flag is automatically cleared on a 1.2 v low-voltage detected (power domain #0 or #1) or a 2.7 v low-voltage detected. this means that if the power-up sequence is not monotonic (i.e the voltage rises and then drops enough to trigger a low-voltage detection), the f_por flag may not be set but instead the RM0017 reset generation module (mc_rgm) doc id 14629 rev 8 204/904 functional event reset disable register (rgm_ferd) this register provides dedicated bits to disable functional reset sources.when a functional reset source is disabled, the associated functional event will trigger either a safe mode request or an interrupt request (see section functional event alternate request register (rgm_fear) ). it can be accessed in read/write in either supervisor mode or test mode. it can be accessed in read only in user mode. each byte can be written only once after power- on reset. figure 78. functional event reset disable register (rgm_ferd) address 0xc3fe_4004 access: supervisor read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r d_exr 000000 d_flash d_lvd45 d_cmu_fhl d_cmu_olr d_fmpll d_chkstop d_soft d_core d_jtag w por0000000000000000 table 82. functional event reset disable register (rgm_ferd) field descriptions field description d_exr disable external reset 0 an external reset event triggers a reset sequence 1 an external reset event generates a safe mode request d_flash disable code or data flash fatal error 0 a code or data flash fatal error event triggers a reset sequence 1 a code or data flash fatal error event generates either a safe mode or an interrupt request depending on the value of rgm_fear.ar_flash d_lvd45 disable 4.5 v low-voltage detected 0 a 4.5 v low-voltage detected event triggers a reset sequence 1 a 4.5 v low-voltage detected event generates either a safe mode or an interrupt request depending on the value of rgm_fear.ar_lvd45 d_cmu_fhl disable cmu clock frequency higher/lower than reference 0 a cmu clock frequency higher/lower than reference event triggers a reset sequence 1 a cmu clock frequency higher/lower than reference event generates either a safe mode or an interrupt request depending on the value of rgm_fear.ar_cmu_fhl d_cmu_olr disable fxosc frequency lower than reference 0 a fxosc frequency lower than reference event triggers a reset sequence 1 a fxosc frequency lower than reference event generates either a safe mode or an interrupt request depending on the value of rgm_fear.ar_cmu_olr d_fmpll disable fmpll fail 0 a fmpll fail event triggers a reset sequence 1 a fmpll fail event generates either a safe mode or an interrupt request depending on the value of rgm_fear.ar_fmpll reset generation module (mc_rgm) RM0017 205/904 doc id 14629 rev 8 destructive event reset disable register (rgm_derd) this register provides dedicated bits to disable particular destructive reset sources. when a destructive reset source is di sabled, the associated destructi ve event will trigger either a safe mode request or an interrupt request (see section destructive event alternate request register (rgm_dear) ). d_chkstop disable checkstop reset 0 a checkstop reset event triggers a reset sequence 1 a checkstop reset event generates either a safe mode or an interrupt request depending on the value of rgm_fear.ar_chkstop d_soft disable software reset 0 a software reset event triggers a reset sequence 1 a software reset event generates either a safe mode or an interrupt request depending on the value of rgm_fear.ar_soft d_core disable debug control core reset 0 a debug control core reset event triggers a reset sequence 1 a debug control core reset event generates either a safe mode or an interrupt request depending on the value of rgm_fear.ar_core d_jtag disable jtag initiated reset 0 a jtag initiated reset event triggers a reset sequence 1 a jtag initiated reset event generates either a safe mode or an interrupt request depending on the value of rgm_fear.ar_jtag table 82. functional event reset disable regist er (rgm_ferd) field descriptions (continued) field description figure 79. destructive event reset disable register (rgm_derd) address 0xc3fe_4006 access: read 0123456789101112131415 r000000000000 d_lvd27 d_swt d_lvd12_pd1 d_lvd12_pd0 w por0000000000000000 RM0017 reset generation module (mc_rgm) doc id 14629 rev 8 206/904 functional event alternate request register (rgm_fear) this register defines an alternate request to be generated when a reset on a functional event has been disabled. the alternate request can be either a safe mode request to mc_me or an interrupt request to the system. it can be accessed in read/write in either supervisor mode or test mode. it can be accessed in read only in user mode. table 83. destructive event reset disable register (rgm_derd) field descriptions field description d_lvd27 disable 2.7 v low-voltage detected 0 a 2.7 v low-voltage detected event triggers a reset sequence 1 a 2.7 v low-voltage detected event generates either a safe mode or an interrupt request depending on the value of rgm_dear.ar_lvd27 d_swt disable software watchdog timer 0 a software watchdog timer event triggers a reset sequence 1 a software watchdog timer event generates either a safe mode or an interrupt request depending on the value of rgm_dear . d_lvd12_pd1 disable 1.2 v low-voltage detected (power domain #1) 0 a 1.2 v low-voltage detected (power dom ain #1) event triggers a reset sequence 1 a 1.2 v low-voltage detected (power domain #1) event generates either a safe mode or an interrupt request depending on the value of rgm_dear.ar_lvd12_pd1 d_lvd12_pd0 disable 1.2 v low-voltage detected (power domain #0) 0 a 1.2 v low-voltage detected (power dom ain #0) event triggers a reset sequence 1 a 1.2 v low-voltage detected (power domain #0) event generates either a safe mode or an interrupt request depending on the value of rgm_dear.ar_lvd12_pd0 figure 80. functional event alternate request register (rgm_fear) address 0xc3fe_4010 access: supervisor read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r ar_exr 000000 ar_flash ar_lvd45 ar_cmu_fhl ar_cmu_olr ar_fmpll ar_chkstop ar_soft ar_core ar_jtag w por0000000000000000 reset generation module (mc_rgm) RM0017 207/904 doc id 14629 rev 8 table 84. functional event alternate request register (rgm_fear) field descriptions field description ar_exr alternate request for external reset 0 generate a safe mode request on an external reset event if the reset is disabled 1 generate an interrupt request on an external reset event if the reset is disabled ar_flash alternate request for code or data flash fatal error 0 generate a safe mode request on a code or data flash fatal error event if the reset is disabled 1 generate an interrupt request on a code or data flash fatal error event if the reset is disabled ar_lvd45 alternate request for 4.5 v low-voltage detected 0 generate a safe mode request on a 4.5 v low-voltage detected event if the reset is disabled 1 generate an interrupt request on a 4.5 v low- voltage detected event if the reset is disabled ar_cmu_fhl alternate request for cmu clock freq uency higher/lower than reference 0 generate a safe mode request on a cmu clock frequency higher/lower than reference event if the reset is disabled 1 generate an interrupt request on a cmu clock frequency higher/lower than reference event if the reset is disabled ar_cmu_olr alternate request for fxosc fr equency lower than reference 0 generate a safe mode request on a fxosc frequency lower than reference event if the reset is disabled 1 generate an interrupt request on a fxosc frequency lower than reference event if the reset is disabled for the case when rgm_ferd[d_cmu_olr] = 1 & rgm_fear[ar_cmu_olr] = 1, an rgm interrupt will not be generated for an fxosc failure when the system clock = fxosc as there will be no system cloc k to execute the interrupt service routine. however, the interrupt service routine will be executed if the fxosc recovers at some point. the recommended use case for this feature is when the system clock = firc or fmpll. ar_fmpll alternate request for fmpll fail 0 generate a safe mode request on a fmpll fail event if the reset is disabled 1 generate an interrupt request on a fmpll fail event if the reset is disabled ar_chkstop alternate request for checkstop reset 0 generate a safe mode request on a checkstop reset event if the reset is disabled 1 generate an interrupt request on a checkstop reset event if the reset is disabled ar_soft alternate request for software reset 0 generate a safe mode request on a software reset event if the reset is disabled 1 generate an interrupt request on a software reset event if the reset is disabled ar_core alternate request for debug control core reset 0 generate a safe mode request on a debug control core reset event if the reset is disabled 1 generate an interrupt request on a debug contro l core reset event if the reset is disabled ar_jtag alternate request for jtag initiated reset 0 generate a safe mode request on a jtag initiated reset event if the reset is disabled 1 generate an interrupt request on a jtag initiated reset event if the reset is disabled RM0017 reset generation module (mc_rgm) doc id 14629 rev 8 208/904 destructive event alternate request register (rgm_dear) this register defines an alternate request to be generated when a reset on a destructive event has been disabled. the alternate request can be either a safe mode request to mc_me or an interrupt request to the system. figure 81. destructive event altern ate request register (rgm_dear) address 0xc3fe_4012 access: read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r000000000000 ar_lvd27 ar_swt ar_lvd12_pd1 ar_lvd12_pd0 w por0000000000000000 table 85. destructive event alternate request register (rgm_dear) field descriptions field description ar_lvd27 alternate request for 2.7 v low-voltage detected 0 generate a safe mode request on a 2.7 v low-voltage dete cted event if the reset is disabled 1 generate an interrupt request on a 2.7 v low-vo ltage detected event if the reset is disabled ar_swt alternate request for software watchdog timer 0 generate a safe mode request on a software watchdog timer event if the reset is disabled 1 generate an interrupt request on a software watchdog timer event if the reset is disabled ar_lvd12_pd1 alternate request for 1.2 v low-voltage detected (power domain #1) 0 generate a safe mode request on a 1.2 v low-voltage detected (power domain #1) event if the reset is disabled 1 generate an interrupt request on a 1.2 v low-vo ltage detected (power domain #1) event if the reset is disabled ar_lvd12_pd0 alternate request for 1.2 v low-voltage detected (power domain #0) 0 generate a safe mode request on a 1.2 v low-voltage detected (power domain #0) event if the reset is disabled 1 generate an interrupt request on a 1.2 v low-vo ltage detected (power domain #0) event if the reset is disabled reset generation module (mc_rgm) RM0017 209/904 doc id 14629 rev 8 functional event short sequence register (rgm_fess) this register defines which reset sequence will be done when a functional reset sequence is triggered.the functional reset sequence can either start from phase1 or from phase3 , skipping phase1 and phase2 . note: this could be useful for fast reset sequence, for example to skip flash reset. it can be accessed in read/write in either supervisor mode or test mode. it can be accessed in read in user mode. figure 82. functional event s hort sequence regi ster (rgm_fess) address 0xc3fe_4018 access: supervisor read/write 0123456789101112131415 r ss_exr 000000 ss_flash ss_lvd45 ss_cmu_fhl ss_cmu_olr ss_fmpll ss_chkstop ss_soft ss_core ss_jtag w por0000000000000000 table 86. functional event short sequence register (rgm_fess) field descriptions field description ss_exr short sequence for external reset 0 the reset sequence triggered by an external reset event will start from phase1 1 the reset sequence triggered by an external reset event will start from phase3 , skipping phase1 and phase2 ss_flash short sequence for code or data flash fatal error 0 the reset sequence triggered by a code or data flash fatal error event will start from phase1 1 the reset sequence triggered by a code or data flash fatal error event will start from phase3 , skipping phase1 and phase2 ss_lvd45 short sequence for 4.5 v low-voltage detected 0 the reset sequence triggered by a 4.5 v low-voltage detected event will start from phase1 1 the reset sequence triggered by a 4.5 v low- voltage detected event will start from phase3, skipping phase1 and phase2 ss_cmu_fhl short sequence for cmu clock frequency higher/lower than reference 0 the reset sequence triggered by a cmu clock frequency higher/lower than reference event will start from phase1 1 the reset sequence triggered by a cmu clock frequency higher/lower than reference event will start from phase3 , skipping phase1 and phase2 ss_cmu_olr short sequence for fxosc freq uency lower than reference 0 the reset sequence triggered by a fxosc freq uency lower than reference event will start from phase1 1 the reset sequence triggered by a fxosc freq uency lower than reference event will start from phase3 , skipping phase1 and phase2 RM0017 reset generation module (mc_rgm) doc id 14629 rev 8 210/904 standby reset sequence register (rgm_stdby) this register defines the reset sequence to be applied on standby mode exit. it can be accessed in read/write in either supervisor mode or test mode. it can be accessed in read only in user mode. ss_fmpll short sequence for fmpll fail 0 the reset sequence triggered by a fmpll fail event will start from phase1 1 the reset sequence triggered by a fmpll fail event will start from phase3 , skipping phase1 and phase2 ss_chkstop short sequence for checkstop reset 0 the reset sequence triggered by a checkstop reset event will start from phase1 1 the reset sequence triggered by a checkstop reset event will start from phase3 , skipping phase1 and phase2 ss_soft short sequence for software reset 0 the reset sequence triggered by a software reset event will start from phase1 1 the reset sequence triggered by a software reset event will start from phase3 , skipping phase1 and phase2 ss_core short sequence for debug control core reset 0 the reset sequence triggered by a debug control core reset event will start from phase1 1 the reset sequence triggered by a debug control core reset event will start from phase3 , skipping phase1 and phase2 ss_jtag short sequence for jtag initiated reset 0 the reset sequence triggered by a jtag initiated reset event will start from phase1 1 the reset sequence triggered by a jtag initiated reset event will start from phase3 , skipping phase1 and phase2 table 86. functional event short sequence regist er (rgm_fess) field d escriptions (continued) field description figure 83. standby reset sequence register (rgm_stdby) address 0xc3fe_401a access: supervisor read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r00000000 boot_from_bkp_ram 0000000 w reset0000000000000000 reset generation module (mc_rgm) RM0017 211/904 doc id 14629 rev 8 note: this register is reset on any enable d ?destructive? or ?functional? reset event. functional bidirectional reset enable register (rgm_fbre) this register enables the generation of an external reset on functional reset. it can be accessed in read/write in either supervisor mode or test mode. it can be accessed in read in user mode. table 87. standby reset sequence regi ster (rgm_stdby) field descriptions field description boot_ from_ bkp_ram boot from backup sram indicator ? this bit indicates whether the system will boo t from backup sram or flash out of standby exit. 0 boot from default boot location on standby exit 1 boot from backup sram on standby exit figure 84. functional bidirectional reset enable register (rgm_fbre) address 0xc3fe_401c access: supervisor read/write 0123456789101112131415 r be_exr 000000 be_flash be_lvd45 be_cmu_fhl be_cmu_olr be_fmpll be_chkstop be_soft be_core be_jtag w por0000000000000000 table 88. functional bidirectional reset enable register (rgm_fbre) field descriptions field description be_exr bidirectional reset enable for external reset 0 reset is asserted on an external reset event if the reset is enabled 1 reset is not asserted on an external reset event be_flash bidirectional reset enable for co de or data flash fatal error 0 reset is asserted on a code or data flash fatal error event if the reset is enabled 1 reset is not asserted on a code or data flash fatal error event be_lvd45 bidirectional reset enable for 4.5 v low-voltage detected 0 reset is asserted on a 4.5 v low-voltage detected event if t he reset is enabled 1 reset is not asserted on a 4.5 v low-voltage detected event be_cmu_fhl bidirectional reset enable for cmu clock frequency higher/lower than reference 0 reset is asserted on a cmu clock frequency hig her/lower than referenc e event if the reset is enabled 1 reset is not asserted on a cmu clock frequ ency higher/lower than reference event be_cmu_olr bidirectional reset enable for fxosc frequency lower than reference 0 reset is asserted on a fxosc frequency lower than reference event if the reset is enabled 1 reset is not asserted on a fxosc frequency lower than reference event RM0017 reset generation module (mc_rgm) doc id 14629 rev 8 212/904 9.4 functional description 9.4.1 reset state machine the main role of mc_rgm is the generation of the reset sequence which ensures that the correct parts of the device are reset based on the reset source event. this is summarized in ta bl e 8 9 . note: jtag logic has its own independent reset control and is not controlled by the mc_rgm in any way. be_fmpll bidirectional reset en able for fmpll fail 0 reset is asserted on a fmpll fail event if the reset is enabled 1 reset is not asserted on a fmpll fail event be_chkstop bidirectional reset enable for checkstop reset 0 reset is asserted on a checkstop reset event if the reset is enabled 1 reset is not asserted on a checkstop reset event be_soft bidirectional reset enab le for software reset 0 reset is asserted on a software re set event if the reset is enabled 1 reset is not asserted on a software reset event be_core bidirectional reset enable fo r debug control core reset 0 reset is asserted on a debug control core reset event if the reset is enabled 1 reset is not asserted on a debug control core reset event be_jtag bidirectional reset enable for jtag initiated reset 0 reset is asserted on a jtag initiated reset event if the reset is enabled 1 reset is not asserted on a jtag initiated reset event table 88. functional bidirectional reset enable register (rgm_fbre) field descriptions (continued) field description table 89. mc_rgm reset implications source what gets reset external reset assertion boot mode capture power-on reset all yes yes ?destructive? resets all except some clock/reset management yes yes external reset all except some clock/reset management and debug yes yes ?functional? resets all except some clock/reset management and debug programmable (1) 1. the assertion of the external reset is controlled via the rgm_fbre register programmable (2) 2. the boot mode is captured if the external reset is asserted shortened ?functional? resets (3) 3. the short sequence is enabled via the rgm_fess register flip-flops except some clock/reset management programmable (1) programmable (2) reset generation module (mc_rgm) RM0017 213/904 doc id 14629 rev 8 the reset sequence is comprised of five phases managed by a state machine, which ensures that all phases are correctly processed through waiting for a minimum duration and until all processes that need to occur during that phase have been completed before proceeding to the next phase. the state machine used to produce the reset sequence is shown in figure 85 . RM0017 reset generation module (mc_rgm) doc id 14629 rev 8 214/904 x figure 85. mc_rgm state machine phase0 phase1 phase2 phase3 idle duration 3 fast internal rc oscill ator (16 mhz) clock cycles firc stable, vreg voltage okay done duration 350 fast internal rc oscillator (16 mhz) clock cycles duration 8 fast internal rc oscillator (16 mhz) clock cycles code and data flash initialization done duration 40 fast internal rc oscillator (16 mhz) clock cycles code and data flash initialization done fast internal rc oscillator (16 mhz) clock is running power-up has completed power-on or enabled ?destructive? reset enabled non- shortened external or ?functional? reset 1 enabled shortened external or ?functional? reset code and data flash initialization done reset released reset generation module (mc_rgm) RM0017 215/904 doc id 14629 rev 8 phase0 phase this phase is entered immediately from any phase on a power-on or enabled ?destructive? reset event. the reset state machine exits phase0 and ente rs phase1 on verification of the following: power-up has completed fast internal rc oscillator (16 mhz) clock is running all enabled ?destructive? resets have been processed all processes that need to be done in phase0 are completed ? firc stable, vreg voltage okay a minimum of 3 fast internal rc oscillator (16 mhz) clock cycles have elapsed since power-up completion and the last enabled ?destructive? reset event phase1 phase this phase is ent ered either on exit from phase0 or immediately from phase2, phase3, or idle on a non-masked external or ?functional? reset event if it has not been configured to trigger a ?short? sequence. th e reset state machin e exits phase1 and enters phase2 on verification of the following: all enabled, non-shortened ?functional? resets have been processed a minimum of 350 fast internal rc oscillato r (16 mhz) clock cycles have elapsed since the last enabled external or non-shortened ?functional? reset event phase2 phase this phase is ent ered on exit from ph ase1. the reset state ma chine exits phase2 and enters phase3 on verification of the following: all processes that need to be done in phase2 are completed ? code and data flash initialization a minimum of 8 fast internal rc oscillator (16 mhz) clock cycles have elapsed since entering phase2 phase3 phase this phase is a entered either on exit from phase2 or immediately from idle on an enabled, shortened ?functiona l? reset event. the reset st ate machine exits phase3 and enters idle on verification of the following: all processes that need to be done in phase3 are completed ? code and data flash initialization a minimum of 40 fast internal rc oscillator (16 mhz) clock cycles have elapsed since the last enabled, shortened ?functional? reset event idle phase this is the final phase and is entered on exit from phase3. when this phase is reached, the mc_rgm releases control of the system to the platform and waits for new reset events that can trigger a reset sequence. RM0017 reset generation module (mc_rgm) doc id 14629 rev 8 216/904 9.4.2 destructive resets a ?destructive? reset indicates that an event has occurred after which critical register or memory content can no longer be guaranteed. the status flag associated with a given ?destructive? reset event (rgm_des.f_ reset generation module (mc_rgm) RM0017 217/904 doc id 14629 rev 8 9.4.4 functional resets a ?functional? reset indicates that an event has occurred after which it can be guaranteed that critical register and me mory content is still intact. the status flag associated with a given ?functional? reset event (rgm_fes.f_ RM0017 reset generation module (mc_rgm) doc id 14629 rev 8 218/904 the alternate event is cleared by deasserting the source of the request (i.e. at the reset source that caused the alternate request) and also clearing the appropriate rgm_f/des status bit. note: alternate requests (safe mode as well as interrupt requests) are generated asynchronously. note: if a masked ?destructive? reset event which is configured to generate a safe mode/interrupt request occurs during phase0, it is igno red, and the mc_rgm will not send any safe mode/interrupt request to the mc_me. the same is true for masked ?functional? reset events during phase1. 9.4.7 boot mode capturing the mc_rgm provides sampling of the boot mode pa[8] and pa[9] for use by the system to determine the boot mode. this sampling is done five fast internal rc oscillator (16 mhz) clock cycles before the rising edge of reset. t he result of the sampling is then provided to the system. for each bit, a value of ?1? is produced only if each of the oldest three of the five samples have the value ?1?, other wise a value of ?0? is produced. note: in order to ensure that the boot mode is correctly captured, the application needs to apply the valid boot mode value to the de vice at least five fast inter nal rc oscillator (16 mhz) clock periods before the external reset deassertion crosses the v ih threshold. note: reset can be low as a consequence of the inte rnal reset generation. this will force re- sampling of the boot mode pins. table 90. mc_rgm alternate event selection rgm_f/derd bit value rgm_f/dear bit value generated event 0 x reset 1 0 safe mode request 1 1 interrupt request power control unit (mc_pcu) RM0017 219/904 doc id 14629 rev 8 10 power control unit (mc_pcu) 10.1 introduction 10.1.1 overview the power control unit (mc_pcu) is used to reduce the overall soc power consumption. power can be saved by disconnecting parts of the soc from the power supply via a power switching device. the soc is grouped into multiple parts having this capability which are called ?power domains?. when a power domain is disconnected from th e supply, the power consumption is reduced to zero in that domain. any status information of such a power domain is lost. when re- connecting a power domain to the supply voltage, the domain draws an increased current until the power domain reaches its operational voltage. power domains are controlled on a device mode basis. for each mode, software can configure whether a power domain is connected to the supply voltage (power-up state) or disconnected (power-down state). maximum power saving is reached by entering the standby mode. on each mode change request, the mc_pcu evaluates the power domain settings in the power domain configuration registers and initiates a power-down or a power-up sequence for each individual power domain. the power-up/down sequences are handled by finite state machines to ensure a smooth and safe transition from one power state to the other. exiting the standby mode can only be done via a system wakeup event as all power domains other than power domain #0 are in the power-down state. in addition, the mc_pcu acts as a bridge for mapping the vreg peripheral to the mc_pcu address space. figure 86 depicts the mc_pcu block diagram. RM0017 power control unit (mc_pcu) doc id 14629 rev 8 220/904 10.1.2 features the mc_pcu includes the following features: support for 3 power domains support for device modes reset, drun, safe, test, run0?3, halt, stop, and standby (for further mode details, please see the mc_me chapter) power states updating on each mode change and on system wakeup a handshake mechanism for power state changes thus guaranteeing operable voltage maps the vreg registers to the mc_pcu address space 10.1.3 modes of operation the mc_pcu is available in all device modes. mc_me firc vreg wkpu power domains power domain state machines registers platform interface mc_pcu figure 86. mc_pcu block diagram mapped module interface mapped peripheral core power control unit (mc_pcu) RM0017 221/904 doc id 14629 rev 8 10.2 external signal description the mc_pcu has no connections to any external pins. 10.3 memory map and register definition note: any access to unused registers as well as write accesses to read-only registers will: ? not change register content ? cause a transfer error table 91. mc_pcu register description address name description size access location supervisor 0xc3fe_8000 pcu_pconf0 power domain #0 configuration word read on page 10-222 0xc3fe_8004 pcu_pconf1 power domain #1 configuration word read on page 10-224 0xc3fe_8008 pcu_pconf2 power domain #2 configuration word read/write on page 10-224 0xc3fe_8040 pcu_pstat power domain status register word read on page 10-225 table 92. mc_pcu memory map address name 01232756789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0xc3fe _8000 pcu_pconf0 r0000000000000000 w r0 0 stby0 00 stop 0 halt run3 run2 run1 run0 drun safe test rst w 0xc3fe _8004 pcu_pconf1 r0000000000000000 w r0 0 stby0 00 stop 0 halt run3 run2 run1 run0 drun safe test rst w 0xc3fe _8008 pcu_pconf2 r0000000000000000 w r0 0 stby0 00 stop 0 halt run3 run2 run1 run0 drun safe test rst w 0xc3fe _800c ? 0xc3fe _803c reserved RM0017 power control unit (mc_pcu) doc id 14629 rev 8 222/904 10.3.1 register descriptions all registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. the bytes are ordered according to big endian. for example, the pd0 field of the pcu_pstat register may be accessed as a word at address 0xc3fe_8040, as a half-word at address 0xc3fe_8042, or as a byte at address 0xc3fe_8043. power domain #0 configuration register (pcu_pconf0) 0xc3fe _8040 pcu_pstat r0000000000000000 w r0000000000000 pd2 pd1 pd0 w 0x044 ? 0x07c reserved 0xc3fe _8080 ? 0xc3fe _80fc vreg registers 0xc3fe _8100 ? 0xc3fe _bffc reserved table 92. mc_pcu memory map (continued) address name 01232756789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 figure 87. power domain #0 configuration register (pcu_pconf0) address 0xc3fe_8000 access: supervisor read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 stby0 00 stop 0 halt run3 run2 run1 run0 drun safe test rst w reset0010010111111111 power control unit (mc_pcu) RM0017 223/904 doc id 14629 rev 8 this register defines for power domain #0 whether it is on or off in each device mode. as power domain #0 is the always-on power domain (and includes the mc_pcu), none of its bits are programmable. this register is available for completeness reasons. table 93. power domain configurat ion register field descriptions field description rst power domain control during reset mode 0 power domain off 1 power domain on test power domain control during test mode 0 power domain off 1 power domain on safe power domain control during safe mode 0 power domain off 1 power domain on drun power domain control during drun mode 0 power domain off 1 power domain on run0 power domain control during run0 mode 0 power domain off 1 power domain on run1 power domain control during run1 mode 0 power domain off 1 power domain on run2 power domain control during run2 mode 0 power domain off 1 power domain on run3 power domain control during run3 mode 0 power domain off 1 power domain on halt power domain control during halt mode 0 power domain off 1 power domain on stop power domain control during stop mode 0 power domain off 1 power domain on stby0 power domain control during standby mode 0 power domain off 1 power domain on RM0017 power control unit (mc_pcu) doc id 14629 rev 8 224/904 power domain #1 configuration register (pcu_pconf1) this register defines for power domain #1 whether it is on or off in each device mode. the bit field description is the same as in ta b l e 9 3 . as the platform, clock generation, and mode control reside in power domain #1, this power domain is only powered down during the standby mode. therefore, none of the bits is programmable. this register is available for completeness reasons. the difference between pcu_pconf0 and pcu_pconf1 is the reset value of the stby0 bit: during the standby mode, power domain #1 is disconnected from the power supply, and therefore pcu_pconf1.stby0 is always ?0?. power domain #0 is always on, and therefore pcu_pcon f0.stby0 is ?1?. for further details about standby mode, please see section standby mode transition . power domain #2 configuration register (pcu_pconf2) this register defines for power domain #2 whether it is on or off in each device mode. the bit field description is the same as in ta bl e 9 3 . figure 88. power domain #1 configuration register (pcu_pconf1) address 0xc3fe_8004 access: supervisor read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 stby0 00 stop 0 halt run3 run2 run1 run0 drun safe test rst w reset0000010111111111 figure 89. power domain #2 configuration register (pcu_pconf2) address 0xc3fe_8008 access: supervisor read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 stby0 00 stop 0 halt run3 run2 run1 run0 drun safe test rst w reset0000010111111111 power control unit (mc_pcu) RM0017 225/904 doc id 14629 rev 8 power domain status register (pcu_pstat) this register reflects the power status of all available power domains. 10.4 functional description 10.4.1 general the mc_pcu controls all available power domains on a device mode basis. the pcu_pconfn registers specify during wh ich system/user modes a power domain is powered up. the power state for each individual power domain is reflected by the bits in the pcu_pstat register. on a mode change, the mc_pcu evaluates which power domain(s) must change power state. the power state is controlled by a state machine (fsm) for each individual power domain which ensures a clean and safe state transition. 10.4.2 reset / power-on reset after any reset, the soc will tr ansition to the reset mode du ring which all power domains are powered up (see the mc_me chapter). once the reset sequence has been completed, the drun mode is entered and software can begin the mc_pcu configuration. 10.4.3 mc_pcu configuration per default, all power domains are powered in all modes other than standby. software can change the configuration for each power domain on a mode basis by programming the pcu_pconfn registers. figure 90. power domain status register (pcu_pstat) address 0xc3fe_8040 access: supervisor read 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pd2 pd1 pd0 w reset0000000000000111 table 94. power domain status register (pcu_pstat) field descriptions field description pd n power status for power domain # n 0 power domain is inoperable 1 power domain is operable RM0017 power control unit (mc_pcu) doc id 14629 rev 8 226/904 each power domain which is powered down is held in a reset state. read/write accesses to peripherals in those power domain s will result in a transfer error. 10.4.4 mode transitions on a mode change requested by the mc_me, the mc_pcu evaluates the power configurations for all power domains. it compares the settings in the pcu_pconfn registers for the new mode with the settings for the current mode. if the configuration for a power domain differs between the modes, a power state change request is generated. these requests are handled by a finite state machine to ensure a smooth and safe transition from one power state to another. drun, safe, test, run0?3, ha lt, and stop mode transition the drun, safe, test, run0?3, halt, and stop modes allow an increased power saving. the level of power saving is software-controllable via the settings in the pcu_pconfn registers for power domain #2 onwards. the settings for power domains #0 and #1 can not be changed. therefore, power domains #0 and #1 remain connected to the power supply for all modes beside standby. figure 91 shows an example for a mode transition from run0 to halt and back, which will result in power domain #2 being powered down during the halt mode. in this case, pcu_pconf2.halt is programmed to be ?0?. when the mc_pcu receives the mode change request to halt mode, it starts its power- down phase. during the power-down phase, clocks are disabled and the reset is asserted resulting in a loss of all in formation for this power domain. then the power domain is disconnected from the power supply (power-down state). when the mc_pcu receives a mode change request to run0, it starts its power-up phase if pcu_pconf2.run0 is ?1?. the power domain is re-connected to the power supply, and the voltage in power domain #2 will increase slo wly. once the voltage of power domain #2 is new mode power-down run0 voltage in pstat.pd2 halt run0 notes: not drawn to scale; pconf2.run0 = 1; pconf2.halt = 0 current mode power-up phase power domain #2 run0 halt run0 requested by me power-down state power-up state power-up state phase figure 91. mc_pcu events during power sequences (non-standby mode) power control unit (mc_pcu) RM0017 227/904 doc id 14629 rev 8 within an operable range, its clocks are enabled, and its resets are deasserted (power-up state). note: it is possible that, due to a mode change, power-up is requested before a power domain completed its power-down sequence. in this case, the information in that power domain is lost. standby mode transition standby offers the maximum power saving. the level of power saving is software- controllable via the settings in the pcu_pconfn registers for power domain #2 onwards. power domain #0 stays connected to the power supply while power domain #1 is disconnected from the power supply. amongst others power domain #1 contains the platform and the mc_me. therefore this mo de differs from all other user/system modes. once standby is entered it can only be left via a system wakeup. on exiting the standby mode, all power domains are powered up according to the settings in the pcu_pconfn registers, and the drun mode is entered. in drun mode, at least power domains #0 and #1 are powered. figure 92 shows an example for a mode transition from run0 to standby to drun. all power domains which have pcu_pconfn.stby0 cleared will enter power-down phase. in this example only power domain #1 will be disabled during standby mode. when the mc_pcu receives the mode change request to standby mode it starts the power down phase for power domain #1. during the power down phase, clocks are disabled and reset is asserted resulting in a loss of all information fo r this power domain. then the power domain is disconnected from the power supply (power-down state). when the mc_pcu receives a system wakeup request, it starts the power-up phase. the power domain is re-connected to the power su pply and the voltage in power domain #1 will new mode power-down run0 voltage in pstat.pd1 standby notes: not drawn to scale; pconf1.run0 = 1; pconf1.stby0 = 0 current mode power-up phase power domain #1 run0 standby drun requested by me power-down state power-up state power-up state phase mode set due to reset being asserted to power domain #1 wakeup request figure 92. mc_pcu events during power sequences (standby mode) RM0017 power control unit (mc_pcu) doc id 14629 rev 8 228/904 increase slowly. once the voltage is in an operable range, clocks are enabled and the reset is be deasserted (power-up state). note: it is possible that due to a wakeup request, power-up is requested before a power domain completed its power-down sequence. in this case, the information in that power domain is lost. power saving for memories during standby mode all memories which are not powered down during standby mode automatically enter a power saving state. no software configuration is required to enable this power saving state. while a memory is residing in this state an increased power saving is achieved. data in the memories is retained. 10.5 initialization information to initialize the mc_pcu, the registers pc u_pconf2? should be programmed. after programming is done, those registers should no longer be changed. 10.6 application information 10.6.1 standby mode considerations standby offers maximum power saving possibility. but power is only saved during the time a power domain is disconnected from the supp ly. increased power is required when a power domain is re-connected to the power supply. additional power is required during restoring the information (e.g. in the platform). care should be taken that the time during which the soc is operating in standby mo de is significantly longer than the required time for restoring the information. voltage regulators and power supplies RM0017 229/904 doc id 14629 rev 8 11 voltage regulators and power supplies 11.1 voltage regulators the power blocks provide a 1.2 v digital supply to the internal logic of the device. the main supply is (3.3 v?5 v 10%) and digital/regulated output supply is (1.2 v 10%). the voltage regulator used in spc560bx and spc560cx comprises three regulators. high power regulator (hpreg) low power regulator (lpreg) ultra low power regulator (ulpreg) the hpreg and lpreg regulators are switched off during standby mode to save consumption from the regulator itself. in st andby mode, the supply is provided by the ulpreg regulator. in stop mode, the user can configure the hpreg regulator to switch-off (refer to mc_me chapter). in this case, when current is low enough to be handled by lpreg alone, the hpreg regulator is switch-off and the supply is provided by the lpreg regulator. the internal voltage regulator requires an external capacitance (creg) to be connected to the device in order to provide a stable low voltage digital supply to the device. capacitances should be placed on the board as near as possible to the associated pins. the regulator has two digital domains, one for the high power regulator (hpreg) and the low power regulator (lpreg) called ?high power domain? and another one for the ultra low power regulator (ulpreg) called ?standby domain.? for each domain there is a low voltage detector for the 1.2 v output voltage. additionally there are two low voltage detectors for the main/input supply with different thresholds, one at the 3.3 v level and the other one at the 5 v level. 11.1.1 high power regulator (hpreg) the hpreg converts the 3.3 v?5 v input supply to a 1.2 v digital supply. for more information, see the voltage regulator electrical characteristics section of the datasheet. the regulator can be switched off by software. refer to the main voltage regulator control bit (mvron) of the mode configuration registers in the mode entry module chapter of the reference manuals. 11.1.2 low power regulator (lpreg) the lpreg generates power for the device in the stop mode, providing the output supply of 1.2 v. it always sees the minimum external capacitance. the control part of the regulator can be used to disable the low power regulator. it is managed by mc_me. 11.1.3 ultra low power regulator (ulpreg) the ulpreg generates power for the standby domain as well as a part of the main domain and might or might not see the external capacitance. the control circuit of ulpreg can be used to disable the ultra low power regulator by software: this action is managed by mc_me. RM0017 voltage regulators and power supplies doc id 14629 rev 8 230/904 11.1.4 lvds and por there are three kinds of lvd available: 1. lvd_main for the 3.3 v?5 v input supply with thresholds at approximately 3 v level (h) 2. lvd_main5 for the 3.3 v?5 v input supply with threshold at approximately 4.5 v level h 3. lvd_dig for the 1.2 v output voltage the lvd_main and lvd_main5 sense the 3.3 v?5 v power supply for core, shared with io ring supply and indicate when the 3.3 v?5 v supply is stabilized. two lvd_digs are provided in the design. one lvd_dig is placed in the high power domain and senses the hpreg/lpreg output notifying that the 1.2 v output is stable. the other lvd_dig is placed in the standby domain and senses the standby 1.2 v supply level notifying that the 1.2 v output is stable. the reference voltage used for all lvds is generated by the low power reference generator and is trimmed for lvd_dig, using the bits lp[4:7]. therefore, during the pre-trimming period, lvd_dig exhibits higher thresholds, whereas during post trimming, the thresholds come in the desired range. power-down pins are provided for lvds. when lvds are power-down, their outputs are pulled high. por is required to initialize the device during supply rise. por works only on the rising edge of the main supply. to ensure its functioning during the following rising edge of the supply, it is reset by the output of the lvd_main block when main supply reaches below the lower voltage threshold of the lvd_main. por is asserted on power-up when vdd supply is above v porup min (refer to datasheet for details). it will be released onl y after vdd supply is above v porh (refer to datasheet for details). vdd above v porh ensures power management module including internal lvds modules are fully functional. 11.1.5 vreg digital interface the voltage regulator digital interface provides the temporization delay at initial power-up and at exit from low-power modes. a signal, indicating that ultra low power domain is powered, is used at power-up to release reset to temporization counter. at exit from low- power modes, the power-down for high power regulator request signal is monitored by the digital interface and used to release reset to the temporization counter. in both cases, on completion of the delay counter, a end-of-count signal is released, it is gated with an other signal indicating main domain voltage fine in order to release the vregok signal. this is used by mc_rgm to release the reset to the device. it manages other specific requirements, like the transition between high power/low power mode to ultra low power mode avoiding a voltage drop below the permissible threshold limit of 1.08 v. the vreg digital interface also holds control register to mask 5 v lvd status coming from the voltage regulator at the power-up. 11.1.6 register description the vreg_ctl register is mapped to the mc_pcu address space as described in 10, power control unit (mc_pcu) . h. see section ?voltage monitor electr ical characteristic s? of the datasheet for detailed information about this voltage value. voltage regulators and power supplies RM0017 231/904 doc id 14629 rev 8 11.2 power supply strategy from a power-routing perspective, the device is organized as follows. the device provides four dedicated supply domains at package level: 1. hv (high voltage external power supply for i/os and most analog module) ? this must be provided externally th rough vdd_hv/vss_hv power pins. voltage values should be aligned with v dd /v ss . refer to datasheet for details. 2. adc (high voltage external power supply for adc module) ? this must be provided externally through vdd_hv_adc/vss_hv_a dc power pins. voltage values should be aligned with v dd_hv_adc /v ss_hv_adc . refer to datasheet for details. 3. bv (high voltage external power supply for voltage regulator module) ? this must be provided externally throug h vdd_bv_/vss_bv power pins. voltage values should be aligned with v dd /v ss . refer to datasheet for details. 4. lv (low voltage internal power supply for core, fmpll and flash digital logic) ? this is generated internally by embedded voltage regulator and provided to the core, fmpll and flash. three vdd_lv/vss_lv pins pa irs are provided to connect the three decoupling capacitances. this is generated in ternally by internal voltage regulator but provided outside to connect stability capacito r. refer to datasheet for details. figure 93. voltage regulator control register (vreg_ctl) address: 0xc3fe_8080 access: user read/write 0123456789101112131415 r000000000000000 0 w reset000000000000000 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000000000 5v_lvd_mask w reset000000000000000 1 table 95. vreg_ctl field descriptions field description 5v_lvd_mask mask bit for 5 v lvd from regulator this is a read/write bit and must be unmasked by writing a ?1? by software to generate lvd functional reset request to mc_rgm for 5 v trip. 1: 5 v lvd is masked 0: 5 v lvd is not masked. RM0017 voltage regulators and power supplies doc id 14629 rev 8 232/904 the four dedicated supply domains are further divided within the package in order to reduce as much as possible emc and noise issues. hv_io: high voltage pad supply hv_flan: high voltage flash supply hv_osc0reg (i) : high voltage external oscillator and regulator supply hv_adr: high voltage reference for adc module. supplies are further star routed to reduce impact of adc resistive reference on adc capacitive reference accuracy. hv_adv: high voltage supply for adc module bv: high voltage supply for voltage regulator ballast. these two ballast pads are used to supply core and flash. each pad contains two ballasts to supply 80 ma and 20 ma respectively. core is henc e supplied through two ballast s of 80 ma capability and cflash and dflash through two 20 ma ballast s. the hv supply for both ballasts is shorted through double bonding. lv_cor: low voltage supply for the core. it is also used to provide supply for fmpll through double bonding. lv_flan: low voltage supply for flash module n. it is supplied with dedicated ballast and shorted to lv_cor through double bonding. lv _ p l l (j) : low voltage supply for fmpll 11.3 power domain organization based on stringent requirements for current consumption in different operational modes, the device is partitioned into different power domains. organization into these power domains primarily means separate power supplies which are separated from each other by use of power switches (switch sw1 for power domain no. 1 and switch sw2 for power domain no. 2 as shown in figure 94 ). these different separated power supplies are hence enabling to switch off power to certain regions of the de vice to avoid even leakage current consumption in logic supplied by the corresponding power supply. this device employs three primary power domains, namely pd0, pd1 and pd2. as pcu supports dynamic power down of domains based on different device mode, such a possible domain is depicted below in dotted periphery. power domain organization and connections to the internal regulator are depicted in figure 94 . i. regulator ground is separated from oscillator gr ound and shorted to the lv ground through star routing j. during production test, it is also possible to provide the vdd_lv exte rnally through pins by configuring regulator in bypass mode. voltage regulators and power supplies RM0017 233/904 doc id 14629 rev 8 figure 94. power domain organization vdd_lv_bkp vdd pd0 pd1 pcu hpvdd ulpvdd lpvdd sw1 ipe_iso0 sirc rgm firc vgate hv por1hv por2hv nbypass hppd lppd vss vreg api can sampler wkpu cflash dflash rc dig wakeup pads siul option bits reset platform pa 0 pa 1 pa 2 ph15 vdd12 330nf cgm cgl me peripheral set fmpll peripheral set avddref avddsupply avsssupply avssref vdd5_cfla vdd5_dlf 330nf 330nf adc vdd_lv_cor vdd_lv_bkp vdd_lv_bkp domain vdd_lv_fla0 ipe_pd vdd5b vdd_lv_fla1 8 kb sram pd2 24 kb sram sw2 v ss pa x pbx pcx pex pfx pgx e200z0h 16 kb sram jtag RM0017 wakeup unit (wkpu) doc id 14629 rev 8 234/904 12 wakeup unit (wkpu) 12.1 overview the wakeup unit supports 2 internal sources (wkpu[0:1]) and up to 18 (k) external sources (wkpu[2:19]) that can generate interrupts or wakeup events, of which 1 can cause non- maskable interrupt requests. figure 95 is the block diagram of the wakeup unit and its interfaces to other system components. the wakeup vector mapping is shown in ta bl e 9 6 . all unused wkpu pins must use a pull resistor ? either pullup (internal or external) or pulldown (external) ? to ensure no leakage from floating inputs. k. up to 18 external sources in 144-pin lqfp and 208bga; up to 14 external sources in 100-pin lqfp table 96. wakeup vector mapping wakeup number port siu pcr# port input function (1) (can be used in conjunction with wkpu function) wkpu irq to intc irq# wisr register (2) bit position package 64-pin qfp 100-pin qfp 144-pin qfp 208-pin bga wkpu0 api n/a (3) ? wakeup_irq_0 46 eif0 31 ? (3) ? (3) ? (3) ? (3) wkpu1 rtc n/a (3) ?eif130 ? (3) ? (3) ? (3) ? (3) wkpu2 pa1 pcr1 nmi eif2 29 ??? ? wkpu3 pa2 pcr2 ? eif3 28 ??? ? wkpu4 pb1 pcr17 can0-rx eif4 27 ??? ? wkpu5 pc11 pcr43 can1-rx, can4-rx eif5 26 x (4) ?? ? wkpu6 pe0 pcr64 can5-rx eif6 25 x (4) ?? ? wkpu7 pe9 pcr73 can2-rx, can3-rx eif7 24 x (4) ?? ? wkpu8 pb10 pcr26 ? wakeup_irq_1 47 eif8 23 ??? ? wkpu9 pa4 pcr4 ? eif9 22 ??? ? wkpu10 pa15 pcr15 ? eif10 21 ??? ? wkpu11 pb3 pcr19 lin0-rx eif11 20 ??? ? wkpu12 pc7 pcr39 lin1-rx eif12 19 ??? ? wkpu13 pc9 pcr41 lin2-rx eif13 18 ??? ? wkpu14 pe11 pcr75 lin3-rx eif14 17 x (4) ?? ? wkpu15 pf11 pcr91 ? eif15 16 x (4) x (4) ?? wakeup unit (wkpu) RM0017 235/904 doc id 14629 rev 8 figure 95. wkpu block diagram wkpu16 pf13 pcr93 ? wakeup_irq_2 48 eif16 15 x (4) x (4) ?? wkpu17 pg3 pcr99 ? eif17 14 x (4) x (4) ?? wkpu18 pg5 pcr101 ? eif18 13 x (4) x (4) ?? wkpu19 pa0 pcr0 ? eif19 12 ??? ? 1. this column does not contain an exhaustive list of func tions on that pin. rather, it includes peripheral communication functions (such as can and linflex rx) that could be used to wake up the microc ontroller. dspi pins are not included because dspi would typically be used in master mode. 2. wisr, irer, wrer, wifeer, wifeef, wifer, wipuer 3. port not required to use timer functions. 4. unavailable wkpu pins must us e internal pullup enabled using wipuer. table 96. wakeup vector mapping (continued) wakeup number port siu pcr# port input function (1) (can be used in conjunction with wkpu function) wkpu irq to intc irq# wisr register (2) bit position package 64-pin qfp 100-pin qfp 144-pin qfp 208-pin bga ips bus pads interrupt controller peripheral mode / power control irqs system wakeup wakeup 0-19 platform 0-2 nmi / wakeup - configuration irq / wakeup - configuration wakeup unit iomux rtc, etc. 0-19 filter filter filter bypass filter bypass nmi enable bridge RM0017 wakeup unit (wkpu) doc id 14629 rev 8 236/904 12.2 features the wakeup unit supports these distinctive features: non-maskable interrupt support with ? 1 nmi source with bypassable glitch filter ? independent interrupt destination: non-maskable interrupt, critical interrupt, or machine check request ? edge detection external wakeup/interrupt support with ? 3 system interrupt vectors fo r up to 18 interrupt sources ? analog glitch filter per each wakeup line ? independent interrupt mask ? edge detection ? configurable system wakeup triggering from all interrupt sources ? configurable pullup on-chip wakeup support ? 2 wakeup sources ? wakeup status mapped to same register as external wakeup/interrupt status 12.3 external signal description the wakeup unit has 18 signal inputs that can be used as external interrupt sources in normal run mode or as system wakeup sources in all power down modes. the 18 external signal inputs include one si gnal input that can be used as a non-maskable interrupt source in normal run, halt or st op modes or a system wakeup source in stop or standby modes. note: the user should be aware that the wake-up pins are enabled in all modes, therefore, the wake-up pins should be correctly terminated to ensure minimal current consumption. any unused wake-up signal input should be termi nated by using an external pull-up or pull- down, or by internal pull-up enabled at wkpu_wipuer. also, care has to be taken on packages where the wake-up signal inputs are not bonded. for these packages the user must ensure the internal pull-up are enabled for those signals not bonded. 12.4 memory map and register description this section provides a detailed description of all registers accessible in the wkpu module. 12.4.1 memory map ta bl e 9 7 gives an overview on the wkpu registers implemented. wakeup unit (wkpu) RM0017 237/904 doc id 14629 rev 8 note: reserved registers will read as 0, writes will have no effect. if sscm_error[rae] is enabled, a transfer error will be issued when trying to access complete ly reserved register space. 12.4.2 nmi status fl ag register (nsr) this register holds the non-maskable interrupt status flags. table 97. wkpu memory map base address: 0xc3f9_4000 address offset register name location 0x00 nmi status flag register (nsr) on page 12-237 0x04 ? 0x07 reserved 0x08 nmi configuration register (ncr) on page 12-238 0x0c ? 0x13 reserved 0x14 wakeup/interrupt status flag register (wisr) on page 12-239 0x18 interrupt request enable register (irer) on page 12-240 0x1c wakeup request enable register (wrer) on page 12-240 0x20 ? 0x27 reserved 0x28 wakeup/interrupt rising-edge event enable register (wireer) on page 12-241 0x2c wakeup/interrupt falling-edge event enable register (wifeer) on page 12-241 0x30 wakeup/interrupt filter enable register (wifer) on page 12-241 0x34 wakeup/interrupt pullup enable register (wipuer) on page 12-242 figure 96. nmi status flag register (nsr) offset: 0x00 access: user read/write 012 3 4 5 6 7 8 9 10 11 12 13 14 15 r nif0 novf0 00000000000000 ww1c w1c reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 RM0017 wakeup unit (wkpu) doc id 14629 rev 8 238/904 12.4.3 nmi configurat ion register (ncr) this register holds the configuration bits for the non-maskable interrupt settings. table 98. nsr field descriptions field description nif0 nmi status flag if enabled (nree0 or nfee0 set), nif0 causes an interrupt request. 1 an event as defined by nree0 and nfee0 has occurred 0 no event has occurred on the pad novf0 nmi overrun status flag it will be a copy of the current nif0 value whene ver an nmi event occurs, thereby indicating to the software that an nmi occurred while the last one was not yet serviced. if enabled (nree0 or nfee0 set), novf0 causes an interrupt request. 1 an overrun has occurred on nmi input 0 no overrun has occurred on nmi input figure 97. nmi configuration register (ncr) offset: 0x08 access: user read/write 0123456789101112131415 r nlock0 ndss0 nwre0 0 nree0 nfee0 nfe0 00000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 table 99. ncr field descriptions field description nlock0 nmi configuration lock register writing a 1 to this bit locks the co nfiguration for the nmi until it is unlocked by a system reset. writing a 0 has no effect. ndss0 nmi destination source select 00 non-maskable interrupt 01 critical interrupt 10 machine check request 11 reserved?no nmi, critical interrupt, or machine check request generated wakeup unit (wkpu) RM0017 239/904 doc id 14629 rev 8 note: writing a ?0? to both nree0 and nfee0 disables the nmi functionality completely (that is, no system wakeup or interrupt will be generated on any pad activity)! 12.4.4 wakeup/interrupt stat us flag register (wisr) this register holds the wakeup/interrupt flags. note: status bits associated with on-chip wakeup sources are located to the left of the external wakeup/interrupt status bits and are read only. the wakeup for these sources must be nwre0 nmi wakeup request enable 1 a set nif0 bit or set novf0 bit causes a system wakeup request 0 system wakeup requests from the corresponding nif0 bit are disabled note: software should only enable the nmi after the ivpr/ivor registers have been configured. this should be noted when booting from reset or standby mode as all registers will have been cleared to their reset state. nree0 nmi rising-edge events enable 1 rising-edge event is enabled 0 rising-edge event is disabled nfee0 nmi falling-edge events enable 1 falling-edge event is enabled 0 falling-edge event is disabled nfe0 nmi filter enable enable analog glitch filter on the nmi pad input. 1 filter is enabled 0 filter is disabled table 99. ncr field de scriptions (continued) field description figure 98. wakeup/interrupt status flag register (wisr) offset: 0x14 access: user read/write 012345678910111213141516171819202122232425262728293031 r000000000000 eif[19:0] (1) 1. eif[18:15] are not avail able in all 100-pin packages. w w1c reset00000000000000000000000000000000 table 100. wisr field descriptions field description eif[x] external wakeup/interru pt wkpu[x] status flag this flag can be cleared only by writing a 1. writ ing a 0 has no effect. if en abled (irer[x]), eif[x] causes an interrupt request. 1 an event as defined by wireer and wifeer has occurred 0 no event has occurred on the pad RM0017 wakeup unit (wkpu) doc id 14629 rev 8 240/904 configured and cleared at the on-chip wakeup source. also, the configuration registers for the external interrupts/wakeups do not have corresponding bits. 12.4.5 interrupt request enable register (irer) this register is used to enable the interrupt messaging from the wakeup/interrupt pads to the interrupt controller. 12.4.6 wakeup request enable register (wrer) this register is used to enable the system wakeup messaging from the wakeup/interrupt pads to the mode entry and power control modules. figure 99. interrupt request enable register (irer) offset: 0x18 access: user read/write 012345678910111213141516171819202122232425262728293031 r000000000000 eire[19:0] (1) 1. eire[18:15] are not available in all 100-pin packages. w w1c reset00000000000000000000000000000000 table 101. irer field descriptions field description eire[x] external interrupt request enable x 1 a set eif[x] bit causes an interrupt request 0 interrupt requests from the co rresponding eif[x] bit are disabled figure 100. wakeup request enable register (wrer) offset: 0x1c access: user read/write 012345678910111213141516171819202122232425262728293031 r000000000000 wre[19:0] (1) 1. wre[18:15] are not available in all 100-pin packages. w reset00000000000000000000000000000000 table 102. wrer field descriptions field description wre[x] external wakeup request enable x 1 a set eif[x] bit causes a system wakeup request 0 system wakeup requests from the corresponding eif[x] bit are disabled wakeup unit (wkpu) RM0017 241/904 doc id 14629 rev 8 12.4.7 wakeup/interrupt rising-edge event enable register (wireer) this register is used to enable rising-edge triggered events on the corresponding wakeup/interrupt pads. note: the rtc_api can only be configured on the rising edge. . 12.4.8 wakeup/interrupt falling-edge event enable register (wifeer) this register is used to enable falling-edge tr iggered events on the corresponding wakeup/interrupt pads. 12.4.9 wakeup/interrupt filter enable register (wifer) this register is used to enable an analog filter on the corresponding interrupt pads to filter out glitches on the inputs. figure 101. wakeup/interrupt rising-edge event enable register (wireer) offset: 0x28 access: user read/write 012345678910111213141516171819202122232425262728293031 r000000000000 iree[19:0] (1) 1. iree[18:15] are not avail able in all 100-pin packages. w reset00000000000000000000000000000000 table 103. wireer field descriptions field description iree[x] external interrupt rising-edge events enable x 1 rising-edge event is enabled 0 rising-edge event is disabled figure 102. wakeup/interrupt falling-edge event enable register (wifeer) offset: 0x2c access: user read/write 012345678910111213141516171819202122232425262728293031 r000000000000 ifee[19:0] (1) 1. ifee[18:15] are not available in all 100-pin packages. w reset00000000000000000000000000000000 table 104. wifeer field descriptions field description ifeex external interrupt falling-edge events enable x 1 falling-edge event is enabled 0 falling-edge event is disabled RM0017 wakeup unit (wkpu) doc id 14629 rev 8 242/904 note: there is no analog filter for the rtc_api. 12.4.10 wakeup/interrupt pullup enable register (wipuer) this register is used to enable a pullup on the corresponding interrupt pads to pull an unconnected wakeup/interrupt input to a value of ?1?. 12.5 functional description 12.5.1 general this section provides a complete functional description of the wakeup unit. figure 103. wakeup/interrupt filter enable register (wifer) offset: 0x30 access: user read/write 012345678910111213141516171819202122232425262728293031 r000000000000 ife[19:0] (1) 1. ife[18:15] are not avail able in all 100-pin packages. w reset00000000000000000000000000000000 table 105. wifer field descriptions field description ife[x] external interrupt filter enable x enable analog glitch filter on the external interrupt pad input. 1 filter is enabled 0 filter is disabled figure 104. wakeup/interrupt pullup enable register (wipuer) offset: 0x34 access: user read/write 012345678910111213141516171819202122232425262728293031 r000000000000 ipue[19:0] (1) 1. ipue[18:15] are not available in all 100-pin packages. w reset00000000000000000000000000000000 table 106. wipuer field descriptions field description ipue[x] external interrupt pullup enable x 1 pullup is enabled 0 pullup is disabled wakeup unit (wkpu) RM0017 243/904 doc id 14629 rev 8 12.5.2 non-maskable interrupts the wakeup unit supports one non-maskable interrupt which is allocated to the following pins: 100-pin lqfp: pin 7 144-pin lqfp: pin 11 208-pin bga: pin f3 the wakeup unit supports the generation of three types of interrupts from the nmi. the wakeup unit supports the capturing of a second event per nmi input before the interrupt is cleared, thus reducing the chance of losing an nmi event. each nmi passes through a bypassable analog glitch filter. note: glitch filter control and pad configuration sh ould be done while the nm i is disabled in order to avoid erroneous triggering by glitches caused by the configuration process itself. figure 105. nmi pad diagram nmi management the nmi can be enabled or disabled using the single ncr register laid out to contain all configuration bits for an nmi in a single byte (see figure 97 ). the pad defined as an nmi can be configured by the user to recognize interrupts with an active rising edge, an active glitch filter edge detect flag overrun destination nmi critical irq machine check cpu mode/ pwr ctl ndss0 nwre0 nree0 nfee0 nfe0 nmi configuration register (ncr) wakeup enable RM0017 wakeup unit (wkpu) doc id 14629 rev 8 244/904 falling edge or both edges being active. a setting of ha ving both edge events disabled results in no interrupt being detected and should not be configured. the active nmi edge is controlled by the user through the configuration of the nree0 and nfee0 bits. note: after reset, nree0 and nfee0 are set to ?0?, therefore the nmi functionality is disabled after reset and must be enabled explicitly by software. once the pad?s nmi functionality has been enabled, the pad cannot be reconfigured in the iomux to override or disable the nmi. the nmi destination interrupt is controlled by the user through the configuration of the ndss0 field. see ta bl e 9 9 for details. an nmi supports a status flag and an overrun flag which are located in the nsr register (see figure 96 ). the nif0 and novf0 fields in this register are cleared by writing a ?1? to them; this prevents inadvertent overwriting of other flags in the register. the status flag is set whenever an nmi event is detected. the overrun flag is set whenever an nmi event is detected and the status flag is set (that is, has not yet been cleared). note: the overrun flag is cleared by writing a ?1? to the appropriate overrun bit in the nsr register. if the status bit is cleared and the overrun bi t is still set, the pend ing interrupt will not be cleared. 12.5.3 external wakeups/interrupts the wakeup unit supports up to 18 external wakeup/interrupts which can be allocated to any pad necessary at the soc level. this allocation is fixed per soc. the wakeup unit supports up to three interrupt vectors to the interrupt controller of the soc. each interrupt vector can support up to the number of external interrupt sources from the device pads with the total across all vectors being equal to the number of external interrupt sources. each external interrupt source is assigned to exactly one interrupt vector. the interrupt vector assignment is sequential so that one interrupt vector is for external interrupt sources 0 through n-1, the next is for n through n+m-1, and so forth. see figure 106 for an overview of the external interrupt implementation for the example of three interrupt vectors with up to eight external interrupt sources each. wakeup unit (wkpu) RM0017 245/904 doc id 14629 rev 8 figure 106. external interrupt pad diagram all of the external interrupt pads within a single group have equal priority. it is the responsibility of the us er software to search through t he group of sources in the most appropriate way for their application. note: glitch filter control and pad configuration sh ould be done while the external interrupt line is disabled in order to avoid erroneous triggering by glitches caused by the configuration process itself. external interrupt management each external interrupt can be enabled or disabled independently. this can be performed using a single rolled up register ( figure 99 ). a pad defined as an external interrupt can be configured by the user to recognize external interrupts with an active rising edge, an active falling edge or both e dges being active. note: writing a ?0? to both iree[x] and ifee[x] disables the external interrupt functionality for that pad completely (that is, no system wakeup or interrupt will be generated on any activity on that pad)! the active irq edge is controlled by the users through the configuration of the registers wireer and wifeer. each external interrupt supports an individual flag which is held in the flag register (wisr). the bits in the wisr[eif] field are cleared by writing a ?1? to them; this prevents inadvertent overwriting of other flags in the register. 12.5.4 on-chip wakeups the wakeup unit supports two on-chip wakeup sources. it combines the on-chip wakeups with the external ones to generate a single wakeup to the system. interrupt vectors pads wireer[19:0] interrupt edge enable wifeer[19:0] falling rising edge detection analog glitch filter wifer[19:0] glitch filter enable interrupt enable or or or irq_19_16 irq_15_08 irq_07_00 flag[19:16] flag[15:8] wisr[19:0] flag[7:0] wrer[19:0] wakeup enable mode / pwr ctl irer[19:0] rtc api interrupt controller RM0017 wakeup unit (wkpu) doc id 14629 rev 8 246/904 on-chip wakeup management in order to allow software to determine the wakeup source at one location, on-chip wakeups are reported along with external wakeups in the wisr register (see figure 98 for details). enabling and clearing of these wakeups are done via the on-chip wakeup source?s own registers. real time clock / autonomous periodic interrupt (rtc/api) RM0017 247/904 doc id 14629 rev 8 13 real time clock / autonomous periodic interrupt (rtc/api) 13.1 overview the rtc/api is a free running counter used for time keeping applications. the rtc may be configured to generate an interrupt at a predefined interval independent of the mode of operation (run mode or low power mode). if in a low power mode when the rtc interval is reached, the rtc first generates a wakeup and then assert the interrupt request. the rtc also supports an autonomous periodic interrupt (api) function used to generate a periodic wakeup request to exit a low power mode or an interrupt request. 13.2 features features of the rtc/api include: 3 selectable counter clock sources ? sirc (128 khz) ? sxosc (32 khz) ? firc (16 mhz) optional 512 prescaler and optional 32 prescaler 32-bit counter ? supports times up to 1.5 months with 1 ms resolution ? runs in all modes of operation ? reset when disabled by software and by por 12-bit compare value to support interrupt intervals of 1 s up to greater than 1 hr with 1 s resolution rtc compare value changeable while counter is running rtc status and control register are reset only by por autonomous periodic interrupt (api) ? 10-bit compare value to support wakeup intervals of 1.0 ms to 1 s ? compare value changeable while counter is running configurable interrupt for rtc match, api match, and rtc rollover configurable wakeup event for rtc match, api match, and rtc rollover RM0017 real time clock / autonom ous periodic interrupt (rtc/api) doc id 14629 rev 8 248/904 figure 107. rtc/api block diagram 0 1 2 clksel[0:1] 3 sirc firc sxosc == cnten rtccnt rtcval 10:21 rtcf rtcie rtc interrupt offset reg == 22:31 api wakeup + load 22:31 apival apien reset reset 32-bit counter sync sync rtc wakeup apif apiie api sync interrupt rovrf sync reserved div512 div32 div32en div512en rtcie rovren real time clock / autonomous periodic interrupt (rtc/api) RM0017 249/904 doc id 14629 rev 8 figure 108. clock gating for rtc clocks 13.3 device-specific information for spc560bx and spc560cx, the device specific information is the following: sxosc, firc and sirc clocks are provided as counter clocks for the rtc. default clock on reset is sirc divided by 4. the rtc will be reset on destructive reset, with the exception of software watchdog reset. the rtc provides a configurable divider by 512 to be optionally used when firc source is selected. 13.4 modes of operation 13.4.1 functional mode there are two functional modes of operation for the rtc: normal operation and low power mode. in normal operation, all rtc registers can read or written and the input isolation is 32-bit counter cell c.g. en sirc (cnten & clksel== 2?b00) cell en sxosc (cnten & clksel== 2?b01) cell en firc (cnten & clksel== 2?b10) cell c.g. en reserved (cnten & clksel== 2?b11) c.g. c.g. 0 1 2 clksel[0:1] 3 cell c.g. en 1 0 div 512 cell c.g. en 1 0 div 32 div512en div32en cnten RM0017 real time clock / autonom ous periodic interrupt (rtc/api) doc id 14629 rev 8 250/904 disabled. the rtc/api and associated interrupts are optionally enabled. in low power mode, the bus interface is disabled and the input isolation is enabled. the rtc/api is enabled if enabled prior to entry into low power mode. 13.4.2 debug mode on entering into the debug mode the rtc counter freezes on the last valid count if the rtcc[frzen] is set. on exit from debug mode counter continues from the frozen value. 13.5 register descriptions table 107 lists the rtc/api registers. 13.5.1 rtc supervisor control register (rtcsupv) the rtcsupv register contains the supv bit which determines whether other registers are accessible in supervisor mode or user mode. note: rtcsupv register is access ible only in supervisor mode. table 107. rtc/api register map base address: 0xc3fe_c000 address offset register location 0x0 rtc supervisor control register (rtcsupv) on page 13-250 0x4 rtc control register (rtcc) on page 13-251 0x8 rtc status register (rtcs) on page 13-253 0xc rtc counter register (rtccnt) on page 13-254 figure 109. rtc supervisor control register (rtcsupv) offset: 0x0 access: read/write 012345678910111213141516171819202122232425262728293031 r supv w reset10000000000000000000000000000000 table 108. rtcsupv field descriptions field description supv rtc supervisor bit 0 all registers are accessible in both user as well as supervisor mode. 1 all other registers are accessible in supervisor mode only. real time clock / autonomous periodic interrupt (rtc/api) RM0017 251/904 doc id 14629 rev 8 13.5.2 rtc control register (rtcc) the rtcc register contains: rtc counter enable rtc interrupt enable rtc clock source select rtc compare value api enable api interrupt enable api compare value figure 110. rtc control register (rtcc) offset: 0x4 access: user read/write 0123 4 56789101112131415 r cnten rtcie frzen rovren rtcval w reset0000 0 00000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r apien apiie clksel div512en div32en apival w reset0000 0 00000000000 table 109. rtcc field descriptions field description cnten counter enable the cnten field enables the rtc counter. making cnten bit 1?b0 has the effect of asynchronously resetting (synchronous reset negation) all the rtc and api logic. this allows for the rtc configuration and clock source select ion to be updated without causing synchronization issues. 1 counter enabled 0 counter disabled rtcie rtc interrupt enable the rtcie field enables inte rrupts requests to the system if rtcf is asserted. 1 rtc interrupts enabled 0 rtc interrupts disabled frzen freeze enable the counter freezes on entering the debug mode on the last valid count value if the frzen bit is set. after coming out of the debug mode, th e counter starts from the frozen value. 0 counter does not freeze in debug mode. 1 counter freezes in debug mode. RM0017 real time clock / autonom ous periodic interrupt (rtc/api) doc id 14629 rev 8 252/904 rovren counter roll over wakeup/interrupt enable the rovren bit enables wakeup and interrupt requests when the rtc has rolled over from 0xffff_ffff to 0x0000_0000. the rtcie bit must al so be set in order to generate an interrupt from a counter rollover. 1 rtc rollover wakeup/interrupt enabled 0 rtc rollover wakeup/interrupt disabled rtcval rtc compare value the rtcval bits are compared to bits 10:21 of the rtc counter and if match sets rtcf. rtcval can be updated when the counter is running. note: rtcval = 0 does not generate an interrupt. apien autonomous periodic interrupt enable the apien bit enables the autonomous periodic interrupt function. 1 api enabled 0 api disabled apiie api interrupt enable the apiie bit enables interrupts reques ts to the system if apif is asserted. 1 api interrupts enabled 0 api interrupts disabled clksel clock select this field selects the clock source for the rtc. clksel may only be updated when cnten is 0. the user should ensure that oscillator is enabl ed before selecting it as a clock source for rtc. 00 sxosc 01 sirc 10 firc 11 reserved div512en divide by 512 enable the div512en bit enables the 512 clock divide r. div512en may only be updated when cnten is 0. 0 divide by 512 is disabled. 1 divide by 512 is enabled. div32en divide by 32 enable the div32en bit enables the 32 clock divider. di v32en may only be updated when cnten is 0. 0 divide by 32 is disabled. 1 divide by 32 is enabled. apival api compare value the apival field is compared with bits 22:31 of the rtc counter and if match asserts an interrupt/wakeup request. apival may only be upd ated when apien is 0 or api function is undefined. note: api functionality starts only when apival is non zero. the first api interrupt takes two more cycles because of synchronization of apival to the rtc clock. after that interrupts are periodic in nature. the minimum supported value of apival is 4. table 109. rtcc field descriptions (continued) field description real time clock / autonomous periodic interrupt (rtc/api) RM0017 253/904 doc id 14629 rev 8 13.5.3 rtc status register (rtcs) the rtcs register contains: rtc interrupt flag api interrupt flag rollovr flag figure 111. rtc status register (rtcs) offset: 0x8 access: user read/write 0123456789101112131415 r 0 0 rtcf 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 apif 0 0 rovrf 0 0 0 0 0 0 0 0 0 0 w reset0000000000000000 table 110. rtcs field descriptions field description rtcf rtc interrupt flag the rtcf bit indicates that the rtc counter has reached the counter value matching rtcval. rtcf is cleared by writing a 1 to rtcf. writing a 0 to rtcf has no effect. 1 rtc counter matches rtcval 0 rtc counter is not equal to rtcval apif api interrupt flag the apif bit indicates that the rtc counter has reached the counter value matching api offset value. apif is cleared by writing a 1 to apif. writing a 0 to apif has no effect. 1 api interrupt 0 no api interrupt note: the periodic interrupt comes after apival[0:9] + 1?b1 rtc counts rovrf counter roll over interrupt flag the rovrf bit indicates that the rtc has rolled over from 0xffff_ffff to 0x0000_0000. rovrf is cleared by writing a 1 to rovrf. 1 rtc has rolled over 0 rtc has not rolled over RM0017 real time clock / autonom ous periodic interrupt (rtc/api) doc id 14629 rev 8 254/904 13.5.4 rtc counter register (rtccnt) the rtccnt register contains the current value of the rtc counter. 13.6 rtc functional description the rtc consists of a 32-bit free running counter enabled with the rtcc[cnten] bit (cnten when negated asynchronously resets the counter and synchronously enables the counter when enabled). the value of the counter may be read via the rtccnt register. note that due to the clock synchronization , the rtccnt value may actually represent a previous counter value. the difference between the counter and the read value depends on ratio of counter clock and system clock. maximum possible difference between the two is 6 count values. the clock source to the coun ter is selected with the rtcc[c lksel] field, which gives the options for clocking the rtc/api. the output of the clock mux can be optionally divided by combination of 512 and 32 to give a 1 ms rtc/api count period for different clock sources. note that the rtcc[cnten] bit must be disabled when the rtc/api clock source is switched. when the counter value for counter bits 10:21 match the 12-bit value in the rtcc[rtcval] field, then the rtcs[rtcf] interrupt flag bit is set (after proper clock synchronization). if the rtcc[rtcie] interrupt enable bit is set, then the rtc interrupt request is generated. the rtc supports interrupt requests in the range of 1 s to 4096 s (> 1 hr) with a 1 s resolution. if there is a match while in low power mode then the rtc will first generate a wakeup request to force a wakeup to run mode, then the rtcf flag will be set. a rollover wakeup and/or interrupt can be generated when the rtc transitions from a count of 0xffff_ffff to 0x0000_0000. the rollover flag is enabled by setting the rtcc[rovren] bit. an rtc counter rollover wit h this bit will cause a wakeup from low power mode. an interrupt request is generated for an rtc counter rollover when both the rtcc[rovren] and rtcc[rtcie] bits are set. all the flags and counter values are synchronized with the system clock. it is assumed that the system clock frequency is always more than or equal to the rtc_clk used to run the counter. figure 112. rtc counter register (rtccnt) offset: 0xc access: read 0 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425262728293031 r rtccnt w reset00000000000000000000000000000000 table 111. rtccntfield descriptions field description rtccnt rtc counter value due to the clock synchronization, the rtccnt valu e may actually represent a previous counter value. real time clock / autonomous periodic interrupt (rtc/api) RM0017 255/904 doc id 14629 rev 8 13.7 api functional description setting the rtcc[apien] bit enables the autonomous interrupt function. the 10-bit rtcc[apival] field selects the time interval for triggering an interrupt and/or wakeup event. since the rtc is a free running counter, the apival is added to the current count to calculate an offset. when the counter reaches the offset count, a interrupt and/or wakeup request is generated. then the offset value is recalculated and again re-triggers a new request when the new value is reached. apival may only be updated when apien is disabled. when a compare is reached, the rtcs[apif] interrupt flag bit is set (after proper clock synchronization). if the rtcc[apiie] interrupt enable bit is set, then the api interrupt request is generated. if there is a match while in low power mode, then the api will first generate a wakeup request to force a wakeup into normal op eration, then the apif flag will be set. RM0017 can sampler doc id 14629 rev 8 256/904 14 can sampler 14.1 introduction the can sampler peripheral has been designed to store the first identifier of can message ?detected? on the can bus while no precise clock (crystal) is running at that time on the device, typically in low power modes (stop, halt or standby) or in run mode with crystal switched off. depending on both can baud rate and low power mode used, it is possible to catch either the first or the second can frame by sampling one can rx port among six and storing all samples in internal registers. after selection of the mode (first or second frame), the can sampler stores samples of the 48 bits or skips the first frame and stores samples of the 48 bits of second frame using the 16 mhz fast internal rc oscillator and the 5-bit clock prescaler. after completion, software has to process the sampled data in order to rebuild the 48 minimal bits. figure 113. extended can data frame 14.2 main features store 384 samples, equivalent to 48 can bit @ 8 samples/bit sample frequency from 500 khz up to 16 mhz, equivalent at 8 samples/bit to can baud rates of 62.5 kbps to 2 mbps user selectable can rx sa mple port [can0rx-can5rx] 16 mhz fast internal rc oscillator clock 5-bit clock prescaler configurable trigger mode (immediate, next frame) flexible samples proc essing by software very low power consumption base identifier (11-bit) sof spr extended identifier (18-bit) ide-bit rtr-bit r1 r0 data length code can sampler RM0017 257/904 doc id 14629 rev 8 14.3 register description the can sampler registers are listed in table 112 . 14.3.1 control register (cr) table 112. can sampler memory map base address: 0xffe7_0000 address offset register location 0x00 control register (cr) on page 14-257 0x04?0x30 sample registers 0?11 on page 14-258 offset: 0x00 access: read/write 012 3 456 7 8 9 10 11 12 13 14 15 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rx_complete busy active_ck 000 mode can_rx_sel brp can_smplr_en w reset0000000000000000 figure 114. control register (cr) table 113. cr field descriptions field description rx_complete 1: can frame is stored in the sample registers 0: can frame has not been stored in the sample registers busy this bit indicates the sampling status 1: sampling is ongoing 0: sampling is complete or has not started active_ck this bit indicates which is current clock for sample registers, that is, xmem_ck. 1: rc_clk is currently xmem_ck 0: ipg_clk_s is currently xmem_ck mode 0: skip the first frame and sample and store the second frame (sf_mode) 1: sample and store the first frame (ff_mode) RM0017 can sampler doc id 14629 rev 8 258/904 14.3.2 sample register n (n = 0..11) can_rx_sel this field determines which rx port is samp led. one rx port can be selected per sampling routine. 000: can0rx pb[1] is selected 001: can1rx pc[11] is selected 010: can2rx pe[9] is selected 011: can3rx pe[9] is selected 100: can4rx pc[11] is selected 101: can5rx pe[0] is selected 110: reserved 111: reserved brp baud rate prescaler this field is used to set the baud rate before going into standby mode. 00000: prescaler has 1 11111: prescaler has 32 can_smplr_en can sampler enable this bit enables the can sampler before going into standby or stop mode. 0: can sampler is disabled 1: can sampler is enabled table 113. cr field descriptions (continued) field description offsets: 0x04?0x30 (12 regi sters) access: read/write 012 3 456 7 8 9 10 11 12 13 14 15 r sr[31:16] w reset the reset values are unknown. they will be filled only after the first can sampling. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r sr[15:0] w reset the reset values are unknown. they will be filled only after the first can sampling. figure 115. sample register n can sampler RM0017 259/904 doc id 14629 rev 8 14.4 functional description as the can sampler is driven by the 16 mhz fast internal rc osc illator (or ?firc?) to properly sample the can identifier, two mo des are possible depending on both the can baud rate and low power mode used: immediate sampling on falling edge detection (first can frame): th is mode is used when the firc is available in lp mode (for example, stop or halt). sampling on next frame (second can frame) : this mode is used when the firc is switched off in lp mode (for example, standby). due to the start-up times of both the voltage regulator and the firc (~10 s), the can sampler would miss the first bits of a can identifier sent at 500 kbps. therefore, the first identifier is ignored and the sampling is performed on the first fa lling edge of after interframe space. the can sampler is in power domain 0 and ma intains register settings throughout low power modes. the can sampler performs sampling on a user-selected can rx port among six rx ports available, normally when the device is in standby or stop mode, storing the samples in internal registers. the user is required to configure the baud rate to achieve eight samples per can nominal bit. it does not perform any sort of filtering on input samples. thereafter the software must enable the sampler by setting the can_smplr_en bit in the cr register. it then becomes the master controller for accessing the internal registers implemented for storing samples. the can sampler, when enabled, waits for a low pulse on the selected rx line, taking it as a valid bit of the first can frame and generates the rc wakeup request which can be used to start the firc. depending upon the mode, it stores the first 8 samples of the 48 bits on selected rx line or skips the first frame and stores 8 bits for first 48 bits of second frame. in ff_mode, it samples the can rx line on the firc clock and stores the 8 samples of first 48 bits (384 samples). in sf_mode, it samples the rx and waits for 11 consecutive dominant bits ( 11 * 8 samples), taking it as the end of first frame. it then waits for first low pulse on the rx, taking it as a valid start of frame (sof) of the second frame. the sampler takes 384 samples (48 bytes * 8) using the firc clock (configuring 8 samples per nominal bit) of the second frame, including the sof bit. these samples are stored in consecutive addresses of the (12 x 32) internal registers. the rx_complete bit is set to ?1?, indicating that sampling is complete. software should now process the sampled data by first becoming master for accessing samples internal registers by resetting the can_smplr_en bit. the sampler will need to be enabled again to start waiting for a new sampling routine. 14.4.1 enabling/disabling the can sampler the can sampler is disabled on reset and the cpu is able to access the 12 registers used for storing samples. the can sampler must be enabled before going into standby or stop mode by setting the can_smplr_en bit in the control register (cr) by writing ?1? to this bit. in case of any activity on the selected rx line, the sampler enables the 16 mhz fast internal rc oscillator. when bit can_smplr_en is rese t to 0, the sampler sh ould receive at last three firc clock pulses to re set itself, after which the firc can be switched off. when the software attempts to access the sample registers? contents it must first reset the can_smplr_en bit by writing a ?0?. before acce ssing the register contents it must monitor active_ck bit for ?0?. when this bit is reset it can safely access the (12 x 32) sample RM0017 can sampler doc id 14629 rev 8 260/904 registers. while shifting from normal to sample mode and from sample to normal mode, the sample register signals must be static and inactive to ensure the data is not corrupt. 14.4.2 baud rate generation sampling is performed at a baud rate that is set by the software as a multiple of rc oscillator frequency of 62.5 ns (a ssuming rc is configured for high frequency mode, that is, 16 mhz). the user must set the baud rate prescaler (brp) such that eight samples per bit are achieved. the baud rate setting must be made by software before going into standby or stop mode. this is done by setting bits brp[4:0] in the control register. the reset value of brp is 00000 and can be set to max. 11111 which gives a prescale value of brp + 1, thus providing a brp range of 1 to 32. maximum bitrate supported for sampling is 2 mbps using brp as 1 minimum bitrate supported for sampling is 62.5 kbps using brp as 32 for example, suppose the system is transmitting at 125 kbps. in this case, nominal bit period: equation 2 t=1/(125*10 3 )s =8*10 -3 *10 -3 s = 8s to achieve 8 samples per bit sample period= 8/8 s = 1 s brp = 1 s/62.5 ns = 16. thus in this case brp = 01111 e200z0h core RM0017 261/904 doc id 14629 rev 8 15 e200z0h core 15.1 overview the e200 processor family is a set of cpu cores that implement cost-efficient versions of the power architecture ? . e200 processors are designed for deeply embedded control applications which require low cost solutions rather than maximum performance. the e200z0h processors integrate an integer execution unit, branch control unit, instruction fetch and load/store units, and a multi-ported register file capable of sustaining three read and two write operations per clock. most integer instructions execute in a single clock cycle. branch target prefetching is performed by the br anch unit to allow single-cycle branches in some cases. the e200z0h core is a single-issue, 32-bit power architecture technology vle-only design with 32-bit general purpose registers (gprs). all arithmetic instructions that execute in the core operate on data in the general purpose registers (gprs). instead of the base power architecture technology support, the e200z0h core only implements the vle (variable-length encoding) apu, providing improved code density. 15.2 microarchitecture summary the e200z0h processor utilizes a four sta ge pipeline for instruct ion execution. the instruction fetch (stage 1), instruction de code/register file r ead/effective address calculation (stage 2), execute/memory access (stage 3), and register writeback (stage 4) stages operate in an overlapped fashion, allowing single clock instruction execution for most instructions. the integer execution unit consists of a 32-bit arithmetic unit (au), a logic unit (lu), a 32- bit barrel shifter (shifter), a mask-insertion un it (miu), a condition register manipulation unit (cru), a count-leading-zeros unit (clz), an 8x32 hardware mu ltiplier array, result feed-forward hardware, and a hardware divider. arithmetic and logical operations are executed in a single cycle with the exception of the divide and multiply instructions. a count-leading-zeros unit operates in a single clock cycle. the instruction unit contains a pc incrementer and a dedicated branch address adder to minimize delays during change of flow operat ions. sequential prefetching is performed to ensure a supply of instructions into the execution pipeline. branch target prefetching from the btb is performed to accelerate certain taken branches in the e200z0h. prefetched instructions are placed into an instruction buffer with 4entries in e200z0h, each capable of holding a single 32-bit instruction or a pair of 16-bit instructions. conditional branches which are not taken execute in a single clock. branches with successful target prefetching have an effective execution time of one clock on e200z0h. all other taken branches have an execution time of two clocks. memory load and store operations are provided for byte, halfword, and word (32-bit) data with automatic zero or sign extension of byte and halfword load data as well as optional byte reversal of data. these inst ructions can be pi pelined to allow effective single cycle throughput. load and store multiple word instructions allow low overhead context save and restore operations. the load/store unit contains a dedicated effective address adder to allow RM0017 e200z0h core doc id 14629 rev 8 262/904 effective address generation to be optimized. also, a load-to-use dependency does not incur any pipeline bubbles for most cases. the condition register unit supports the condition register (cr) and condition register operations defined by the power architecture platform. the condition register consists of eight 4-bit fields that reflect the results of certain operations, such as move, integer and floating-point compare, arithmetic, and logical instructions, and provide a mechanism for testing and branching. vectored and autovectored interrupts are supported by the cpu. vectored interrupt support is provided to allow multiple interrupt source s to have unique interrupt handlers invoked with no software overhead. e200z0h core RM0017 263/904 doc id 14629 rev 8 15.3 block diagram figure 116. e200z0h block diagram cpu control logic load/ data address store unit instruction unit branch unit pc unit instruction buffer gpr cr spr multiply unit data bus interface unit control 32 32 n once/nexus control logic interface control data (mtspr/mfspr) integer execution unit external spr ctr xer lr data address instruction bus interface unit control 32 32 n RM0017 e200z0h core doc id 14629 rev 8 264/904 15.4 features the following is a list of some of the key features of the e200z0h core: 32-bit power architecture vle-only programmer?s model single issue, 32-bit cpu implements the vle apu for reduced code footprint in-order execution and retirement precise exception handling branch processing unit ? dedicated branch address calculation adder ? branch acceleration using branch target buffer supports independent instruction and data accesses to different memory subsystems, such as sram and flash memory via independent instruction and data bus interface units (bius) (e200z0h only). load/store unit ? 1 cycle load latency ? fully pipelined ? big-endian support only ? misaligned access support ? zero load-to-use pipeline bubbles for aligned transfers power management ? low power design ? power saving modes: nap, sleep, and wait ? dynamic power management of execution units testability ? synthesizeable, full muxd scan design ? abist/mbist for optional memory arrays 15.4.1 instruction unit features the features of the e200 instruction unit are: 32-bit instruction fetch path supports fetching of one 32-bit instruction per clock, or up to two 16-bit vle instructions per clock instruction buffer with 4 entries in e200z0h, each holding a single 32-bit instruction, or a pair of 16-bit instructions dedicated pc incrementer supporting instruction prefetches branch unit with dedicated branch address adder supporting singl e cycle of execution of certain branches, two cycles for all others e200z0h core RM0017 265/904 doc id 14629 rev 8 15.4.2 integer unit features the e200 integer unit supports single cycle ex ecution of most integer instructions: 32-bit au for arithmetic and comparison operations 32-bit lu for logical operations 32-bit priority encoder for count leading zero?s function 32-bit single cycle barrel shifter for shifts and rotates 32-bit mask unit for data masking and insertion divider logic for signed and unsigned divide in 5 to 34 clocks with minimized execution timing 8x32 hardware multiplier array supports 1 to 4 cycle 32x32->32 multiply (early out) 15.4.3 load/store unit features the e200 load/store unit supports load, store, and the load multiple / store multiple instructions: 32-bit effective address adder for data memory address calculations pipelined operation supports throughput of one load or store operation per cycle 32-bit interface to memory (dedicated memory interface on e200z0h) 15.4.4 e200z0h system bus features the features of the e200z0h system bus interface are as follows: independent instruction and data buses amba (l) ahb (m) lite rev 2.0 specification with support for arm v6 amba extensions ? exclusive access monitor ? byte lane strobes ? cache allocate support 32-bit address bus plus attributes and control on each bus 32-bit read data bus fo r instruction interface separate uni-directional 32-bit read data bus and 32-bit write data bus for data interface overlapped, in-order accesses 15.4.5 nexus 2+ features the nexus 2+ module is comp liant with class 2 of the ieee- isto 5001-2003 standard, with additional class 3 and class 4 features available. the following features are implemented: program trace via branch trace messaging (b tm)?branch trace messaging displays program flow discontinuities (direct and indirect branches, exceptions, etc.), allowing the development tool to interpolate what transpires between the discontinuities. thus, static code may be traced. ownership trace via owners hip trace messaging (otm)?otm facilitates ownership trace by providing visibility of which proce ss id or operating system task is activated. l. advanced microcontro ller bus architecture m. advanced high performance bus RM0017 e200z0h core doc id 14629 rev 8 266/904 an ownership trace message is transmitte d when a new process/task is activated, allowing the development tool to trace ownership flow. run-time access to the processor memory map via the jtag port. this allows for enhanced download/up load capabilities. watchpoint messaging via the auxiliary interface watchpoint trigger enable of program trace messaging auxiliary interface for hi gher data input/output ? configurable (min/max) message data out pins ( nex_mdo[n:0] ) ? one (1) or two (2) message start/end out pins ( nex_mseo_b[1:0] ) ? one (1) read/write ready pin ( nex_rdy_b ) pin ? one (1) watchpoint event pin ( nex_evto_b ) ? one (1) event in pin ( nex_evti_b ) ? one (1) mcko (message clock out) pin registers for program trace, ownership trace and watchpoint trigger control all features controllable and configurable via the jtag port 15.5 core registers and programmer?s model this section describes the registers implemented in the e200z0h cores. it includes an overview of registers defined by the power architecture platform, highlighting differences in how these registers are implemented in the e200 core, and provides a detailed description of e200-specific registers. full descriptions of the architecture-defined register set are provided in the power architecture specification. the power architecture defines register-to-register operations for all computational instructions. source data for these instructions are accessed from the on-chip registers or are provided as immediate values embedded in the opcode. the three-register instruction format allows specification of a target register distinct from the two source registers, thus preserving the original data for use by other instructions. data is transferred between memory and registers with explicit load and store instructions only. figure 117 , and figure 116 show the e200 register set including the registers which are accessible while in supervisor mode, and the re gisters which are accessible in user mode. the number to the right of the special-purpose registers (sprs) is the decimal number used in the instruction syntax to access the register (for example, the integer exception register (xer) is spr 1). note: e200z0h is a 32-bit implementation of the power architecture specification. in this document, register bits are sometimes numbered from bit 0 (most significant bit) to 31 (least significant bit), rather than the book e numbering scheme of 32:63, thus register bit numbers for some registers in book e are 32 higher. where appropriate, the book e defined bit numbers are shown in parentheses. e200z0h core RM0017 267/904 doc id 14629 rev 8 figure 117. e200z0 superviso r mode program model sprs spr general exception handling/control registers save and restore machine state msr pvr processor control registers supervisor mode program model sprs sprg0 sprg1 spr 272 spr 273 srr0 srr1 csrr0 csrr1 dsrr0 1 dsrr1 1 spr 26 spr 27 spr 58 spr 59 spr 574 spr 575 processor id pir spr 286 interrupt vector prefix ivpr spr 63 debug registers 2 debug control dbcr0 dbcr1 dbcr2 dbcr3 1 spr 308 spr 309 spr 310 spr 561 instruction address iac1 iac2 iac3 iac4 spr 312 spr 313 spr 314 spr 315 data address compare dac1 dac2 spr 316 spr 317 1 - these e200-specific registers may not be supported by other power architecture processors. 2 - optional registers defined by the power architecture technology 3 - read-only registers processor version hardware implementation hid0 spr 1008 cache registers spr 9 general-purpose registers count register ctr spr 8 link register lr condition register cr gpr0 gpr1 spr 515 cache configuration (read-only) l1cfg0 spr 1 xer xer general registers spr 287 debug status dbsr spr 304 system version 1 svr spr 1023 esr spr 62 exception syndrome data exception address dear spr 61 machine check syndrome register mcsr spr 572 btb control 1 spr 1013 bucsr btb register memory management registers process id pid0 spr 48 configuration (read only) spr 1015 mmucfg dvc1 dvc2 spr 318 spr 319 RM0017 interrupt co ntroller (intc) doc id 14629 rev 8 268/904 16 interrupt controller (intc) 16.1 introduction the intc provides priority-based preemptive scheduling of interrupt service requests (isrs). this scheduling scheme is suitable for statically scheduled hard real-time systems. the intc supports 142 interrupt requests. it is targeted to work with a power architecture technology processor and automotive powertrain applications where the isrs nest to multiple levels, but it also can be used with other processors and applications. for high priority interrupt requests in these target applications, the time from the assertion of the peripheral?s interrupt request from the peripheral to when the processor is performing useful work to service the interrupt request needs to be minimized. the intc supports this goal by providing a unique vector for each interrupt request source. it also provides 16 priorities so that lower priority isrs do not del ay the execution of higher priority isrs. since each individual application will have different priorities for eac h source of interrupt request, the priority of each interrupt request is configurable. when multiple tasks share a resource, coherent accesses to that resource need to be supported. the intc supports the priority ceiling protocol for coherent accesses. by providing a modifiable priority mask, the priority can be raised temporarily so that all tasks which share the resource cannot preempt each other. multiple processors can assert interrupt requests to each other through software configurable interrupt requests. these same software configurable interrupt requests also can be used to break the work involved in servicing an interrupt request into a high priority portion and a low priority portion. the high priority portion is initiated by a peripheral interrupt request, but then the isr can assert a software configurable interrupt request to finish the servicing in a lower priority isr. therefore these software configurable interrupt requests can be used instead of the peripheral isr scheduling a task through the rtos. 16.2 features supports 134 peripheral and 8 software-configurable interrupt request sources unique 9-bit vector per interrupt source each interrupt source can be programmed to one of 16 priorities preemption ? preemptive prioritized interrupt requests to processor ? isr at a higher priority preempts isrs or tasks at lower priorities ? automatic pushing or popping of preempted priority to or from a lifo ? ability to modify the isr or task priori ty; modifying the priority can be used to implement the priority ceiling protoc ol for accessing shared resources. low latency ? 3 clocks from receipt of interrupt request from peripheral to interrupt request to processor interrupt controller (intc) RM0017 269/904 doc id 14629 rev 8 16.3 block diagram figure 118 provides a block diagram of the intc. table 114. interrupt sources available interrupt sources (142) number available software 8 ecsm 1 software watchdog (swt) 1 stm 4 flash/sram ecc (sec-ded) 2 real time counter (rtc/api) 2 system integration unit lite (siul) 2 wkpu 3 mc_me 4 mc_rgm 1 fxosc 1 pit 6 adc_0 3 flexcan_0 8 flexcan_1 8 flexcan_2 8 flexcan_3 8 flexcan_4 8 flexcan_5 8 linflex_0 3 linflex_1 3 linflex_2 3 linflex_3 3 dspi_0 5 dspi_1 5 dspi_2 5 i2c_0 1 enhanced modular i/o subsystem 0 (emios_0) 14 emios_1 14 RM0017 interrupt co ntroller (intc) doc id 14629 rev 8 270/904 figure 118. intc block diagram 16.4 modes of operation 16.4.1 normal mode in normal mode, the intc has two handshaking modes with the processor: software vector mode and hardware vector mode. software vector mode in software vector mode, software, that is the interrupt exception handler, must read a register in the intc to obtain the vector associated with the interrupt request to the processor. the intc will use software ve ctor mode for a given processor when its associated hven bit in intc_mcr is negated. the hardware vector enable signal to processor 0 or processor 1 is driven as negated when its associated hven bit is negated. the vector is read from inc_iackr. read ing the intc_iackr negates the interrupt request to the associated processor. even if a higher priority interrupt request arrived while waiting for this interrupt acknowledge, the in terrupt request to the processor will negate for at least one clock. the reading also pushes the pri value in intc_cpr onto the associated lifo and updates pri in the associated intc_cpr with the new priority. furthermore, the interrupt vector to the processor is driven as all 0s. the interrupt acknowledge signal from the associated processor is ignored. hardware vector enable software set/clear interrupt registers flag bits priority select registers peripheral interrupt requests module configuration register highest priority 4 priority comparator slave interface for reads & writes 1 push/update/acknowledge 1 1 1 update interrupt vector 1 interrupt request to processor memory mapped registers non-memory mapped logic end of interrupt register request selector priority arbitrator highest priority interrupt requests n 1 n 1 vector encoder interrupt vector 9 processor 0 interrupt acknowledge register interrupt vector 9 n 1 8 n 1 x 4-bits new priority 4 current priority 4 processor 0 current priority register processor 0 priority lifo pop 1 lowest vector interrupt request 1 vector table entry size pushed priority 4 popped priority 4 interrupt acknowledge peripheral bus interrupt controller (intc) RM0017 271/904 doc id 14629 rev 8 hardware vector mode in hardware vector mode, the hardware is the interrupt vector signal from the intc in conjunction with a processor with the capability use that vector . in hardware vector mode, this hardware causes the first instruction to be executed in handling the interrupt request to the processor to be specific to that vector. therefore the interrupt exception handler is specific to a peripheral or software configurable interrupt request rather than being common to all of them. the intc uses hardware vector mode for a given processor when the associated hven bit in the intc_mcr is asserted. the hardware vector enable signal to the associated processor is driven as asserted. when the interrupt request to the associated processor asserts, the interrupt vector signal is updated. the value of that interrupt vector is the unique vector associated with the preempting peripheral or software configurable interrupt request. the vector value matches the value of the intvec field in the intc_iackr field in the intc_iackr, depending on which processor was assigned to handle a given interrupt source. the processor negates the interrupt request to the processor driven by the intc by asserting the interrupt acknowledge signal for one clock. even if a higher priority interrupt request arrived while waiting for the interrupt acknowledge, the interrupt request to the processor will negate for at least one clock. the assertion of the interrupt acknowledge signal for a given processor pushes the associated pri value in the associated intc_cpr register onto the associated lifo and updates the associated pri in the associated intc_cpr register with the new priority. this pushing of the pri value onto the associated lifo and updating pri in the associated intc_cpr does not occur when the associated interrupt acknowledge signal asserts and intc_sscir0_3?intc_sscir4_7 is written at a time such that the pri value in the associated intc_cpr register would need to be pushed and the previously last pushed pri value would need to be popped simultaneously. in this case, pri in the associated intc_cpr is updated with the new priority, and the associated lifo is neither pushed or popped. debug mode the intc operation in debug mode is identical to its operation in normal mode. stop mode the intc supports stop mode. the intc can have its clock input disabled at any time by the clock driver on the device. while its clocks are disabled, the intc registers are not accessible. the intc requires clocking in order for a peripheral interrupt request to generate an interrupt request to the processor. since the intc is not clocked in stop mode, peripheral interrupt requests can not be used as a wakeup source, unless the device supports that interrupt request as a wakeup source. 16.5 memory map and register description 16.5.1 module memory map table 115 shows the intc memory map. RM0017 interrupt co ntroller (intc) doc id 14629 rev 8 272/904 16.5.2 register description with exception of the intc_ssci n and intc_psr n , all registers are 32 bits in width. any combination of accessing the four bytes of a register with a single access is supported, provided that the access does not cross a register boundary. these supported accesses include types and sizes of eight bits, aligned 16 bits, misaligned 16 bits to the middle two bytes, and aligned 32 bits. although intc_ssci n and intc_psr n are 8 bits wide, they can be accessed with a single 16-bit or 32-bit access, provided that the access does not cross a 32-bit boundary. in software vector mode, the side effects of a read of intc_iackr are the same regardless of the size of the read. in either software or hardware vector mode, the size of a write to either intc_sscir0_3?intc_sscir4_7 or intc _eoir does not affect the operation of the write. intc module configuration register (intc_mcr) the module configuration register is used to configure options of the intc. table 115. intc memory map base address: 0xfff4_8000 address offset register location 0x0000 intc module configur ation register (intc_mcr) on page 16-272 0x0004 reserved 0x0008 intc current priority register for processor (intc_cpr) on page 16-273 0x000c reserved 0x0010 intc interrupt acknowledge register (intc_iackr) on page 16-275 0x0014 reserved 0x0018 intc end-of-interrupt register (intc_eoir) on page 16-276 0x001c reserved 0x0020?0x0027 intc software set/clear interrupt registers (intc_sscir0_3? intc_sscir4_7) on page 16-276 0x0028?0x003c reserved 0x0040?0x00d0 intc priority select registers (intc_psr0_3? intc_psr208_210) (1) 1. the pri fields are ?reserved? for peripheral interrupt requests whose vectors are labeled ?reserved? in figure 120 . on page 16-278 interrupt controller (intc) RM0017 273/904 doc id 14629 rev 8 intc current priority register for processor (intc_cpr) figure 119. intc module conf iguration register (intc_mcr) offset: 0x0000 access: user read/write 0123456789101112131415 r0000000000000000 w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000 vtes 0000 hven w reset 0000000000000000 table 116. intc_mcr field descriptions field description vtes vector table entry size. controls the number of ?0?s to the right of intvec in section intc interrupt acknowledge register (intc_iackr) . if the contents of intc_iackr are used as an address of an entry in a vectortable as in software vector mode, then the number of ri ghtmost ?0?s will determine the size of each vector table entry. vtes impacts software vector mode operation but also affects intc_iackr[intvec] position in both hardware vector mode and software vector mode. 0 4 bytes 1 8 bytes hven hardware vector enable. controls whether the intc is in hardware vector mode or software vector mode. refer to section 16.4 modes of operation , for the details of the handshaking with the processor in each mode. 0 software vector mode 1 hardware vector mode figure 120. intc current priority register (intc_cpr) offset: 0x0008 access: user read/write 0 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425262728293031 r0000000000000000000000000000 pri w reset00000000000000000000000000001111 table 117. intc_cpr field descriptions field description pri priority pri is the priority of the currently executing isr according to the field values defined in ta b l e 1 1 8 . RM0017 interrupt co ntroller (intc) doc id 14629 rev 8 274/904 the intc_cpr masks any peripheral or software configurable interrupt request set at the same or lower priority as the current value of the intc_cpr[pri] field from generating an interrupt request to the processor. when the intc interrupt acknowledge register (intc_iackr) is read in software vector mode or the interrupt acknowledge signal from the processor is asserted in hardware vector mode, the value of pri is pushed onto the lifo, and pri is updated with the priority of the preempting interrupt request. when the intc end-of-interrupt register (intc_eoir) is written, the lifo is popped into the intc_cpr?s pri field. the masking priority can be raised or lowered by writing to the pri field, supporting the pcp. refer to section 16.7.5 priority ceiling protocol . note: a store to modify the pri field which clos ely precedes or follows an access to a shared resource can result in a non-coherent access to that resource. refer to section ensuring coherency for example code to ensure coherency. table 118. pri values pri meaning 1111 priority 15?highest priority 1110 priority 14 1101 priority 13 1100 priority 12 1011 priority 11 1010 priority 10 1001 priority 9 1000 priority 8 0111 priority 7 0110 priority 6 0101 priority 5 0100 priority 4 0011 priority 3 0010 priority 2 0001 priority 1 0000 priority 0?lowest priority interrupt controller (intc) RM0017 275/904 doc id 14629 rev 8 intc interrupt acknowledge register (intc_iackr) the interrupt acknowledge register provides a value which can be used to load the address of an isr from a vector table. the vector table can be composed of addresses of the isrs specific to their respective interrupt vectors. in software vector mode, the intc_iackr has side effects from reads. therefore, it must not be speculatively read while in this mode. the side effects are the same regardless of the figure 121. intc interrupt acknowledge register (intc_iackr) when intc_mcr[vtes] = 0 offset: 0x0010 access: user read/write 0123456789101112131415 r vtba[20:5] w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r vtba[4:0] intvec 0 0 w reset 0000000000000000 figure 122. intc interrupt acknowledge register (intc_iackr) when intc_mcr[vtes] = 1 offset: 0x0010 access: user read/write 0123456789101112131415 r vtba[19:4] w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r vtba[3:0] intvec 0 0 0 w reset 0000000000000000 table 119. intc_iackr field descriptions field description vtba vector table base address can be the base address of a vect or table of addresses of isrs. intvec interrupt vector it is the vector of the peripheral or software conf igurable interrupt request that caused the interrupt request to the processor. when the interrupt request to the processor asserts, the intvec is updated, whether the intc is in so ftware or hardware vector mode. RM0017 interrupt co ntroller (intc) doc id 14629 rev 8 276/904 size of the read. reading the intc_iackr does not have side effects in hardware vector mode. intc end-of-interrupt register (intc_eoir) writing to the end-of-interrupt register signals the end of the servicing of the interrupt request. when the intc_eoir is written, the priority last pushed on the lifo is popped into intc_cpr. an exception to this behavior is described in section hardware vector mode . the values and size of data written to the intc_eoir are ignored. the values and sizes written to this register neither update the intc_eoir contents or affect whether the lifo pops. for possible future compatibility, writ e four bytes of all 0s to the intc_eoir. reading the intc_eoir has no effect on the lifo. intc software set/clear interrupt registers (intc_sscir0_3? intc_sscir4_7) figure 123. intc end-of-interrupt register (intc_eoir) offset: 0x0018 access: write only 012345678910111213141516171819202122232425262728293031 r000000000000000000 00000000 000000 w see text reset 00000000000000000000000000000000 figure 124. intc software set/clear in terrupt register 0?3 (intc_sscir[0:3]) offset: 0x0020 access: user read/write 0123456789101112131415 r 0 0 0 0 0 0 0 clr0 0 0 0 0 0 0 0 clr1 w set0 set1 reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 clr2 0 0 0 0 0 0 0 clr3 w set2 set3 reset 0000000000000000 interrupt controller (intc) RM0017 277/904 doc id 14629 rev 8 the software set/clear interrupt registers support the setting or clearing of software configurable interrupt request. these registers contain eight independent sets of bits to set and clear a corresponding flag bit by software. excepting being set by software, this flag bit behaves the same as a flag bit set within a peripheral. this flag bit generates an interrupt request within the intc like a peripheral interrupt request. writing a 1 to set x will leave set x unchanged at 0 but sets clr x . writing a 0 to set x has no effect. clr x is the flag bit. writing a 1 to clr x clears it. writing a 0 to clr x has no effect. if a 1 is written simultaneously to a pair of set x and clr x bits, clr x will be asserted, regardless of whether clr x was asserted before the write. figure 125. intc software set/clear in terrupt register 4?7 (intc_sscir[4:7]) offset: 0x0024 access: user read/write 0123456789101112131415 r 0 0 0 0 0 0 0 clr4 0 0 0 0 0 0 0 clr5 w set4 set5 reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 clr6 0 0 0 0 0 0 0 clr7 w set6 set7 reset 0000000000000000 table 120. intc_sscir[0 :7] field descriptions field description setx set flag bits writing a 1 sets the corresponding clr x bit. writing a 0 has no effect. each set x always will be read as a 0. clrx clear flag bits clr x is the flag bit. writing a 1 to clr x clears it provided that a 1 is not written simultaneously to its corresponding set x bit. writing a 0 to clr x has no effect. 0 interrupt request not pending within intc 1 interrupt request pending within intc RM0017 interrupt co ntroller (intc) doc id 14629 rev 8 278/904 intc priority select registers (intc_psr0_3?intc_psr208_210) figure 126. intc priority select register 0?3 (intc_psr[0:3]) offset: 0x0040 access: user read/write 0123456789101112131415 r 0000 pri0 0000 pri1 w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 pri2 0000 pri3 w reset 0000000000000000 figure 127. intc priority select register 208-210 (intc_psr[208:210]) offset: 0x0110 access: user read/write 0123456789101112131415 r0 0 0 0 pri208 0000 pri209 w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 0 0 pri210 00000000 w reset 0000000000000000 table 121. intc_psr0_3?intc_ psr208_210 field descriptions field description pri priority select pri x selects the priority for interrupt requests. see section 16.6 functional description . table 122. intc priority select register address offsets intc_psr x _ x offset address intc_psr x _ x offset address intc_psr0_3 0x0040 intc_psr108_111 0x00ac intc_psr4_7 0x0044 intc_psr112_115 0x00b0 intc_psr8_11 0x0048 intc_psr116_119 0x00b4 intc_psr12_15 0x004c intc_psr120_123 0x00b8 intc_psr16_19 0x0050 intc_psr124_127 0x00bc interrupt controller (intc) RM0017 279/904 doc id 14629 rev 8 16.6 functional description the functional description involves the areas of interrupt request sources, priority management, and handshaking with the processor. note: the intc has no spurious vector support. therefore, if an asserted peripheral or software settable interrupt request, whose prin valu e in intc_psr0?intc_psr210 is higher than the pri value in intc_cpr, negates before the interrupt request to the processor for that peripheral or software settable interrupt request is acknowledged, the interrupt request to the processor still can assert or will remain asserted for that pe ripheral or software settable interrupt request. in this case, the interrupt vector will correspond to that peripheral or software settable interrupt request. also, th e pri value in the intc_cpr will be updated with the corresponding prin value in intc_psrn. furthermore, clearing the peripheral interrupt request?s enable bit in the peripheral or, alternatively, setting its mask bit has the same consequences as clearing its flag bit. setting its enable bit or clearing its mask bit while its flag bit is asserted has the same effect on the intc as an interrupt event setting the flag bit. intc_psr20_23 0x0054 intc_psr128_131 0x00c0 intc_psr24_27 0x0058 intc_psr132_135 0x00c4 intc_psr28_31 0x005c intc_psr136_139 0x00c8 intc_psr32_35 0x0060 intc_psr140_143 0x00cc intc_psr36_39 0x0064 intc_psr144_147 0x00d0 intc_psr40_43 0x0068 intc_psr148_151 0x00d4 intc_psr44_47 0x006c intc_psr152_155 0x00d8 intc_psr48_51 0x0070 intc_psr156_159 0x00dc intc_psr52_55 0x0074 intc_psr160_163 0x00e0 intc_psr56_59 0x0078 intc_psr164_167 0x00e4 intc_psr60_63 0x007c intc_psr168_171 0x00e8 intc_psr64_67 0x0080 intc_psr172_175 0x00ec intc_psr68_71 0x0084 intc_psr176_179 0x00f0 intc_psr72_75 0x0088 intc_psr180_183 0x00f4 intc_psr76_79 0x008c intc_psr184_187 0x00f8 intc_psr80_83 0x0090 intc_psr188_191 0x00fc intc_psr84_87 0x0094 intc_psr192_195 0x0100 intc_psr88_91 0x0098 intc_psr196_199 0x0104 intc_psr92_95 0x009c intc_psr200_203 0x0108 intc_psr96_99 0x00a0 intc_psr204_207 0x010c intc_psr100_103 0x00a4 intc_psr208_210 0x0110 intc_psr104_107 0x00a8 ? ? table 122. intc priority select register address offsets (continued) intc_psr x _ x offset address intc_psr x _ x offset address RM0017 interrupt co ntroller (intc) doc id 14629 rev 8 280/904 table 123. interrupt vector table irq # offset size (bytes) interrupt module section a (core section) ? 0x0000 16 critical input (intc software vector mode) / nmi core ? 0x0010 16 machine check / nmi core ? 0x0020 16 data storage core ? 0x0030 16 instruction storage core ? 0x0040 16 external input (intc software vector mode) core ? 0x0050 16 alignment core ? 0x0060 16 program core ? 0x0070 16 reserved core ? 0x0080 16 system call core ? 0x0090 96 unused core ? 0x00f0 16 debug core ? 0x0100 1792 unused core section b (on-platform peripherals) 0 0x0800 4 software configurable flag 0 software 1 0x0804 4 software configurable flag 1 software 2 0x0808 4 software configurable flag 2 software 3 0x080c 4 software configurable flag 3 software 4 0x0810 4 software configurable flag 4 software 5 0x0814 4 software configurable flag 5 software 6 0x0818 4 software configurable flag 6 software 7 0x081c 4 software configurable flag 7 software 8 0x0820 4 reserved 9 0x0824 4 platform flash bank 0 abort | platform flash bank 0 stall | platform flash bank 1 abort | platform flash bank 1 stall | ecsm 10 0x0828 4 reserved 11 0x082c 4 reserved 12 0x0830 4 reserved 13 0x0834 4 reserved 14 0x0838 4 reserved 15 0x083c 4 reserved interrupt controller (intc) RM0017 281/904 doc id 14629 rev 8 16 0x0840 4 reserved 17 0x0844 4 reserved 18 0x0848 4 reserved 19 0x084c 4 reserved 20 0x0850 4 reserved 21 0x0854 4 reserved 22 0x0858 4 reserved 23 0x085c 4 reserved 24 0x0860 4 reserved 25 0x0864 4 reserved 26 0x0868 4 reserved 27 0x086c 4 reserved 28 0x0870 4 timeout swt 29 0x0874 4 reserved 30 0x0878 4 match on channel 0 stm 31 0x087c 4 match on channel 1 stm 32 0x0880 4 match on channel 2 stm 33 0x0884 4 match on channel 3 stm 34 0x0888 4 reserved 35 0x088c 4 ecc_dbd_platformflash | ecc_dbd_platformram platform ecc double bit detection 36 0x0890 4 ecc_sbc_platformflash | ecc_sbc_platformram platform ecc single bit correction 37 0x0894 4 reserved section c 38 0x0898 4 rtc rtc/api 39 0x089c 4 api rtc/api 40 0x08a0 4 reserved 41 0x08a4 4 siu external irq_0 siul 42 0x08a8 4 siu external irq_1 siul 43 0x08ac 4 reserved 44 0x08b0 4 reserved 45 0x08b4 4 reserved 46 0x08b8 4 wakeup_irq_0 wkpu 47 0x08bc 4 wakeup_irq_1 wkpu table 123. interrupt vector table (continued) irq # offset size (bytes) interrupt module RM0017 interrupt co ntroller (intc) doc id 14629 rev 8 282/904 48 0x08c0 4 wakeup_irq_2 wkpu 49 0x08c4 4 reserved 50 0x08c8 4 reserved 51 0x08cc 4 safe mode interrupt mc_me 52 0x08d0 4 mode transition interrupt mc_me 53 0x08d4 4 invalid mode interrupt mc_me 54 0x08d8 4 invalid mode config mc_me 55 0x08dc 4 reserved 56 0x08e0 4 functional and destructive reset alternate event interrupt (ipi_int) mc_rgm 57 0x08e4 4 fxosc counter expired (ipi_int_osc) fxosc 58 0x08e8 4 reserved 59 0x08ec 4 pitimer channel 0 pit 60 0x08f0 4 pitimer channel 1 pit 61 0x08f4 4 pitimer channel 2 pit 62 0x08f8 4 adc_eoc adc_0 63 0x08fc 4 adc_er adc_0 64 0x0900 4 adc_wd adc_0 65 0x0904 4 flexcan_esr[err_int] flexcan_0 66 0x0908 4 flexcan_esr_boff | flexcan_transmit_warning | flexcan_receive_warning flexcan_0 67 0x090c 4 reserved 68 0x0910 4 flexcan_buf_00_03 flexcan_0 69 0x0914 4 flexcan_buf_04_07 flexcan_0 70 0x0918 4 flexcan_buf_08_11 flexcan_0 71 0x091c 4 flexcan_buf_12_15 flexcan_0 72 0x0920 4 flexcan_buf_16_31 flexcan_0 73 0x0924 4 flexcan_buf_32_63 flexcan_0 74 0x0928 4 dspi_sr[tfuf] dspi_sr[rfof] dspi_0 75 0x092c 4 dspi_sr[eoqf] dspi_0 76 0x0930 4 dspi_sr[tfff] dspi_0 77 0x0934 4 dspi_sr[tcf] dspi_0 78 0x0938 4 dspi_sr[rfdf] dspi_0 table 123. interrupt vector table (continued) irq # offset size (bytes) interrupt module interrupt controller (intc) RM0017 283/904 doc id 14629 rev 8 79 0x093c 4 linflex_rxi linflex_0 80 0x0940 4 linflex_txi linflex_0 81 0x0944 4 linflex_err linflex_0 82 0x0948 4 reserved 83 0x094c 4 reserved 84 0x0950 4 reserved 85 0x0954 4 flexcan_esr[err_int] flexcan_1 86 0x0958 4 flexcan_esr_boff | flexcan_transmit_warning | flexcan_receive_warning flexcan_1 87 0x095c 4 reserved 88 0x0960 4 flexcan_buf_00_03 flexcan_1 89 0x0964 4 flexcan_buf_04_07 flexcan_1 90 0x0968 4 flexcan_buf_08_11 flexcan_1 91 0x096c 4 flexcan_buf_12_15 flexcan_1 92 0x0970 4 flexcan_buf_16_31 flexcan_1 93 0x0974 4 flexcan_buf_32_63 flexcan_1 94 0x0978 4 dspi_sr[tfuf] dspi_sr[rfof] dspi_1 95 0x097c 4 dspi_sr[eoqf] dspi_1 96 0x0980 4 dspi_sr[tfff] dspi_1 97 0x0984 4 dspi_sr[tcf] dspi_1 98 0x0988 4 dspi_sr[rfdf] dspi_1 99 0x098c 4 linflex_rxi linflex_1 100 0x0990 4 linflex_txi linflex_1 101 0x0994 4 linflex_err linflex_1 102 0x0998 4 reserved 103 0x099c 4 reserved 104 0x09a0 4 reserved 105 0x09a4 4 flexcan_[err_int] flexcan_2 106 0x09a8 4 flexcan_esr_boff | flexcan_transmit_warning | flexcan_receive_warning flexcan_2 107 0x09ac 4 reserved 108 0x09b0 4 flexcan_buf_00_03 flexcan_2 table 123. interrupt vector table (continued) irq # offset size (bytes) interrupt module RM0017 interrupt co ntroller (intc) doc id 14629 rev 8 284/904 109 0x09b4 4 flexcan_buf_04_07 flexcan_2 110 0x09b8 4 flexcan_buf_08_11 flexcan_2 111 0x09bc 4 flexcan_buf_12_15 flexcan_2 112 0x09c0 4 flexcan_buf_16_31 flexcan_2 113 0x09c4 4 flexcan_buf_32_63 flexcan_2 114 0x09c8 4 dspi_sr[tfuf] dspi_sr[rfof] dspi_2 115 0x09cc 4 dspi_sr[eoqf] dspi_2 116 0x09d0 4 dspi_sr[tfff] dspi_2 117 0x09d4 4 dspi_sr[tcf] dspi_2 118 0x09d8 4 dspi_sr[rfdf] dspi_2 119 0x09dc 4 linflex_rxi linflex_2 120 0x09e0 4 linflex_txi linflex_2 121 0x09e4 4 linflex_err linflex_2 122 0x09e8 4 linflex_rxi linflex_3 123 0x09ec 4 linflex_txi linflex_3 124 0x09f0 4 linflex_err linflex_3 125 0x09f4 4 i2c_sr[ibal] i2c_sr[tcf] i2c_sr[iaas] i2c_0 126 0x09f8 4 reserved 127 0x09fc 4 pitimer channel 3 pit 128 0x0a00 4 pitimer channel 4 pit 129 0x0a04 4 pitimer channel 5 pit 130 0x0a08 4 reserved 131 0x0a0c 4 reserved 132 0x0a10 4 reserved 133 0x0a14 4 reserved 134 0x0a18 4 reserved 135 0x0a1c 4 reserved 136 0x0a20 4 reserved 137 0x0a24 4 reserved 138 0x0a28 4 reserved 139 0x0a2c 4 reserved 140 0x0a30 4 reserved table 123. interrupt vector table (continued) irq # offset size (bytes) interrupt module interrupt controller (intc) RM0017 285/904 doc id 14629 rev 8 141 0x0a34 4 emios_gf r[f0,f1] emios_0 142 0x0a38 4 emios_gf r[f2,f3] emios_0 143 0x0a3c 4 emios_gf r[f4,f5] emios_0 144 0x0a40 4 emios_gf r[f6,f7] emios_0 145 0x0a44 4 emios_gf r[f8,f9] emios_0 146 0x0a48 4 emios_gfr[f10,f11] emios_0 147 0x0a4c 4 emios_gfr[f12,f13] emios_0 148 0x0a50 4 emios_gfr[f14,f15] emios_0 149 0x0a54 4 emios_gfr[f16,f17] emios_0 150 0x0a58 4 emios_gfr[f18,f19] emios_0 151 0x0a5c 4 emios_gfr[f20,f21] emios_0 152 0x0a60 4 emios_gfr[f22,f23] emios_0 153 0x0a64 4 emios_gfr[f24,f25] emios_0 154 0x0a68 4 emios_gfr[f26,f27] emios_0 155 0x0a6c 4 reserved 156 0x0a70 4 reserved section d (device specific vectors) 157 0x0a74 4 emios_gf r[f0,f1] emios_1 158 0x0a78 4 emios_gf r[f2,f3] emios_1 159 0x0a7c 4 emios_gf r[f4,f5] emios_1 160 0x0a80 4 emios_gf r[f6,f7] emios_1 161 0x0a84 4 emios_gf r[f8,f9] emios_1 162 0x0a88 4 emios_gfr[f10,f11] emios_1 163 0x0a8c 4 emios_gfr[f12,f13] emios_1 164 0x0a90 4 emios_gfr[f14,f15] emios_1 165 0x0a94 4 emios_gfr[f16,f17] emios_1 166 0x0a98 4 emios_gfr[f18,f19] emios_1 167 0x0a9c 4 emios_gfr[f20,f21] emios_1 168 0x0aa0 4 emios_gfr[f22,f23] emios_1 169 0x0aa4 4 emios_gfr[f24,f25] emios_1 170 0x0aa8 4 emios_gfr[f26,f27] emios_1 171 0x0aac 4 reserved 172 0x0ab0 4 reserved 173 0x0ab4 4 flexcan_esr flexcan_3 table 123. interrupt vector table (continued) irq # offset size (bytes) interrupt module RM0017 interrupt co ntroller (intc) doc id 14629 rev 8 286/904 174 0x0ab8 4 flexcan_esr_boff | flexcan_transmit_warning | flexcan_receive_warning flexcan_3 175 0x0abc 4 reserved 176 0x0ac0 4 flexcan_buf_0_3 flexcan_3 177 0x0ac4 4 flexcan_buf_4_7 flexcan_3 178 0x0ac8 4 flexcan_buf_8_11 flexcan_3 179 0x0acc 4 flexcan_buf_12_15 flexcan_3 180 0x0ad0 4 flexcan_buf_16_31 flexcan_3 181 0x0ad4 4 flexcan_buf_32_63 flexcan_3 182 0x0ad8 4 reserved 183 0x0adc 4 reserved 184 0x0ae0 4 reserved 185 0x0ae4 4 reserved 186 0x0ae8 4 reserved 187 0x0aec 4 reserved 188 0x0af0 4 reserved 189 0x0af4 4 reserved 190 0x0af8 4 flexcan_esr flexcan_4 191 0x0afc 4 flexcan_esr_boff | flexcan_transmit_warning | flexcan_receive_warning flexcan_4 192 0x0b00 4 reserved 193 0x0b04 4 flexcan_buf_0_3 flexcan_4 194 0x0b08 4 flexcan_buf_4_7 flexcan_4 195 0x0b0c 4 flexcan_buf_8_11 flexcan_4 196 0x0b10 4 flexcan_buf_12_15 flexcan_4 197 0x0b14 4 flexcan_buf_16_31 flexcan_4 198 0x0b18 4 flexcan_buf_32_63 flexcan_4 199 0x0b1c 4 reserved 200 0x0b20 4 reserved 201 0x0b24 4 reserved 202 0x0b28 4 flexcan_esr flexcan_5 table 123. interrupt vector table (continued) irq # offset size (bytes) interrupt module interrupt controller (intc) RM0017 287/904 doc id 14629 rev 8 16.6.1 interrupt request sources the intc has two types of interrupt requests, peripheral and software configurable. these interrupt requests can assert on any clock cycle. peripheral interrupt requests an interrupt event in a peripheral?s hardware sets a flag bit that resides in the peripheral. the interrupt request from the peripheral is driven by that flag bit. the time from when the peripheral starts to drive its peripheral interrupt request to the intc to the time that the intc starts to drive the interrupt request to the processor is three clocks. external interrupts are handled by the siu (see section 19.6.3 external interrupts ). software configurable interrupt requests an interrupt request is triggered by software by writing a 1 to a set x bit in intc_sscir0_3?intc_sscir4_7 . this write sets the corresponding flag bit, clr x , resulting in the interrupt request. the interrupt request is cleared by writing a 1 to the clr x bit. the time from the write to the set x bit to the time that the intc starts to drive the interrupt request to the processor is four clocks. 203 0x0b2c 4 flexcan_esr_boff | flexcan_transmit_warning | flexcan_receive_warning flexcan_5 204 0x0b30 4 reserved 205 0x0b34 4 flexcan_buf_0_3 flexcan_5 206 0x0b38 4 flexcan_buf_4_7 flexcan_5 207 0x0b3c 4 flexcan_buf_8_11 flexcan_5 208 0x0b40 4 flexcan_buf_12_15 flexcan_5 209 0x0b44 4 flexcan_buf_16_31 flexcan_5 210 0x0b48 4 flexcan_buf_32_63 flexcan_5 211 0x0b4c 4 reserved 212 0x0b50 4 reserved 213 0x0b54 4 reserved 214 0x0b58 4 reserved 215 0x0b5c 4 reserved 216 0x0b60 4 reserved table 123. interrupt vector table (continued) irq # offset size (bytes) interrupt module RM0017 interrupt co ntroller (intc) doc id 14629 rev 8 288/904 unique vector for each interrupt request source each peripheral and software configurable interrupt request is assigned a hardwired unique 9-bit vector. software configurable interrupts 0?7 are assigned vectors 0?7 respectively. the peripheral interrupt requests are assigned vectors 8 to as high as needed to include all the peripheral interrupt requests. the peripheral interrupt request input ports at the boundary of the intc block are assigned specific ha rdwired vectors within the intc (see ta b l e 1 1 4 ). 16.6.2 priority management the asserted interrupt requests are compared to each other based on their pri x values set in the intc priority select registers (intc_psr0_3?intc_psr208_210). the result is compared to pri in the associated intc_cpr . the results of those comparisons manage the priority of the isr executed by the associated processor. the associated lifo also assists in managing that priority. current priority and preemption the priority arbitrator, selector, encoder, and comparator subblocks shown in figure 118 compare the priority of the asserted interrupt requests to the current priority. if the priority of any asserted peripheral or software configurable interrupt request is higher than the current priority for a given processor, then the interrupt request to the processor is asserted. also, a unique vector for the preempting peripheral or software configurable interrupt request is generated for intc interrupt acknowledge register (intc_iackr), and if in hardware vector mode, for the interrupt vector provided to the processor. priority arbitrator subblock the priority arbitrator subblock for each processor compares all the priorities of all of the asserted interrupt requests assigned to that processor, both peripheral and software configurable. the output of the priority arbitrator subblock is the highest of those priorities assigned to a given processor. also, any interr upt requests which have this highest priority are output as asserted interrupt requests to the associated request selector subblock. request selector subblock if only one interrupt request from the associated priority arbitrator subblock is asserted, then it is passed as asserted to the associated vector encoder subblock. if multiple interrupt requests from the associated priority arbitrator subblock are asserted, the only the one with the lowest vector is passed as asserted to the associated vector encoder subblock. the lower vector is chosen regardless of the time order of the assertions of the peripheral or software configurable interrupt requests. vector encoder subblock the vector encoder subblock generates the unique 9-bit vector for the asserted interrupt request from the request selector subblock for the associated processor. priority comparator subblock the priority comparator subblock compares the highest priority output from the priority arbitrator subblock with pri in intc_cpr. if the priority comparator subblock detects that this highest priority is higher than the current pr iority, then it asserts the interrupt request to the associated processor. this interrupt request to the processor asserts whether this highest priority is raised above the value of pri in intc_cpr or the pri value in interrupt controller (intc) RM0017 289/904 doc id 14629 rev 8 intc_cpr is lowered below this highest priori ty. this highest priority then becomes the new priority which will be written to pri in intc _cpr when the interrupt request to the processor is acknowledged. interrupt requests whose pri n in intc_psr n are zero will not cause a preemption because their pri n will not be higher than pri in intc_cpr. last-in first-out (lifo) the lifo stores the preempted pri values fr om the intc_cpr. therefore, because these priorities are stacked within the intc, if interrupts need to be enabled during the isr, at the beginning of the interrupt exception handler the pri value in the intc_cpr does not need to be loaded from the intc_cpr and stored onto the context stack. likewise at the end of the interrupt exception handler, the priority does not need to be loaded from the context stack and stored into the intc_cpr. the pri value in the intc_cpr is pushed onto the lifo when the intc_iackr is read in softwarevector mode or the interrupt acknowledge signal from the processor is asserted in hardware vector mode. the priority is popped into pri in the intc_cpr whenever the intc_eoir is written. although the intc supports 16 priorities, an isr executing with pri in the intc_cpr equal to 15 will not be preempted. therefore, the li fo supports the stacking of 15 priorities. however, the lifo is only 14 entries deep. an entry for a priority of 0 is not needed because of how pushing onto a full lifo and popping an empty lifo are treated. if the lifo is pushed 15 or more times than it is popped, the priorities first pushed are overwritten. a priority of 0 would be an overwr itten priority. however, the lifo will pop ?0?s if it is popped more times than it is pushed. therefore, although a priority of 0 was overwritten, it is regenerated with the popping of an empty lifo. the lifo is not memory mapped. 16.6.3 handshaking with processor software vector mode handshaking this section describes handshaking in software vector mode. acknowledging interrupt request to processor a timing diagram of the interrupt request and acknowledge handshaking in software vector mode, along with the handshaking near the end of the interrupt exception handler, is shown in figure 128 . the intc examines the peripheral and software configurable interrupt requests. when it finds an asserted peripheral or software configurable interrupt request with a higher priority than pri in the associat ed intc_cpr, it asserts the interrupt request to the processor. the intvec field in the associated intc_iackr is updated with the preempting interrupt request?s vector when the interrupt request to the processor is asserted. the intvec field retains that value until the next time the interrupt request to the processor is asserted. the rest of the handshaking is described in section software vector mode . end of interrupt exception handler before the interrupt exception handling completes, intc end-of-interrupt register (intc_eoir) must be written.when written, the associated lifo is popped so the preempted priority is restored into pri of the intc_cpr. before it is written, the peripheral RM0017 interrupt co ntroller (intc) doc id 14629 rev 8 290/904 or software configurable flag bit must be cleared so that the peripheral or software configurable interrupt request is negated. note: to ensure proper operation across all power architecture ? mcus, execute an mbar or msync instruction between the access to clear the flag bit and the write to the intc_eoir. when returning from the preemption, the intc does not search for the peripheral or software settable interrupt request whose isr was preempted. depending on how much the isr progressed, that interrupt request may no longer even be asserted. when pri in intc_cpr is lowered to the priority of the preempted isr, the interrupt request for the preempted isr or any other asserted peripheral or software settable interrupt request at or below that priority will not cause a preempti on. instead, after the restoration of the preempted context, the processor will return to the instruction address that it was to next execute before it was preempted. this next instruction is part of the preempted isr or the interrupt exception handler?s prolog or epilog. figure 128. software vector mode handshaking timing diagram hardware vector mode handshaking a timing diagram of the interrupt request and acknowledge handshaking in hardware vector mode, along with the handshaking near the end of the interrupt exception handler, is shown in figure 129 . as in software vector mode, the intc examines the peripheral and software settable interrupt requests, and when it finds an asserted one with a higher priority than pri in intc_cpr, it asserts the interrupt request to the processor. the intvec field in the intc_iackr is updated with the preempting peripheral or software settable interrupt request?s vector when the interrupt request to the processor is asserted. the intvec field retains that value until the next time the interrupt request to the processor is asserted. in addition, the value of the interrupt vector to the processor matches the value of the intvec 0 1 0 clock interrupt request to processor hardware vector enable interrupt vector interrupt acknowledge read intc_iackr write intc_eoir intvec in intc_iackr pri in intc_cpr peripheral interrupt request 100 0 108 0 interrupt controller (intc) RM0017 291/904 doc id 14629 rev 8 field in the intc_iackr. the rest of the handshaking is described in section hardware vector mode . the handshaking near the end of the interrupt exception handler, that is the writing to the intc_eoir, is the same as in software vector mode. refer to section end of interrupt exception handler . figure 129. hardware vector mode handshaking timing diagram 16.7 initialization/app lication information 16.7.1 initialization flow after exiting reset, all of the pri n fields in intc priority select registers (intc_psr0? intc_psr210) will be zero, and pri in intc cu rrent priority register (intc_cpr) will be 15. these reset values will prevent the intc fr om asserting the inte rrupt request to the processor. the enable or mask bits in the peripherals are reset such that the peripheral interrupt requests are negated. an initialization sequence for allowing the peripheral and software settable interrupt requests to cause an interrupt request to the processor is:interrupt_request_initialization: interrupt_request_initialization: configure vtes and hven in intc_mcr configure vtba in intc_iackr raise the pri n fields in intc_psr n 0 108 0 1 0 clock interrupt request to processor hardware vector enable interrupt vector interrupt acknowledge read intc_iackr write intc_eoir intvec in intc_iackr pri in intc_cpr peripheral interrupt request 100 0 108 RM0017 interrupt co ntroller (intc) doc id 14629 rev 8 292/904 set the enable bits or clear the mask bits for the peripheral interrupt requests lower pri in intc_cpr to zero enable processor recognition of interrupts 16.7.2 interrupt exception handler these example interrupt exception handlers use power architecture? assembly code. software vector mode interrupt_exception_handler: code to create stack frame, save working register, and save srr0 and srr1 lis r3,intc_iackr@ha # form adjusted upper half of intc_iackr address lwz r3,intc_iackr@l(r3) # load intc_iackr, which clears request to processor lwz r3,0x0(r3) # load address of isr from vector table wrteei 1 # enable processor recognition of interrupts code to save rest of context required by e500 eabi mtlr r3 # move intc_iackr contents into link register blrl # branch to isr; link register updated with epilog # address epilog: code to restore most of context required by e500 eabi # popping the lifo after the restoration of most of the context and the disabling of processor # recognition of interrupts eases the calculation of the maximum stack depth at the cost of # postponing the servicing of the next interrupt request. mbar # ensure store to clear flag bit has completed lis r3,intc_eoir@ha # form adjusted upper half of intc_eoir address li r4,0x0 # form 0 to write to intc_eoir wrteei 0 # disable processor recognition of interrupts stw r4,intc_eoir@l(r3) # store to intc_eoir, informing intc to lower priority code to restore srr0 and srr1, restore working registers, and delete stack frame rfi vector_table_base_address: address of isr for interrupt with vector 0 address of isr for interrupt with vector 1 . . . address of isr for interrupt with vector 510 address of isr for interrupt with vector 511 isr x : code to service the interrupt event interrupt controller (intc) RM0017 293/904 doc id 14629 rev 8 code to clear flag bit which drives interrupt request to intc blr # return to epilog hardware vector mode this interrupt exception handler is useful with processor and system bus implementations which support a hardware vector. this example assumes that each interrupt_exception_handler x only has space for four instructions, and therefore a branch to interrupt_exception_handler_continued x is needed. interrupt_exception_handler x : b interrupt_exception_handler_continued x # 4 instructions available, branch to continue interrupt_exception_handler_continued x : code to create stack frame, save working register, and save srr0 and srr1 wrteei 1 # enable processor recognition of interrupts code to save rest of context required by e500 eabi bl isr x # branch to isr for interrupt with vector x epilog: code to restore most of context required by e500 eabi # popping the lifo after the restoration of most of the context and the disabling of processor # recognition of interrupts eases the calculation of the maximum stack depth at the cost of # postponing the servicing of the next interrupt request. mbar # ensure store to clear flag bit has completed lis r3,intc_eoir@ha # form adjusted upper half of intc_eoir address li r4,0x0 # form 0 to write to intc_eoir wrteei 0 # disable processor recognition of interrupts stw r4,intc_eoir@l(r3) # store to intc_eoir, informing intc to lower priority code to restore srr0 and srr1, restore working registers, and delete stack frame rfi isr x : code to service the interrupt event code to clear flag bit which drives interrupt request to intc blr # branch to epilog 16.7.3 isr, rtos, and task hierarchy the rtos and all of the tasks under its contro l typically execute with pri in intc current priority register (intc_cpr) having a value of 0. the rtos will execute the tasks according to whatever priority scheme that it may have, but that priority scheme is independent and RM0017 interrupt co ntroller (intc) doc id 14629 rev 8 294/904 has a lower priority of execution than the priority scheme of the intc. in other words, the isrs execute above intc_cpr priority 0 and outside the control of the rtos, the rtos executes at intc_cpr priority 0, and while the tasks execute at different priorities under the control of the rtos, they also execute at intc_cpr priority 0. if a task shares a resource with an isr and the pcp is being used to manage that shared resource, then the task?s priority can be elevated in the intc_cpr while the shared resource is being accessed. an isr whose pri n in intc priority select registers (intc_psr0?intc_psr210) has a value of 0 will not cause an interrupt request to the processor, even if its peripheral or software settable interrupt request is asserted. for a peripheral interrupt request, not setting its enable bit or disabling the mask bit will ca use it to remain negat ed, which consequently also will not cause an interrupt request to th e processor. since the isrs are outside the control of the rtos, this isr will not run un less called by another isr or the interrupt exception handler, perhaps after executing another isr. 16.7.4 order of execution an isr with a higher priority can preempt an isr with a lower priority, regardless of the unique vectors associated with each of their peripheral or software configurable interrupt requests. however, if multiple peripheral or software configurable interrupt requests are asserted, more than one has the highest priority, and that priority is high enough to cause preemption, the intc selects the one with the lowest unique vector regardless of the order in time that they asserted. however, the ability to meet deadlines with this scheduling scheme is no less than if the isrs execute in the time order that their peripheral or software configurable interrupt requests asserted. the example in ta b l e 1 2 4 shows the order of execution of both isrs with different priorities and the same priority. table 124. order of isr execution example step no. step description code executing at end of step pri in intc_cpr at end of step rtos isr108 (1) isr208 isr308 isr408 interrupt exception handler 1 rtos at priority 0 is executing. x 0 2 peripheral interrupt request 100 at priority 1 asserts. interrupt taken. x1 3 peripheral interrupt request 400 at priority 4 is asserts. interrupt taken. x4 4 peripheral interrupt request 300 at priority 3 is asserts. x4 5 peripheral interrupt request 200 at priority 3 is asserts. x4 6 isr408 completes. interrupt exception handler writes to intc_eoir. x1 interrupt controller (intc) RM0017 295/904 doc id 14629 rev 8 16.7.5 priority ceiling protocol elevating priority the pri field in intc_cpr is elevated in the osek pcp to t he ceiling of all of the priorities of the isrs that share a resource. this protoc ol allows coherent accesses of the isrs to that shared resource. for example, isr1 has a priority of 1, isr2 has a priority of 2, and isr3 has a priority of 3. they share the same resource. before isr1 or isr2 can access that resource, they must raise the pri value in intc_cpr to 3, the ce iling of all of the isr priorities. after they release the resource, the pri value in intc_cpr can be lowered. if they do not raise their priority, isr2 can preempt isr1, and isr3 can preempt isr1 or isr2, possibly corrupting the shared resource. another possible failure mechanism is deadlock if the higher priority isr needs the lower priority isr to release the resource before it can continue, but the lower priority isr cannot release the resource until the higher priority isr completes and execution returns to the lower priority isr. using the pcp instead of disabling processor recognition of all interrupts eliminates the time when accessing a shared resource that all higher priority interrupts are blocked. for example, while isr3 cannot preempt isr1 while it is accessing the shared resource, all of the isrs with a priority higher than 3 can preempt isr1. ensuring coherency a scenario can cause non-coherent accesses to the shared resource. for example, isr1 and isr2 are both running on the same core and both share a resource. isr1 has a lower priority than isr2. isr1 is executing and wr ites to the intc_cpr. the instruction following 7 interrupt taken. isr208 starts to execute, even though peripheral interrupt request 300 asserted first. x3 8 isr208 completes. interrupt exception handler writes to intc_eoir. x1 9 interrupt taken. isr308 starts to execute. x3 10 isr308 completes. interrupt exception handler writes to intc_eoir. x1 11 isr108 completes. interrupt exception handler writes to intc_eoir. x0 12 rtos continues execution. x 0 1. isr108 executes for peripheral interrupt request 100 because the firs t eight isrs are for software configurable interrupt requests. table 124. order of isr execution example (continued) step no. step description code executing at end of step pri in intc_cpr at end of step rtos isr108 (1) isr208 isr308 isr408 interrupt exception handler RM0017 interrupt co ntroller (intc) doc id 14629 rev 8 296/904 this store is a store to a value in a shared coherent data block. either immediately before or at the same time as the first store, the intc asserts the interrupt request to the processor because the peripheral interrupt request for isr2 has asserted. as the processor is responding to the interrupt request from the intc, and as it is aborting transactions and flushing its pipeline, it is possible that both stores will be executed. isr2 thereby thinks that it can access the data block coherently, but the data block has been corrupted. osek uses the getresource and releaseresourc e system services to manage access to a shared resource. to prevent corruption of a coherent data block, modifications to pri in intc_cpr can be made by those system services with the code sequence: disable processor recognition of interrupts pri modification enable processor recognition of interrupts 16.7.6 selecting priorities according to request rates and deadlines the selection of the priorities for the isrs can be made using rate monotonic scheduling (rms) or a superset of it, deadline monotonic scheduling (dms). in rms, the isrs which have higher request rates have higher priorities. in dms, if the deadline is before the next time the isr is requested, then the isr is assigned a priority according to the time from the request for the isr to the deadline, not from the time of the request for the isr to the next request for it. for example, isr1 executes every 100 s, isr2 executes every 200 s, and isr3 executes every 300 s. isr1 has a higher priority than isr2 which has a higher priority than isr3; however, if isr3 has a deadline of 150 s, then it has a higher priority than isr2. the intc has 16 priorities, which may be less than the number of isrs. in this case, the isrs should be grouped with other isrs that have similar deadlines. for example, a priority could be allocated for every time the request rate doubles. isrs with request rates around 1 ms would share a priority, isrs with request rates around 500 s would share a priority, isrs with request rates around 250 s would share a priority, etc. with this approach, a range of isr request rates of 2 16 could be included, regardless of the number of isrs. reducing the number of priorities reduces the processor?s ability to meet its deadlines. however, reducing the number of priorities can reduce the size and latency through the interrupt controller. it also allows easier management of isrs with similar deadlines that share a resource. they do not need to use the pcp to access the shared resource. 16.7.7 software configurable interrupt requests the software configurable interrupt requests can be used in two ways. they can be used to schedule a lower priority portion of an isr and they may also be used by processors to interrupt other processors in a multiple processor system. scheduling a lower priority portion of an isr a portion of an isr needs to be executed at the pri x value in the intc priority select registers (intc_psr0_3?intc_psr208_210) , which becomes the pri value in intc_cpr with the interrupt acknowledge. the isr, however, can have a portion that does not need to be executed at this higher priority. therefore, executing the later portion that does not need to be executed at this higher priority can prevent the execution of isrs which do not have a higher priority than the earlier portion of the isr but do have a higher priority than what the later portion of the isr needs. this preemptive scheduling inefficiency reduces the processor?s abilit y to meet its deadlines. interrupt controller (intc) RM0017 297/904 doc id 14629 rev 8 one option is for the isr to complete the earlier higher priority portion, but then schedule through the rtos a task to execute the later lower priority portion. however, some rtoss can require a large amount of time for an isr to schedule a task. therefore, a second option is for the isr, after completing the higher priority portion, to set a set x bit in intc_sscir0_3?intc_sscir4_7 . writing a 1 to set x causes a software configurable interrupt request. this software configurable interrupt request will usually have a lower pri x value in the intc_psr x _ x and will not cause preemptive scheduling inefficiencies. after generating a software settable interrupt request, the higher priority isr completes. the lower priority isr is scheduled according to its priority. execution of the higher priority isr is not resumed after the completion of the lower priority isr. scheduling an isr on another processor because the set x bits in the intc_sscir x _ x are memory mapped, processors in multiple- processor systems can schedule isrs on the other processors. one application is that one processor wants to command another processor to perform a piece of work and the initiating processor does not need to use the results of that work. if the initiating processor is concerned that the processor executing the software configurable isr has not completed the work before asking it to again execute the isr, it can check if the corresponding clr x bit in intc_sscir x _ x is asserted before again writing a 1 to the set x bit. another application is the sharing of a block of data. for example, a first processor has completed accessing a block of data and wants a second processor to then access it. furthermore, after the second processor has completed accessing the block of data, the first processor again wants to access it. the accesses to the block of data must be done coherently. to do this, the first processor writes a 1 to a set x bit on the second processor. after accessing the block of data, the second processor clears the corresponding clr x bit and then writes 1 to a set x bit on the first processor, informing it that it can now access the block of data. 16.7.8 lowering priori ty within an isr a common method for avoiding preemptive scheduling inefficiencies with an isr whose work spans multiple priorities (see section scheduling a lower priority portion of an isr ) is to lower the current priority. however, the intc has a lifo whose depth is determined by the number of priorities. note: lowering the pri value in intc_cpr within an isr to below the isr?s corresponding pri value in the intc priority select regist ers (intc_psr0_3?intc_psr208_210) allows more preemptions than the lifo depth can support. therefore, the intc does not support lowering the current priority within an isr as a way to avoid preemptive scheduling inefficiencies. 16.7.9 negating an interrupt request outside of its isr negating an interrupt request as a side effect of an isr some peripherals have flag bits that can be cleare d as a side effect of servicing a peripheral interrupt request. for example, reading a specific register can clear the flag bits and their corresponding interrupt requests. this clearing as a side effect of servicing a peripheral interrupt request can cause the negation of other peripheral interrupt requests besides the peripheral interrupt request whose isr presently is executing. this negating of a peripheral interrupt request outside of its isr can be a desired effect. RM0017 interrupt co ntroller (intc) doc id 14629 rev 8 298/904 negating multiple interrupt requests in one isr an isr can clear other flag bits besides its own. one reason that an isr clears multiple flag bits is because it serviced those flag bits, and therefore the isrs for these flag bits do not need to be executed. proper setting of interrupt request priority whether an interrupt request negates outside its own isr due to the side effect of an isr execution or the intentional clearing a flag bit, the priorities of the peripheral or software configurable interrupt requests for these other flag bits must be selected properly. their pri x values in the intc priority select registers (intc_psr0_3?intc_psr208_210) must be selected to be at or lower than the priority of the isr that cleared their flag bits. otherwise, those flag bits can cause the interrupt request to the processor to assert. furthermore, the clearing of these other flag bits also has the same timing relationship to the writing to intc_sscir0_3?intc_sscir4_7 as the clearing of the flag bit that caused the present isr to be executed (see section end of interrupt exception handler ). a flag bit whose enable bit or mask bit negat es its peripheral interrupt request can be cleared at any time, regardless of the peripheral interrupt request?s pri x value in intc_psr x _ x . 16.7.10 examining lifo contents in normal mode, the user does not need to know the contents of the lifo. he may not even know how deeply the lifo is nested. however, if he wants to read the contents, such as in debug mode, they are not memory mapped. the contents can be read by popping the lifo and reading the pri field in either intc_cpr . the code sequence is: pop_lifo: store to intc_eoir load intc_cpr, examine pri, and store onto stack if pri is not zero or value when interrupts were enabled, branch to pop_lifo when the examination is complete, the lifo can be restored using this code sequence: push_lifo: load stacked pri value and store to intc_cpr load intc_iackr if stacked pri values are not depleted, branch to push_lifo crossbar switch (xbar) RM0017 299/904 doc id 14629 rev 8 17 crossbar switch (xbar) 17.1 introduction this chapter describes the multi-port crossbar switch (xbar), which supports simultaneous connections betwee n two master ports and three sl ave ports. xbar supports a 32-bit address bus width and a 32-bit data bus width at all master and slave ports. 17.2 block diagram figure 130 shows a block diagram of the crossbar switch. figure 130. xbar block diagram table 125 gives the crossbar switch port for each master and slave, and the assigned and fixed id number for each master. the table shows the master id numbers as they relate to the master port numbers. cpu crossbar switch flash master modules slave modules cpu data / internal peripheral bridges instructions nexus memory sram table 125. xbar switch ports for spc560bx and spc560cx module port physical master id type logical number e200z0 core?cpu instructions master 0 0 e200z0 core?cpu data / nexus master 0 1 flash memory slave 0 ? internal sram slave 2 ? peripheral bridges slave 7 ? RM0017 crossbar switch (xbar) doc id 14629 rev 8 300/904 17.3 overview the xbar allows for concurrent transactions to occur from any master port to any slave port. it is possible for all master ports and slave ports to be in use at the same time as a result of independent master requests. if a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher priority master and grants it ownership of the slave port. all other masters requesting that slave port are stalled until the higher priority master completes its transactions. requesting masters are granted access based on a fixed priority. 17.4 features 2 master ports: ? core: e200z0 core instructions ? core: e200z0 core data / nexus 3 slave ports ? flash (refer to the flash memory chapter for information on accessing flash memory) ? internal sram ? peripheral bridges 32-bit address, 32-bit data paths fully concurrent transfers between independent master and slave ports fixed priority scheme and fixed parking strategy 17.5 modes of operation 17.5.1 normal mode in normal mode, the xbar provid es the logic that co ntrols crossbar s witch configuration. 17.5.2 debug mode the xbar operation in debu g mode is identical to op eration in normal mode. 17.6 functional description this section describes the functi onality of the xbar in more detail. 17.6.1 overview the main goal of the xbar is to increase ov erall system performance by allowing multiple masters to communicate concurrently with multiple slaves. to maximize data throughput, it is essential to keep arbitration delays to a minimum. this section examines data throughput from the point of view of masters and slaves, detailing when the xbar stalls masters, or inserts bubbles on the slave side. crossbar switch (xbar) RM0017 301/904 doc id 14629 rev 8 17.6.2 general operation when a master makes an access to the xbar from an idle master state, the access is taken immediately by the xbar. if the targeted slave port of the access is available (that is, the requesting master is currently granted ownership of the slave port), the access is immediately presented on the slave port. it is possible to make single clock (zero wait state) accesses through the xbar by a granted master. if the targeted slave port of the access is busy or parked on a different master port, the requesting master receives wait states until the targeted slave port can service the master request. the latency in servicing the request depends on each master?s priority level and the responding slave?s access time. because the xbar ap pears to be simply another slave to the master devi ce, the master device has no indication that it owns the slave port it is targeting. while the master does not have control of the slave port it is targeting, it is wait-stated. a master is given control of a targeted slave port only after a previous access to a different slave port has completed, regardless of its priority on the newly targeted slave port. this prevents deadlock from occurring when a master has the following conditions: outstanding request to slave port a that has a long response time pending access to a different slave port b lower priority master also makes a request to the different slave port b. in this case, the lower priority master is gr anted bus ownership of slave port b after a cycle of arbitration, assuming the higher priority master slave port a access is not terminated. after a master has control of the slave port it is targeting, the master remains in control of that slave port until it gives up the slave port by running an idle cycle, leaves that slave port for its next access, or loses control of the slave port to a higher priority master with a request to the same slave port. however, because all masters run a fixed-length burst transfer to a slave port, it retains control of the slave port until that transfer sequence is completed. when a slave bus is idled by the xbar, it is parked on the master whic h did the last transfer. 17.6.3 master ports a master access is taken if the slave port to which the access decodes is either currently servicing the master or is parked on the master. in th is case, the xbar is completely transparent and the master access is immediately transmitted on the slave bus and no arbitration delays are incurred. a master access stall if the access decodes to a slave port that is busy serving another master, parked on another master. if the slave port is currently parked on another master, and no other master is requesting access to the slave port, then only one clock of arbitration is incurred. if the slave port is currently serving another master of a lower priority and the master has a higher priority than all other requesting masters, then the master gains control over the slave port as soon as the data phase of the current access is completed. if the slave port is currently servicing another master of a higher priority, then the master gains control of the slave port after the other master releases control of the slave port if no other higher priority master is also waiting for the slave port. a master access is responded to with an error if the access decodes to a location not occupied by a slave port. this is the only time the xbar directly responds with an error response. all other error responses received by the master are the result of error responses on the slave ports being passed through the xbar. RM0017 crossbar switch (xbar) doc id 14629 rev 8 302/904 17.6.4 slave ports the goal of the xbar wit h respect to the slave ports is to keep them 100% saturated when masters are actively making requests. to do this the xbar must not insert any bubbles onto the slave bus unless absolutely necessary. there is only one instance when the xbar fo rces a bubble onto the slave bus when a master is actively making a request. this oc curs when a handoff of bus ownership occurs and there are no wait states from the slave port. a requesting master which does not own the slave port is granted access after a one clock delay. 17.6.5 priority assignment each master port is assigned a fixed 3-bit priority level (hard-wired priority). the following table shows the priority levels assigned to each master (the lowest has highest priority). 17.6.6 arbitration xbar supports only a fixed-prio rity comparison algorithm. fixed priority operation when operating in fixed-priority arbitration mode, each master is assigned a unique priority level in the xbar_mpr. if two ma sters both request ac cess to a slave port, the master with the highest priority in the selected priority register gains control over the slave port. any time a master makes a request to a slave port, the slave port checks to see if the new requesting master?s priority level is higher than that of the master that currently has control over the slave port (if any). the slave port does an arbitration check at every clock edge to ensure that the proper master (if any) has control of the slave port. if the new requesting master?s priority level is higher than that of the master that currently has control of the slave port, the higher priority master is granted control at the termination of any currently pending access, assuming the pending transfer is not part of a burst transfer. a new requesting master must wait until the end of the fixed-length burst transfer, before it is granted control of the slave port. but if the new requesting master?s priority level is lower than that of the master that currently has control of the slave port, the new requesting master is forced to wait until the master that cu rrently has control of the slave port is finished accessing the current slave port. parking if no master is currently requesting the slave port, the slave port is parked. the slave port parks always to the last master (park-on-last). when parked on the last master, the slave port is passing that master?s signals through to the slave bus. when the master accesses table 126. hardwired bus master priorities module port priority level type number e200z0 core?cpu instructions master 0 7 e200z0 core?cpu data / nexus master 0 6 crossbar switch (xbar) RM0017 303/904 doc id 14629 rev 8 the slave port again, no other arbitration penalties are incurred except that a one clock arbitration penalty is incurred for each access request to the slave port made by another master port. all other masters pay a one clock penalty. RM0017 memory protection unit (mpu) doc id 14629 rev 8 304/904 18 memory protection unit (mpu) 18.1 introduction the memory protection unit (mpu) provides hardware access control for all memory references generated in the device. using preprogrammed region descriptors which define memory spaces and their associated access rights, the mpu concurrently monitors all system bus transactions and evaluates the appropriateness of each transfer. memory references that have sufficient access cont rol rights are allowed to complete, while references that are not mapped to any region descriptor or have insufficient rights are terminated with a protection error response. the mpu module provides the following capabilities: support for 8 program-visible 128-bit (4-word) region descriptors ? each region descriptor defines a modulo-32 byte space, aligned anywhere in memory region sizes can vary from a minimum of 32 bytes to a maximum of 4 gbytes ? two types of access control permissions defined in single descriptor word processors have separate {read, write, execute} attributes for supervisor and user accesses non-processor masters have {read, write} attributes ? hardware-assisted maintenance of the descriptor valid bit minimizes coherency issues ? alternate programming model view of the access control permissions word memory-mapped platform device ? interface to 3 slave xbar ports: flas h controller, system sram controller and peripherals bus connections to the address phase address and attributes typical location is immediately ?downstream? of the platform?s crossbar switch a simplified block diagram of the mpu module is shown in figure 131 . memory protection unit (mpu) RM0017 305/904 doc id 14629 rev 8 figure 131. mpu block diagram 18.2 features the memory protection unit implements a two-dimensional hardware array of memory region descriptors and the crossbar slave xbar por ts to continuously mo nitor the legality of every memory reference generated by each bus master in the system. the feature set includes: support for 8 memory region descriptors, each 128 bits in size ? specification of start and end addresses provide granularity for region sizes from 32 bytes to 4 gb ? access control definitions: 2 bus masters (p rocessor cores) supp ort the traditional {read, write, execute} permissions with independent definitions for supervisor and user mode accesses ? automatic hardware maintenance of the region descriptor valid bit removes issues associated with maintaining a coherent image of the descriptor ? alternate memory view of the access control word for each descriptor provides an efficient mechanism to dynamically alter only the access rights of a descriptor ? for overlapping region descriptors, priority is given to permission granting over access denying as th is approach provides more flex ibility to system software. see pflash pram pbridge0 core (z0hn2p) xbar mpu s0 s2 s7 m0 m1 platform RM0017 memory protection unit (mpu) doc id 14629 rev 8 306/904 section 18.6.2 putting it all together and ahb error terminations for details and section 18.8 application information for an example. support for 3 xbar slave port connections: flash controller, syst em sram controller and peripherals bus ? mpu hardware continuous ly monitors every xbar slave port access using the preprogrammed memory region descriptors ? an access protection error is detected if a memory reference does not hit in any memory region or the reference is flagged as illegal in all memory regions where it does hit. in the event of an access error, the xbar reference is terminated with an error response and the mpu inhibits the bus cycle being sent to the targeted slave device. ? 64-bit error registers, one for each xbar slave port, capture the last faulting address, attributes and ?detail? information global mpu enable/disable control bit provides a mechanism to easily load region descriptors during system startup or allow complete access rights during debug with the module disabled 18.3 modes of operation the mpu module does not support any special modes of operation. as a memory-mapped device located on the platform?s high-speed system bus, it responds based strictly on the memory addresses of the connected system buses. the peripheral bus is used to access the mpu?s programming model and the memory protection functions are evaluated on a reference-by-reference basis using the addresses from the xbar system bus port(s). power dissipation is minimized when the mp u?s global enable/disable bit is cleared (mpu_cesr[vld] = 0). 18.4 external signal description the mpu module does not include any external interface. the mpu?s internal interfaces include a peripheral bus connection for accessing the programming model and multiple connections to the address phase signals of the platform crossbar?s slave ahb ports. from a platform topology viewpoint, the mpu module appears to be directly connected ?downstream? from the cros sbar switch with interfaces to the xbar slave ports. 18.5 memory map and register description the mpu module provides an ips programming model ma pped to an spp- standard on- platform 16 kb space. the programming model is partitioned into three groups: control/status registers, the data structure containing the region descriptors and the alternate view of the region descriptor access control values. the programming model can only be referenced using 32-bit (word) accesses. attempted references using different access sizes, to undefined (reserved) addresses, or with a non- supported access type (for example, a write to a read-only register or a read of a write-only register) generate an ips error termination. memory protection unit (mpu) RM0017 307/904 doc id 14629 rev 8 finally, the programming model allocates space for an mpu definition with 8 region descriptors and up to 3 xbar slave ports, like flash controller, system sram controller and peripheral bus. 18.5.1 memory map the mpu programming model map is shown in ta b l e 1 2 7 . table 127. mpu memory map base address: 0xfff1_1000 address offset register location 0x000 mpu control/error status register (mpu_cesr) on page 18-308 0x004?0x00f reserved 0x010 mpu error address register, slave port 0 (mpu_ear0) on page 18-309 0x014 mpu error detail register, slave port 0 (mpu_edr0) on page 18-309 0x018 mpu error address register, slave port 1 (mpu_ear1) on page 18-309 0x01c mpu error detail register, slave port 1 (mpu_edr1) on page 18-309 0x020 mpu error address register, slave port 2 (mpu_ear2) on page 18-309 0x024 mpu error detail register, slave port 2 (mpu_edr2) on page 18-309 0x028?0x3ff reserved 0x400 mpu region descriptor 0 (mpu_rgd0) on page 18-311 0x410 mpu region descriptor 1 (mpu_rgd1) on page 18-311 0x420 mpu region descriptor 2 (mpu_rgd2) on page 18-311 0x430 mpu region descriptor 3 (mpu_rgd3) on page 18-311 0x440 mpu region descriptor 4 (mpu_rgd4) on page 18-311 0x450 mpu region descriptor 5 (mpu_rgd5) on page 18-311 0x460 mpu region descriptor 6 (mpu_rgd6) on page 18-311 0x470 mpu region descriptor 7 (mpu_rgd7) on page 18-311 0x480?0x7ff reserved 0x800 mpu rgd alternate access control 0 (mpu_rgdaac0) on page 18-316 0x804 mpu rgd alternate access control 1 (mpu_rgdaac1) on page 18-316 0x808 mpu rgd alternate access control 2 (mpu_rgdaac2) on page 18-316 0x80c mpu rgd alternate access control 3 (mpu_rgdaac3) on page 18-316 0x810 mpu rgd alternate access control 4 (mpu_rgdaac4) on page 18-316 0x814 mpu rgd alternate access control 5 (mpu_rgdaac5) on page 18-316 0x818 mpu rgd alternate access control 6 (mpu_rgdaac6) on page 18-316 0x81c mpu rgd alternate access control 7 (mpu_rgdaac7) on page 18-316 RM0017 memory protection unit (mpu) doc id 14629 rev 8 308/904 18.5.2 register description mpu control/error status register (mpu_cesr) the mpu_cesr provides one byte of error status plus three bytes of configuration information. a global mpu enable/disable bit is also included in this register. figure 132. mpu control/error status register (mpu_cesr) offset: 0x000 access: read/partial write 0123456789101112131415 r sperr[7:0] 1 0 0 0 hrl w w1c w1c w1c w1c w1c w1c w1c w1c reset000000001000* * * * 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r nsp nrgd 0 0 00 0 0 0 vld w reset********00000000 table 128. mpu_cesr field descriptions field description sperrn slave port n error, where the slave port number matches the bit number. each bit in this field represents a flag maintained by the mpu for signaling the presence of a captured error contained in the mpu_earn and mpu_edrn registers. the individual bit is set when the hardware detects an error and records the faulting address and attributes. it is cleared when the corresponding bit is written as a logical one. if another error is captured at the exact same cycle as a write of a logical one, this flag remains set. a ?find first one? instruction (or equivalent) can be used to detect the presence of a captured error. 0 the corresponding mpu_earn/mpu_edrn registers do not contain a captured error. 1 the corresponding mpu_earn/mpu_edrn registers do contain a captured error. hrl hardware revision level this field specifies the mpu?s hardware and definiti on revision level. it can be read by software to determine the functional definition of the module. nsp number of slave ports this field specifies the number of slave ports [1?8] connected to the mpu. nrgd number of region descriptors this field specifies the number of region descr iptors implemented in the mpu. the defined encodings include: 0b0000 8 region descriptors 0b0001 12 region descriptors 0b0010 16 region descriptors memory protection unit (mpu) RM0017 309/904 doc id 14629 rev 8 mpu error address register, slave port n (mpu_earn) when the mpu detects an access error on sl ave port n, the 32-bit reference address is captured in this read-only register and the corresponding bit in the mpu_cesr[sperr] field set. additional information about the fa ulting access is captured in the corresponding mpu_edrn register at the same time. note this register and the corresponding mpu_edrn register contain the most recent access error; there are no hardware interlocks with the mpu_cesr[sperr] fiel d as the error registers ar e always loaded upon the occurrence of each protection violation. mpu error detail register, slave port n (mpu_edrn) when the mpu detects an access error on slave port n, 32 bits of error detail are captured in this read-only register and the corresponding bit in the mpu_cesr[sperr] field set. information on the faulting address is captured in the corresponding mpu_earn register at the same time. note that this register and the corresponding mpu_earn register contain the most recent access error; there are no hardware interlocks with the mpu_cesr[sperr] field as the error registers are always loaded upon the occurrence of each protection violation. vld valid this bit provides a global enable/disable for the mpu. 0 the mpu is disabled. 1 the mpu is enabled. while the mpu is disabled, all accesses from all bus masters are allowed. table 128. mpu_cesr field descriptions (continued) field description figure 133. mpu error address register, slave port n (mpu_earn) offsets: 0x010?0x020 (3 registers) access: read 0123456789101112131415 r eaddr [31:16] w reset???????????????? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eaddr [15:0] w reset???????????????? table 129. mpu_earn field descriptions field description eaddr error address this field is the reference address from sl ave port n that generated the access error. RM0017 memory protection unit (mpu) doc id 14629 rev 8 310/904 figure 134. mpu error detail register, slave port n (mpu_edrn) offsets: 0x014?0x024 (3 registers) access: read 0123456789101112131415 r eacd w reset???????????????? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r epid emn eattr erw w reset???????????????? table 130. mpu_edrn field descriptions field description eacd error access control detail this field implements one bit per region descriptor a nd is an indication of the region descriptor hit logically anded with the access error indication. the mpu performs a reference-by-reference evaluation to determine the presence/absence of an access error. when an error is detected, the hit- qualified access control vector is captured in this field. if the mpu_edrn register contains a captured erro r and the eacd field is all zeroes, this signals an access that did not hit in any region descriptor. all non-zero eacd values signal references that hit in a region descriptor(s), but failed due to a protection error as defined by the specific set bits. if only a single eacd bit is set, then the protection error was caused by a single non-overlapping region descriptor. if two or more eacd bits are set, then the protection error was caused in an overlapping set of region descriptors. epid error process identification this field records the process identifier of the faulti ng reference. the process identifier is typically driven only by processor cores; for other bus masters, this field is cleared. emn error master number this field records the logical master number of the faulting reference. this field is used to determine the bus master that generated the access error. eattr error attributes this field records attribute information about the faulting reference. the supported encodings are defined as: 0b000 user mode, instruction access 0b001 user mode, data access 0b010supervisor mode, instruction access 0b011supervisor mode, data access all other encodings are reserved. for non-core bu s masters, the access attribute information is typically wired to supervisor, data (0b011). memory protection unit (mpu) RM0017 311/904 doc id 14629 rev 8 mpu region descriptor n (mpu_rgdn) each 128-bit (16 byte) region descriptor specifies a given memory space and the access attributes associated with that space. the descriptor definition is the very essence of the operation of the memory protection unit. the region descriptors are organized sequentially in the mpu?s programming model and each of the four 32-bit words are detailed in the subsequent sections. mpu region descriptor n, word 0 (mpu_rgdn.word0) the first word of the mpu region descriptor defines the 0-modulo-32 byte start address of the memory region. writes to this word clear the region descriptor?s valid bit (see section mpu region descriptor n, word 3 (mpu_rgdn.word3) for more information). mpu region descriptor n, word 1 (mpu_rgdn.word1) the second word of the mpu region descriptor defines the 31-modulo-32 byte end address of the memory region. writes to this word clear the region descriptor?s valid bit (see section mpu region descriptor n, word 3 (mpu_rgdn.word3) for more information). erw error read/write this field signals the access type (read, write) of the faulting reference. 0read 1write table 130. mpu_edrn field descriptions (continued) field description figure 135. mpu region descriptor, word 0 register (mpu_rgdn.word0) offset: 0x400 + (16*n) + 0x0 (mpu_rgdn.word0) access: read/write 0123456789101112131415 r srtaddr[26:11] w reset???????????????? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r srtaddr[10:0] 00000 w reset???????????00000 table 131. mpu_rgdn.word0 field descriptions field description srtaddr start address this field defines the most significant bits of the 0-modulo-32 byte start address of the memory region. RM0017 memory protection unit (mpu) doc id 14629 rev 8 312/904 mpu region descriptor n, word 2 (mpu_rgdn.word2) the third word of the mpu region descriptor defines the access control rights of the memory region. the access control privileges are dependent on two broad classifications of bus masters. bus masters 0?3 are typically reserved for processor cores and the corresponding access control is a 6-bit field defining separate privilege rights for user and supervisor mode accesses as well as the optional inclusion of a process identification field within the definition. bus masters 4?7 are typically reserved for data movement engines and their capabilities are limited to separate read and write permissions. for these fields, the bus master number refers to the logical master number defined as the xbar hmaster[3:0] signal. for the processor privilege rights, there are three flags associated with this function: {read, write, execute}. in this context, these flags follow the traditional definition: read ( r ) permission refers to the ability to acce ss the referenced memory address using an operand (data) fetch. write ( w ) permission refers to th e ability to update the re ferenced memory address using a store (data) instruction. execute ( x ) permission refers to th e ability to read the re ferenced memory address using an instruction fetch. the evaluation logic defines the processor access type based on multiple ahb signals, as hwrite and hprot[1:0]. for non-processor data movement engines (bus masters 4?7), the evaluation logic simply uses hwrite to determine if the access is a read or write. figure 136. mpu region descriptor, word 1 register (mpu_rgdn.word1) offset: 0x400 + (16*n) + 0x4 (mpu_rgdn.word1) access: read/write 0123456789101112131415 r endaddr[26:11] w reset???????????????? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r endaddr[10:0] 11111 w reset???????????11111 table 132. mpu_rgdn.word1 field descriptions field description endaddr end address this field defines the most significant bits of the 31-modulo-32 byte end address of the memory region. there are no hardware checks to verify that endaddr >= srtaddr; it is software?s responsibility to properly load these region descriptor fields. memory protection unit (mpu) RM0017 313/904 doc id 14629 rev 8 writes to this word clear the region descriptor?s valid bit (see section mpu region descriptor n, word 3 (mpu_rgdn.word3) for more information). since it is also expected that system software may adjust only the access controls within a region descriptor (mpu_rgdn.word2) as different tasks execute, an alternate programming view of this 32- bit entity is provided. if only the access controls are being updated, this operation should be performed by writing to mpu_rgdaacn (alternate access control n) as stores to these locations do not affect the descriptor?s valid bit. figure 137. mpu region descriptor, word 2 register (mpu_rgdn.word2) offset: 0x400 + (16*n) + 0x8 (mpu_rgdn.word2) access: r/w 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r m7re m7we m6re m6we m5re m5we m4re m4we m3pe m3sm m3um m2pe m2sm[1] w reset???????????????? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r m2sm[0] m2um m1pe m1sm m1um m0pe m0sm m0um w reset???????????????? table 133. mpu_rgdn.word2 field descriptions field description m7re bus master 7 read enable if set, this flag allows bus master 7 to perform read operations. if cleared, any attempted read by bus master 7 terminates with an access error and the read is not performed. m7we bus master 7 write enable if set, this flag allows bus master 7 to perform writ e operations. if cleared, any attempted write by bus master 7 terminates with an access error and the write is not performed. m6re bus master 6 read enable if set, this flag allows bus master 6 to perform read operations. if cleared, any attempted read by bus master 6 terminates with an access error and the read is not performed. m6we bus master 6 write enable if set, this flag allows bus master 6 to perform writ e operations. if cleared, any attempted write by bus master 6 terminates with an access error and the write is not performed. m5re bus master 5 read enable if set, this flag allows bus master 5 to perform read operations. if cleared, any attempted read by bus master 5 terminates with an access error and the read is not performed. m5we bus master 5 write enable if set, this flag allows bus master 5 to perform writ e operations. if cleared, any attempted write by bus master 5 terminates with an access error and the write is not performed. m4re bus master 4 read enable if set, this flag allows bus master 4 to perform read operations. if cleared, any attempted read by bus master 4 terminates with an access error and the read is not performed. RM0017 memory protection unit (mpu) doc id 14629 rev 8 314/904 m4we bus master 4 write enable if set, this flag allows bus master 4 to perform writ e operations. if cleared, any attempted write by bus master 4 terminates with an access error and the write is not performed. m3pe bus master 3 process identifier enable if set, this flag specifies that the process ident ifier and mask (defined in mpu_rgdn.word3) are to be included in the region hit evaluation. if cleared, then the region hit evaluation does not include the process identifier. m3sm bus master 3 supervisor mode access control this field defines the access controls for bus mast er 3 when operating in supervisor mode. the m3sm field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, ?, x = read and execute allowed, but no write 0b10 r, w, ? = read and write allowed, but no execute 0b11 same access controls as that defined by m3um for user mode m3um bus master 3 user mode access control this field defines the access controls for bus mast er 3 when operating in user mode. the m3um field consists of three independent bits, enabling read, wr ite and execute permissions: {r,w,x}. if set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed. m2pe bus master 2 process identifier enable if set, this flag specifies that the process ident ifier and mask (defined in mpu_rgdn.word3) are to be included in the region hit evaluation. if cleared, then the region hit evaluation does not include the process identifier. m2sm bus master 2 supervisor mode access control this field defines the access controls for bus mast er 2 when operating in supervisor mode. the m2sm field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, ?, x = read and execute allowed, but no write 0b10 r, w, ? = read and write allowed, but no execute 0b11 same access controls as that defined by m2um for user mode m2um bus master 2 user mode access control this field defines the access controls for bus mast er 2 when operating in user mode. the m2um field consists of three independent bits, enabling read, wr ite and execute permissions: {r,w,x}. if set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed. m1pe bus master 1 process identifier enable if set, this flag specifies that the process ident ifier and mask (defined in mpu_rgdn.word3) are to be included in the region hit evaluation. if cleared, then the region hit evaluation does not include the process identifier. m1sm bus master 1 supervisor mode access control this field defines the access controls for bus mast er 1 when operating in supervisor mode. the m1sm field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, ?, x = read and execute allowed, but no write 0b10 r, w, ? = read and write allowed, but no execute 0b11 same access controls as that defined by m1um for user mode table 133. mpu_rgdn.word2 fi eld descriptions (continued) field description memory protection unit (mpu) RM0017 315/904 doc id 14629 rev 8 mpu region descriptor n, word 3 (mpu_rgdn.word3) the fourth word of the mpu region descriptor contains the optional process identifier and mask, plus the region descriptor?s valid bit. since the region descriptor is a 128-bit entity , there are potential coherency issues as this structure is being updated since multiple writes are required to update the entire descriptor. accordingly, the mpu hardware assists in the operation of the descriptor valid bit to prevent incoherent region descriptors from generating spurious access errors. in particular, it is expected that a complete update of a region descriptor is typically done with sequential writes to mpu_rgdn.word0, then mpu_rg dn.word1,... and finally mpu_rgdn.word3. the mpu hardware automatically clears the valid bit on any writes to words {0,1,2} of the descriptor. writes to this word set/clear the valid bit in a normal manner. since it is also expected that system software may adjust only the access controls within a region descriptor (mpu_rgdn.word2) as different tasks execute, an alternate programming view of this 32-bit entity is provided. if only the access controls are being updated, this operation should be performed by writing to mpu_rgdaacn (alternate access control n) as stores to these locations do not affect the descriptor?s valid bit. m1um bus master 1 user mode access control this field defines the access controls for bus mast er 1 when operating in user mode. the m1um field consists of three independent bits, enabling read, wr ite and execute permissions: {r,w,x}. if set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed. m0pe bus master 0 process identifier enable if set, this flag specifies that the process ident ifier and mask (defined in mpu_rgdn.word3) are to be included in the region hit evaluation. if cleared, then the region hit evaluation does not include the process identifier. m0sm bus master 0 supervisor mode access control this field defines the access controls for bus mast er 0 when operating in supervisor mode. the m0sm field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, ?, x = read and execute allowed, but no write 0b10 r, w, ? = read and write allowed, but no execute 0b11 same access controls as that defined by m0um for user mode m0um bus master 0 user mode access control this field defines the access controls for bus mast er 0 when operating in user mode. the m0um field consists of three independent bits, enabling read, wr ite and execute permissions: {r,w,x}. if set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed. table 133. mpu_rgdn.word2 fi eld descriptions (continued) field description RM0017 memory protection unit (mpu) doc id 14629 rev 8 316/904 mpu region descriptor alternate access control n (mpu_rgdaacn) as noted in section mpu region descriptor n, word 2 (mpu_rgdn.word2) , it is expected that since system software may adjust only the access controls within a region descriptor (mpu_rgdn.word2) as different tasks execute, an alternate programming view of this 32- bit entity is desired. if only the access controls are being updated, this operation should be performed by writing to mpu_rgdaacn (alternate access control n) as stores to these locations do not affect th e descriptor?s valid bit. the memory address therefore provides an alternate location for updating mpu_rgdn.word2. figure 138. mpu region descriptor, word 3 register (mpu_rgdn.word3) offset: 0x400 + (16*n) + 0xc (mpu_rgdn.word3) access: read/write 0123456789101112131415 r pid pidmask w reset???????????????? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 00000000 00 0 0 0 vld w reset0000000000000000 table 134. mpu_rgdn.word3 field descriptions field description pid process identifier this field specifies that the optional process identifie r is to be included in t he determination of whether the current access hits in the region descriptor. this field is combined with the pidmask and included in the region hit determination if mpu_rgdn.word2[mxpe] is set. pidmask process identifier mask this field provides a masking capability so that mult iple process identifiers can be included as part of the region hit determinati on. if a bit in the pidmask is set, then the corresponding bit of the pid is ignored in the comparison. this field is combi ned with the pid and included in the region hit determination if mpu_rgdn.word2[mxpe] is set. for more information on the handling of the pid and pidmask, see section access evaluation ? hit determination . vld valid this bit signals the region descriptor is valid. an y write to mpu_rgdn.word{0,1,2} clears this bit, while a write to mpu_rgdn.word3 sets or clears th is bit depending on bit 31 of the write operand. 0 region descriptor is invalid 1 region descriptor is valid memory protection unit (mpu) RM0017 317/904 doc id 14629 rev 8 since the mpu_rgdaacn register is simply another memory mapping for mpu_rgdn.word2, the field definitions shown in ta bl e 1 3 5 are identical to those presented in table 133 . figure 139. mpu rgd alternate access control n (mpu_rgdaacn) offset: 0x800 + (4*n) (mpu_r gdaacn) access: read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r m7re m7we m6re m6we m5re m5we m4re m4we m3pe m3sm m3um m2pe m2sm[1] w reset???????????????? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r m2sm[0] m2um m1pe m1sm m1um m0pe m0sm m0um w reset???????????????? table 135. mpu_rgdaacn field descriptions field description m7re bus master 7 read enable. if set, this flag allows bus master 7 to perform read operations. if cleared, any attempted read by bus master 7 terminates with an access error and the read is not performed. m7we bus master 7 write enable if set, this flag allows bus master 7 to perform wr ite operations. if cleared, any attempted write by bus master 7 terminates with an access e rror and the write is not performed. m6re bus master 6 read enable if set, this flag allows bus master 6 to perform read operations. if cleared, any attempted read by bus master 6 terminates with an access error and the read is not performed. m6we bus master 6 write enable if set, this flag allows bus master 6 to perform wr ite operations. if cleared, any attempted write by bus master 6 terminates with an access e rror and the write is not performed. m5re bus master 5 read enable if set, this flag allows bus master 5 to perform read operations. if cleared, any attempted read by bus master 5 terminates with an access error and the read is not performed. m5we bus master 5 write enable if set, this flag allows bus master 5 to perform wr ite operations. if cleared, any attempted write by bus master 5 terminates with an access e rror and the write is not performed. m4re bus master 4 read enable if set, this flag allows bus master 4 to perform read operations. if cleared, any attempted read by bus master 4 terminates with an access error and the read is not performed. m4we bus master 4 write enable if set, this flag allows bus master 4 to perform wr ite operations. if cleared, any attempted write by bus master 4 terminates with an access e rror and the write is not performed. RM0017 memory protection unit (mpu) doc id 14629 rev 8 318/904 m3pe bus master 3 process identifier enable if set, this flag specifies that the process identifier and mask ( defined in mpu_rgdn.word3) are to be included in the region hit evaluation. if cleared, t hen the region hit evaluation does not include the process identifier. m3sm bus master 3 supervisor mode access control this field defines the access controls for bus master 3 when operating in supervisor mode. the m3sm field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, ?, x = read and execute allowed, but no write 0b10 r, w, ? = read and write allowed, but no execute 0b11 same access controls as that defined by m3um for user mode m3um bus master 3 user mode access control this field defines the access controls for bus mast er 3 when operating in user mode. the m3um field consists of three independent bits, enabling read, write and execute permissions: {r,w,x}. if set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed. m2pe bus master 2 process identifier enable if set, this flag specifies that the process identifier and mask ( defined in mpu_rgdn.word3) are to be included in the region hit evaluation. if cleared, t hen the region hit evaluation does not include the process identifier. m2sm bus master 2 supervisor mode access control this field defines the access controls for bus master 2 when operating in supervisor mode. the m2sm field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, ?, x = read and execute allowed, but no write 0b10 r, w, ? = read and write allowed, but no execute 0b11 same access controls as that defined by m2um for user mode m2um bus master 2 user mode access control this field defines the access controls for bus mast er 2 when operating in user mode. the m2um field consists of three independent bits, enabling read, write and execute permissions: {r,w,x}. if set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed. m1pe bus master 1 process identifier enable if set, this flag specifies that the process identifier and mask ( defined in mpu_rgdn.word3) are to be included in the region hit evaluation. if cleared, t hen the region hit evaluation does not include the process identifier. m1sm bus master 1 supervisor mode access control this 2-bit field defines the access controls for bu s master 1 when operating in supervisor mode. the m1sm field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, ?, x = read and execute allowed, but no write 0b10 r, w, ? = read and write allowed, but no execute 0b11 same access controls as that defined by m1um for user mode table 135. mpu_rgdaacn field descriptions (continued) field description memory protection unit (mpu) RM0017 319/904 doc id 14629 rev 8 18.6 functional description in this section, the functional operation of the mpu is detailed. in particular, subsequent sections discuss the operation of the access evaluation macro as well as the handling of error-terminated bus cycles. 18.6.1 access evaluation macro as previously discussed, the basic operati on of the mpu is performed in the access evaluation macro, a hardware structure replicat ed in the two-dimensional connection matrix. as shown in figure 140 , the access evaluation macro inputs the system bus address phase signals and the contents of a region descriptor (rgdn) and performs two major functions: region hit determination (hit_b) and detection of an access protection violation (error). m1um bus master 1 user mode access control this 3-bit field defines the access controls for bu s master 1 when operating in user mode. the m1um field consists of three independent bits, enabling read , write and execute permissions: {r,w,x}. if set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed. m0pe bus master 0 process identifier enable if set, this flag specifies that the process identifier and mask ( defined in mpu_rgdn.word3) are to be included in the region hit evaluation. if cleared, t hen the region hit evaluation does not include the process identifier. m0sm bus master 0 supervisor mode access control this field defines the access controls for bus master 0 when operating in supervisor mode. the m0sm field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, ?, x = read and execute allowed, but no write 0b10 r, w, ? = read and write allowed, but no execute 0b11 same access controls as that defined by m0um for user mode m0um bus master 0 user mode access control this field defines the access controls for bus mast er 0 when operating in user mode. the m0um field consists of three independent bits, enabling read, write and execute permissions: {r,w,x}. if set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed. table 135. mpu_rgdaacn field descriptions (continued) field description RM0017 memory protection unit (mpu) doc id 14629 rev 8 320/904 figure 140. mpu access evaluation macro figure 140 is not intended to be a schematic of the actual access evaluation macro, but rather a generalized block diagram showing the major functions included in this logic block. access evaluation ? hit determination to evaluate the region hit determination, the mpu uses two magnitude comparators in conjunction with the contents of a region descriptor: the current access must be included between the region's ?start? and ?end? addresses and simultaneously the region's valid bit must be active. recall there are no hardware checks to verify that region's ?end? address is greater then region's ?start? address, and it is software?s re sponsibility to properly load appropriate values into these fields of the region descriptor. in addition to this, the optional process identifier is examined against the region descriptor?s pid and pidmask fields. in order to generate the pid_hit indication: the current pid with its pidmask must be equal to the region's pid wi th its pidmask. also the process identifier enable is take into acc ount in this comparison so that the mpu forces the pid_hit term to be asserted in the case of ahb bus master doesn't provide its process identifier. access evaluation ? privilege violation determination while the access evaluation macro is making the region hit determination, the logic is also evaluating if the current access is allowed by the permissions defined in the region descriptor. the protection violation logic then evaluates the access against the effective permissions using the specification shown in ta b l e 1 3 6 . hit_b start end error > > rgdn system bus hit & error hit_b | error >= <= r,w,x address phase table 136. protection violation definition description inputs output eff_rgd[r] eff_rgd[w] eff_rgd[x] protection violation? inst fetch read ? ? 0 yes, no x permission inst fetch read ? ? 1 no, access is allowed data read 0 ? ? yes, no r permission memory protection unit (mpu) RM0017 321/904 doc id 14629 rev 8 as shown in figure 140 , the output of the protection violation logic is the error signal. the access evaluation macro then uses the hit_b and error signals to form two outputs. the combined (hit_b | error) signal is used to signal the current access is not allowed and (~hit_b & error) is used as the input to mpu_edrn (error detail register) in the event of an error. 18.6.2 putting it all togeth er and ahb error terminations for each xbar slave port being monitored, the mpu performs a reduction-and of all the individual (hit_b | error) terms from each access evaluation macro. this expression then terminates the bus cycle with an error and reports a protection error for three conditions: 1. if the access does not hit in any region descriptor, a protection error is reported. 2. if the access hits in a single region descriptor and that region signals a protection violation, then a protection error is reported. 3. if the access hits in multiple (overlapping) regions and all regions signal protection violations, then a protection error is reported. the third condition reflects that priority is given to permission granting over access denying for overlapping regions as this approach prov ides more flexibility to system software in region descriptor assignments. for an example of the use of overlapping region descriptors, see section 18.8 application information . in event of a protection error, the mpu requires two distinct actions: 1. intercepting the erro r during the address phase (first cycle out of two) and cancelling the transaction before it is seen by the slave device 2. performing the required logic functions to force the standard 2-cycle ahb error response to properly terminate the bus transaction and then providing the right values to the crossbar switch to commit the transaction to other portions of the platform. if, instead, the access is allowed, then the mpu simply passes all ?original? signals to the slave device. in this case, from a functionality point of view, the mpu is fully transparent. 18.7 initialization information the reset state of mpu_cesr[vld] disables the entire module. recall that, while the mpu is disabled, all accesses from all bus masters are allowed. this state also minimizes the power dissipation of the mpu. the power dissipation of each access evaluation macro is minimized when the associated region descriptor is marked as invalid or when mpu_cesr[vld] = 0. typically the appropriate number of region descriptors (mpu_rgdn) is loaded at system startup, including the setting of the mpu_rgdn.word3[vld] bits, before mpu_cesr[vld] data read 1 ? ? no, access is allowed data write ? 0 ? yes, no w permission data write ? 1 ? no, access is allowed table 136. protection violat ion definition (continued) description inputs output eff_rgd[r] eff_rgd[w] eff_rgd[x] protection violation? RM0017 memory protection unit (mpu) doc id 14629 rev 8 322/904 is set, enabling the module. this approach allows all the loaded region descriptors to be enabled simultaneously. recall if a memory reference does not hit in any region descriptor, the attempted access is terminated with an error. 18.8 application information in an operational system, interfacing with the mpu can generally be classified into the following activities: 1. creation of a new memory region requires loading the appropriate region descriptor into an available register location. when a new descriptor is loaded into a rgdn, it would typically be performed using four 32-bit word writes. as discussed in section mpu region descriptor n, word 3 (mpu_rgdn.word3) , the hardware assists in the maintenance of the valid bit, so if this approach is followed, there are no coherency issues associated with the multi-cycle descriptor writes. deletion/removal of an existing memory region is performed simply by clearing mpu_rgdn.word3[vld]. 2. if only the access rights for an existing region descriptor need to change, a 32-bit write to the alternate version of the access control word (mpu_rgdaacn) would typically be performed. recall writes to the region descriptor using this alternate access control location do not affect the valid bit, so there are, by definition, no coherency issues involved with the update. the access rights associated with the memory region switch instantaneously to the new value as the ips write completes. 3. if the region?s start and end addresses are to be changed, this would typically be performed by writing a minimum of three words of the region descriptor: mpu_rgdn.word{0,1,3}, where the writes to word0 and word1 redefine the start and end addresses respectively and the write to word3 re-enables the region descriptor valid bit. in many situations, all four words of the region descriptor would be rewritten. 4. typically, references to the mpu?s programming model would be restricted to supervisor mode accesses from a specific processor(s), so a region descriptor would be specifically allocated for this purpose with attempted accesses from other masters or while in user mode terminated with an error. when the mpu detects an access error, the current bus cycle is terminated with an error response and information on the faulting reference captured in the mpu_earn and mpu_edrn registers. the error-terminated bus cycle typically initiates some type of error response in the originating bu s master. for example, the cp u errors will generate a core exception, whereas the dma erro rs will generate a mpu (external) interrupt. it is important to highlight that in ca se of dma access violat ions the core will continue to run, but if a core violation occurs the system will stop. in any ev ent, the processor can retrieve the captured error address and detail information simply be reading the mpu_e{a,d}rn registers. information on which error registers contain captured fault data is signaled by mpu_cesr[sperr]. system integration un it lite (siul) RM0017 323/904 doc id 14629 rev 8 19 system integration unit lite (siul) 19.1 introduction this chapter describes the system integrati on unit lite (siul), which is used for the management of the pads and their configuration. it controls the multiplexing of the alternate functions used on all pads as well as being responsible for the management of the external interrupts to the device. 19.2 overview the system integration unit lite (siul) controls the mcu pad configuration, ports, general- purpose input and output (gpio) signals and external interrupts with trigger event configuration. figure 141 provides a block diagram of the siul and its interfaces to other system components. the module provides the capabilit y to configure, read, and wr ite to the device?s general- purpose i/o pads that can be configured as either inputs or outputs. when a pad is configured as an input, the state of the pad (logic high or low) is obtained by reading an associated data input register. when a pad is configured as an output, the value driven onto the pad is determined by writing to an associated data output register. enabling the input buffers when a pad is configured as an output allows the actual state of the pad to be read. to enable monitoring of an output pad value, the pad can be configured as both output and input so the actual pad value can be read back and compared with the expected value. RM0017 system integration unit lite (siul) doc id 14629 rev 8 324/904 figure 141. system integration unit lite block diagram ips bus data pad input io interrupt interrupt controller ips master - configuration - glitch filter pad configuration (iomuxc) pad config (pcrs) gpio functionality 123 (1) 123 (1) 123 (1) 16 (2) 2 mux pads 123 (1) siul module interrupt functionality notes: 1. up to 123 i/o pins in 144-pin and 208-pin pack ages; up to 79 i/o pins in 100-pin packages 2. up to 16 i/o pins in 144-pin and 208-pin packages; up to 12 i/o pins in 100-pin packages system integration un it lite (siul) RM0017 325/904 doc id 14629 rev 8 19.3 features the system integration unit lite supports these distinctive features: gpio ? gpio function on up to 123 i/o pins ? dedicated input and output registers for most gpio pins (n) external interrupts ? 2 system interrupt vectors fo r up to 16 interrupt sources ? 16 programmable digital glitch filters ? independent interrupt mask ? edge detection system configuration ? pad configuration control 19.4 external signal description most device pads support multiple device functions. pad configuration registers are provided to enable selection between gpio and other signals. these other signals, also referred to as alternate functions, are typically peripheral functions. gpio pads are grouped in ?ports?, with each port containing up to 16 pads. with appropriate configuration, all pins in a port can be read or written to in parallel with a single r/w access. note: in order to use gpio port functionality, all pads in the port must be configured as gpio rather than as alternate functions. table 137 lists the external pins configurable via the siul. ( n. some device pins, e.g., analog pins, do not have both input and output functionality. table 137. siul signal properties gpio[0:122] (1) category 1. gpio[0:122] in 144-pin lqfp and lbga208; gpio[0:78] in 100-pin lqfp name i/o direction function system configuration gpio [0:19] [26:47] [60:122] input/o utput general-purpose input/output gpio [20:25] [48:59] input analog precise channels, low power oscillator pins external interrupt eirq[0:15] (2) 2. eirq[12:15] available only in 144-pin lqfp input pins with external interrupt request functionality. please see the signal description chapter of this reference manual for details. RM0017 system integration unit lite (siul) doc id 14629 rev 8 326/904 19.4.1 detailed signal descriptions general-purpose i/o pins (gpio[0:122]) the gpio pins provide general-purpose inpu t and output function. the gpio pins are generally multiplexed with other i/o pin functions. each gpio input and output is separately controlled by an input (gpdi n_n ) or output (gpdo n_n ) register. external interrupt request input pins (eirq[0:15]) (o) the eirq[0:15] pins are connected to the siul inputs. rising- or falling-edge events are enabled by setting the corresponding bits in the siul_ireer or the siul_ifeer register. o. eirq[0:15] in 144-pin lqfp and lbga208 pac kages; eirq[0:11] in the 100-pin lqfp system integration un it lite (siul) RM0017 327/904 doc id 14629 rev 8 19.5 memory map and register description this section provides a detailed description of all registers accessible in the siul module. 19.5.1 siul memory map table 138 gives an overview of the siul registers implemented. table 138. siul memory map base address: 0xc3f9_0000 address offset register location 0x0000 reserved 0x0004 mcu id register #1 (midr1) on page 19-329 0x0008 mcu id register #2 (midr2) on page 19-330 0x000c?0x0013 reserved 0x0014 interrupt status flag register (isr) on page 19-331 0x0018 interrupt request enable register (irer) on page 19-332 0x001c?0x0027 reserved 0x0028 interrupt rising-edge event enable register (ireer) on page 19-332 0x002c interrupt falling-edge event enable register (ifeer) on page 19-333 0x0030 interrupt filter enable register (ifer) on page 19-334 0x0034?0x003f reserved 0x0040?0x0134 pad configuration registers (pcr0?pcr122) (1) on page 19-335 0x0136?0x04ff reserved 0x0500?0x051c pad selection for multiplexed inputs registers (psmi0_3? psmi28_31) on page 19-337 0x0520?0x05ff reserved 0x0600?0x06 7 8 gpio pad data output registers (gpdo0_3? gpdo120_123) (2),(3) on page 19-340 0x067c?0x07ff reserved 0x0800?0x0878 gpio pad data input registers (gpdi0_3?gpdi120_123) (2),(4) on page 19-341 0x087c?0x0bff reserved 0x0c00?0x0c0c parallel gpio pad data out registers (pgpdo0 ? pgpdo3) on page 19-341 0x0c10?0x0c3f reserved 0x0c40?0x0c4c parallel gpio pad data in registers (pgpdi0 ? pgpdi3) on page 19-342 0x0c50?0x0c7f reserved 0x0c80?0x0c9c masked parallel gpio pad data out register (mpgpdo0? mpgpdo7) on page 19-343 0x0ca0?0x0fff reserved RM0017 system integration unit lite (siul) doc id 14629 rev 8 328/904 note: a transfer error will be issued when trying to access comp letely reserved register space. 19.5.2 register protection individual registers in system integration unit lite can be protected from accidental writes using the register protection module. the following registers can be protected: interrupt request enable register (irer) interrupt rising-edge event enable register (ireer) interrupt falling-edge event enable register (ifeer) interrupt filter enable register (ifer), pad configuration registers (pcr0?pcr122). note that only the following registers can be protected: ? pcr[0:15] (port a) ? pcr[16:19] (port b[0:3]) ? pcr[34:47] (port c[2:15]) pad selection for multiplexed inputs registers (psmi0_3?psmi28_31) interrupt filter maximum counter registers (ifmc0?ifmc15). note that only ifmc[0:15] can be protected. interrupt filter clock prescaler register (ifcpr) see the ?register under protection? appendix for more details. 19.5.3 register descriptions mcu id register #1 (midr1) this register holds identification information about the device. 0x1000?0x103c interrupt filter maximum counter registers (ifmc0? ifmc15) (5) on page 19-344 0x1040?0x107c reserved 0x1080 interrupt filter clock prescaler register (ifcpr) on page 19-345 0x1084?0x3fff reserved 1. pcr[0:122] is valid in the 144-pin lqfp and the lbga208 packages, while in the 100-pin lqfp packages is pcr[0:78], so all the remaining registers are reserved. 2. not all registers are used. the regist ers, although byte-accessible are alloca ted on 32-bit boundaries. there are some unused registers at the end of the space. the number of unused registers is furt her reduced in packages with reduced gpio pin count. 3. gpdo[0:123] is valid in the 144-pin lqfp and the lb ga208 packages, while in th e 100-pin lqfp packages is gpdo[0:76], so all the remaining registers are reserved. 4. gpdi[0:123] is valid in the 144-pin lqfp and the lbga208 packages, while in the 100-pin lq fp packages is gpdi[0:76], so all the remaining registers are reserved. 5. ifmc[0:15] is valid in the 144-pin lqfp and the lbga208 packages, while in the 100-pin lqfp packages is ifmc[0:11], so all the remaining registers are reserved. table 138. siul memory map (continued) base address: 0xc3f9_0000 address offset register location system integration un it lite (siul) RM0017 329/904 doc id 14629 rev 8 figure 142. mcu id register #1 (midr1) offset: 0x0004 access: read 0123456789101112131415 r partnum[15:0] w reset0101011000000100 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r csp pkg 0 0 major_mask minor_mask w reset0011010000000000 table 139. midr1 field descriptions field description partnum[15:0] mcu part number, lower 16 bits device part number of the mcu. 0101_0110_0000_0001:128 kb 0101_0110_0000_0010: 256 kb 0101_0110_0000_0011: 320/384 kb 0101_0110_0000_0100: 512 kb for the full part number this field needs to be combined with midr2[partnum[23:16]]. csp always reads back 0 pkg package settings can be read by software to determine the pack age type that is used for the particular device as described below. any values not explicitly specified are reserved. 0b00001: 64-pin lqfp 0b01001: 100-pin lqfp 0b01101: 144-pin lqfp major_mask major mask revision counter starting at 0x0. incremented each time there is a resynthesis. minor_mask minor mask revision counter starting at 0x0. incremented each time a mask change is done. RM0017 system integration unit lite (siul) doc id 14629 rev 8 330/904 mcu id register #2 (midr2) interrupt status flag register (isr) this register holds the interrupt flags. figure 143. mcu id register #2 (midr2) offset: 0x0008 access: read 0123456789101112131415 r sf flash_size_1 flash_size_2 0 0 0 0 0 0 0 w reset1010100000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r partnum[23:16] 0 0 0 ee 0 0 0 0 w reset01000010/100010 (1) 1. static bit fixed in hardware 0 (1) 0 (1) 0 table 140. midr2 field descriptions field description sf manufacturer 0 reserved 1st flash_size_1 coarse granularity for flash memory size total flash memory size = flash_size_1 + flash_size_2 0011 128 kb 0100 256 kb 0101 512 kb flash_size_2 fine granularity for flash memory size total flash memory size = flash_size_1 + flash_size_2 0000 0 x (flash_size_1 / 8) 0010 2 x (flash_size_1 / 8) 0100 4 x (flash_size_1 / 8) partnum [23:16] mcu part number, upper 8 bits containing the ascii character within the mcu part number 0x42h: character ?b? (body controller) 0x43h: character ?c? (gateway) for the full part number this field needs to be combined with midr1[partnum[15:0]]. ee data flash present 0 no data flash is present 1 data flash is present system integration un it lite (siul) RM0017 331/904 doc id 14629 rev 8 figure 144. interrupt status flag register (isr) offset: 0x0014 access: user read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eif[15:0] (1) 1. eif[15:0] in 144-pin lqfp and the lbga20 8 packages; eif[11:0] in 100-pin lqfp package. ww1c reset0000000000000000 table 141. isr field descriptions field description eif[x] external interrupt status flag x this flag can be cleared only by writing a ?1?. writing a ?0? has no effect. if enabled (irer[x]), eif[x] causes an interrupt request. 0 no interrupt event has occurred on the pad 1 an interrupt event as defined by ireer[x] and ifeer[x] has occurred RM0017 system integration unit lite (siul) doc id 14629 rev 8 332/904 interrupt request enable register (irer) this register is used to enable the interrupt messaging to the interrupt controller. interrupt rising-edge event enable register (ireer) this register is used to enable rising-edge triggered events on the corresponding interrupt pads. figure 145. interrupt request enable register (irer) offset: 0x0018 access: user read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ire[15:0] (1) 1. ire[15:0] in 144-pin lqfp and the lbga208 packages; ire[11:0] in 100-pin lqfp package. w reset0000000000000000 table 142. irer field descriptions field description ire[x] external interrupt request enable x 0 interrupt requests from the corres ponding isr[eif[x]] bit are disabled. 1 interrupt requests from the corres ponding isr[eif[x]] bit are enabled. figure 146. interrupt rising-edge event enable register (ireer) offset:0x0028 access: user read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r iree[15:0] (1) 1. iree[15:0] in 144-pin lqfp and lbga208 packages; iree[11:0] in 100-pin lqfp package. w reset0000000000000000 system integration un it lite (siul) RM0017 333/904 doc id 14629 rev 8 interrupt falling-edge event enable register (ifeer) this register is used to enab le falling-edge triggere d events on the corresponding interrupt pads. note: if both the ireer[iree] and ifeer[ifee] bits are cleared for the same interrupt source, the interrupt status flag for the co rresponding external interrupt will never be set. if ireer[iree] and ifeer[ifee] bits are set for the same source the interrupts are triggered by both rising edge events and falling edge events. table 143. ireer field descriptions field description iree[x] enable rising-edge events to cause the isr[eif[x]] bit to be set. 0 rising-edge event is disabled 1 rising-edge event is enabled figure 147. interrupt falling-edge event enable register (ifeer) offset:0x002c access: user read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ifee[15:0] (1) 1. ifee[15:0] in 144-pin lqfp and lbga208 pa ckages; ifee[11:0] in 100-pin lqfp package. w reset0000000000000000 table 144. ifeer field descriptions field description ifee[x] enable falling-edge events to caus e the isr[eif[x]] bit to be set. 0 falling-edge event is disabled 1 falling-edge event is enabled RM0017 system integration unit lite (siul) doc id 14629 rev 8 334/904 interrupt filter enable register (ifer) this register is used to enable a digital filter counter on the corresponding interrupt pads to filter out glitches on the inputs. pad configuration registers (pcr0?pcr122) the pad configuration registers allow configuration of the static electrical and functional characteristics associated with i/o pads. each pcr controls the characteristics of a single pad. please note that input and output peripheral muxing are separate. for output pads: ? select the appropriate alternate function in pad config register (pcr) ? obe is not required for functions other than gpio for input pads: ? select the feature location from psmi register ? set the ibe bit in the appropriate pcr for normal gpio (not alternate function): ? configure pcr ? read from gpdi or write to gpdo figure 148. interrupt filter enable register (ifer) offset:0x0030 access: user read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ife[15:0] (1) 1. ife[15:0] in 144-pin lqfp and lbga208 packages; ife[11:0] in 100-pin lqfp package. w reset0000000000000000 table 145. ifer field descriptions field description ife[x] enable digital glitch filter on the interrupt pad input 0 filter is disabled 1 filter is enabled see the ifmc field descriptions in ta b l e 1 5 6 for details on how the filter works. system integration un it lite (siul) RM0017 335/904 doc id 14629 rev 8 note: 16/32-bit access is supported. in addition to the bit map above, the following ta bl e 1 4 7 describes the pcr depending on the pad type (pad types are defined in the ?pad types? section of this reference manual). the bits in shaded fields are not implemented for the particular i/o type. the pa field selecting the number of alternate functions may or may not be present depending on the number of alternate functions actually mapped on the pad. figure 149. pad configur ation registers (pcrx) offsets: base + 0x0040 (pcr0)(123 registers) base + 0x0042 (pcr1) ... base + 0x0130 (pcr122) access: user read/write 0123456789101112131415 r0 smc apc pa[1:0] obe ibe 00 ode 00 src wpe wps w reset 0 0 (1) 1. smc and pa[1] are ?1? for jtag pads 000 (1) 00 (2) 2. obe is ?1? for tdo 0 (3) 3. ibe and wpe are ?1? for tck, tms, tdi, fab and abs 0000000 (3) 1 (4) 4. wps is ?0? for input only pad with analog feature and fab table 146. pcr bit implementation by pad type pad type pcr bit no. 0123456789101112131415 s, m, f (pad with gpio and digital alternate function) smc apc pa[1:0] obe ibe ode src wpe wps j (pad with gpio and analog functionality) smc apc pa[1:0] obe ibe ode src wpe wps i (pad dedicated to adc) smc apc pa[1:0] obe ibe ode src wpe wps table 147. pcrx field descriptions field description smc safe mode control. this bit supports the overriding of the automati c deactivation of the output buffer of the associated pad upon entering safe mode of the device. 0 in safe mode, the output buffer of the pad is disabled. 1 in safe mode, the output buffer remains functional. RM0017 system integration unit lite (siul) doc id 14629 rev 8 336/904 apc analog pad control. this bit enables the usage of the pad as analog input. 0 analog input path from the pad is gated and cannot be used 1 analog input path switch can be enabled by the adc pa[1:0] pad output assignment this field is used to select the function that is allowed to drive the output of a multiplexed pad. 00 alternative mode 0 ? gpio 01 alternative mode 1 ? see the signal description chapter 10 alternative mode 2 ? see the signal description chapter 11 alternative mode 3 ? see the signal description chapter note: number of bits depends on the actual nu mber of actual alternate functions. please see datasheet. obe output buffer enable this bit enables the output buffer of the pad in case the pad is in gpio mode. 0 output buffer of the pad is disabled when pa[1:0] = 00 1 output buffer of the pad is enabled when pa[1:0] = 00 ibe input buffer enable this bit enables the input buffer of the pad. 0 input buffer of the pad is disabled 1 input buffer of the pad is enabled ode open drain output enable this bit controls output driver configuration fo r the pads connected to this signal. either open drain or push/pull driver configurations can be se lected. this feature applies to output pads only. 0 pad configured for push/pull output 1 pad configured for open drain src slew rate control this field controls the slew rate of the associated pad when it is slew rate selectable. its usage is the following: 0 pad configured as slow (default) 1 pad is configured as medium or fast (depending on the pad) note: pc[1] (tdo pad) is medium only. by def ault src = 0, and writing ?1? has no effect. wpe weak pull up/down enable this bit controls whether the weak pull up/d own devices are enabled/disabled for the pad connected to this signal. 0 weak pull device disabled for the pad 1 weak pull device enabled for the pad wps weak pull up/down select this bit controls whether weak pull up or weak pull down devices are used for the pads connected to this signal when weak pull up/down devices are enabled. 0 weak pull-down selected 1 weak pull-up selected table 147. pcrx field descriptions (continued) field description system integration un it lite (siul) RM0017 337/904 doc id 14629 rev 8 pad selection for multiplexed inputs registers (psmi0_3?psmi28_31) in some cases, a peripheral input signal can be selected from more than one pin. for example, the can1_rxd signal can be selected on three different pins: pc[3], pc[11] and pf[15]. only one can be active at a time. to select the pad to be used as input to the peripheral: select the signal via the pad?s pcr register using the pa field. specify the pad to be used via the appropriate psmi field. in order to multiplex different pads to the same peripheral input, the siul provides a register that controls the selection between the different sources. figure 150. pad selection for mult iplexed inputs register (psmi0_3) offsets:0x0500?0x051c (8 registers) access: user read/write 0123456789101112131415 r0000 padsel0 0000 padsel1 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000 padsel2 0000 padsel3 w reset0000000000000000 table 148. psmi0_3 field descriptions field description padsel0?3, padsel4?7, ... padsel28?31 pad selection bits each padsel field selects the pad currently used for a certain input function. see table 149 . RM0017 system integration unit lite (siul) doc id 14629 rev 8 338/904 table 149. peripheral input pin selection psmi registers padsel fields siul address offset function / peripheral mapping (1) psmi0_3 padsel0 0x500 can1rx / flexcan_1 00: pcr[35] 01: pcr[43] 10: pcr[95] (2) padsel1 0x501 can2rx / flexcan_2 00: pcr[73] 01: pcr[89] (2) padsel2 0x502 can3rx / flexcan_3 00: pcr[36] 01: pcr[73] 10: pcr[89] (2) padsel3 (3) 0x503 can4rx / flexcan_4 00: pcr[35] 01: pcr[43] 10: pcr[95] (2) psmi4_7 padsel4 (3) 0x504 can5rx / flexcan_5 00: pcr[64] 01: pcr[97] (2) padsel5 0x505 sck_0 / dspi_0 00: pcr[14] 01: pcr[15] padsel6 0x506 cs0_0 / dspi_0 00: pcr[14] 01: pcr[15] 10: pcr[27] padsel7 0x507 sck_1 / dspi_1 00: pcr[34] 01: pcr[68] 10: pcr[114] (2) psmi8_11 padsel8 0x508 sin_1 / dspi_1 00: pcr[36] 01: pcr[66] 10: pcr[112] (2) padsel9 0x509 cs0_1 / dspi_1 00: pcr[435] 01: pcr[61] 10: pcr[69] 11: pcr[115] (2) padsel10 0x50a sck_2 / dspi_2 00: pcr[46] 01: pcr[78] (2) 10: pcr[105] (2) padsel11 0x50b sin_2 / dspi_2 00: pcr[44] 01: pcr[76] psmi12_15 padsel12 0x50c cs0_2 / dspi_2 00: pcr[47] 01: pcr[79] (2) 10: pcr[82] (2) 11: pcr[104] (2) padsel13 0x50d e1uc[3] / emios_0 00: pcr[3] 01: pcr[27] padsel14 0x50e e0uc[4] / emios_0 00: pcr[4] 01: pcr[28] padsel15 0x50f e0uc[5] / emios_0 00: pcr[5] 01: pcr[29] system integration un it lite (siul) RM0017 339/904 doc id 14629 rev 8 psmi16_19 padsel16 0x510 e0uc[6] / emios_0 00: pcr[6] 01: pcr[30] padsel17 0x511 e0uc[7] / emios_0 00: pcr[7] 01: pcr[31] padsel18 0x512 e0uc[10] / emios_0 00: pcr[10] 01: pcr[80] (2) padsel19 0x513 e0uc[11] / emios_0 00: pcr[11] 01: pcr[81] (2) psmi20_23 padsel20 0x514 e0uc[12] / emios_0 00: pcr[44] 01: pcr[82] (2) padsel21 0x515 e0uc[13] / emios_0 00: pcr[45] 01: pcr[83] (2) padsel22 0x516 e0uc[14] / emios_0 00: pcr[46] 01: pcr[84] (2) padsel23 0x517 e0uc[22] / emios_0 00: pcr[70] 01: pcr[72] 10: pcr[85] (2) psmi24_27 padsel24 0x518 e0uc[23] / emios_0 00: pcr[71] 01: pcr[73] 10: pcr[86] (2) padsel25 (4) 0x519 e0uc[24] / emios_0 00: pcr[60] 01: pcr[106] (2) padsel26 (4) 0x51a e0uc[25] / emios_0 00: pcr[61] 01: pcr[107] (2) padsel27 (4) 0x51b e0uc[26] / emios_0 00: pcr[62] 01: pcr[108] (2) psmi28_31 padsel28 (4) 0x51c e0uc[27] / emios_0 00: pcr[63] 01: pcr[109] (2) padsel29 0x51d scl / f_0 00: pcr[11] 01: pcr[19] padsel30 0x51e sda / i2c__0 00: pcr[10] 01: pcr[18] padsel31 0x51f lin3rx / linflex_3 00: pcr[8] 01: pcr[75] 1. see the signal description chapter of this re ference manual for correspondence between pcr and pinout 2. not available in 100-pin lqfp 3. available only on spc560b50b2 devices 4. not available on spc560b40l3 devices table 149. peripheral input pin selection (continued) psmi registers padsel fields siul address offset function / peripheral mapping (1) RM0017 system integration unit lite (siul) doc id 14629 rev 8 340/904 gpio pad data output registers (gpdo0_3?gpdo120_123) these registers are used to set or clear gpio pads. each pad data out bit can be controlled separately with a byte access. caution: toggling several ios at the same time can significantly increase the current in a pad group. caution must be taken to avoid exceeding maximum current thresholds. please see datasheet. gpio pad data input registers (gpdi0_3?gpdi120_123) these registers are used to read the gpio pad data with a byte access. figure 151. port gpio pad data output register 0?3 (gpdo0_3) offsets: 0x0600?0x06 7 8 (31 registers) access: user read/write 0123456789101112131415 r0000000 pdo[0] 0000000 pdo[1] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000 pdo[2] 0000000 pdo[3] w reset0000000000000000 table 150. gpdo0_3 field descriptions field description pdo[x] pad data out this bit stores the data to be driven out on the external gpio pad controlled by this register. 0 logic low value is driven on the corresponding gpio pad when the pad is configured as an output 1 logic high value is driven on the corresponding gpio pad when the pad is configured as an output system integration un it lite (siul) RM0017 341/904 doc id 14629 rev 8 parallel gpio pad data out registers (pgpdo0 ? pgpdo3) spc560bx and spc560cx devices ports are constructed such that they contain 16 gpio pins, for example porta[0..15]. parallel port registers for input (pgpdi) and output (pgpdo) are provided to allow a complete port to be written or read in one operation, dependent on the individual pad configuration. writing a parallel pgpdo register directly sets the associated gpdo register bits. there is also a masked parallel port output register allowing the user to determine which pins within a port are written. while very convenient and fast, this approach does have implications regarding current consumption for the device power segment containing the port gpio pads. toggling several gpio pins simultaneously can signif icantly increase current consumption. caution: caution must be taken to avoid exceeding maximum current thresholds when toggling multiple gpio pins simultaneously. please see datasheet. table 152 shows the locations and structure of the pgpdo x registers. figure 152. port gpio pad data input register 0?3 (gpdi0_3) offsets: 0x0800?0x0878 (31 registers) access: user read 0123456789101112131415 r0000000 pdi[0] 0000000 pdi[1] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000 pdi[2] 0000000 pdi[3] w reset0000000000000000 table 151. gpdi0_3 field descriptions field description pdi[x] pad data in this bit stores the value of the exter nal gpio pad associated with this register. 0 value of the data in signal for the corresponding gpio pad is logic low 1 value of the data in signal for the corresponding gpio pad is logic high table 152. pgpdo0 ? pgpdo3 register map offset (1) register field 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x0c00 pgpdo0 port a port b 0x0c04 pgpdo1 port c port d RM0017 system integration unit lite (siul) doc id 14629 rev 8 342/904 it is important to note the bit ordering of the ports in the parallel port registers. the most significant bit of the parallel port register corresponds to the least significant pin in the port. for example in table 152 , the pgpdo0 register contains fields for port a and port b. bit 0 is mapped to port a[0], bit 1 is mapped to port a[1] and so on, through bit 15, which is mapped to port a[15] bit 16 is mapped to port b[0], bit 17 is mapped to port b[1] and so on, through bit 31, which is mapped to port b[15]. parallel gpio pad data in registers (pgpdi0 ? pgpdi3) the siu_pgpdi registers are similar in operation to the pgpdio registers, described in the previous section ( section parallel gpio pad data out registers (pgpdo0 ? pgpdo3) ) but they are used to read port pins simultaneously. note: the port pins to be read need to be configured as inputs but even if a single pin within a port has ibe set, then you can still r ead that pin using the parallel port register. however, this does mean you need to be very careful. reads of pgpdi registers are equivalent to reading the corresponding gpdi registers but significantly faster since as many as two ports can be read simultaneously with a single 32- bit read operation. table 153 shows the locations and structure of the pgpdi x registers. each 32-bit pgpdi x register contains two 16-bit fields, each fiel d containing the values for a separate port. it is important to note the bit ordering of the ports in the parallel port registers. the most significant bit of the parallel port register corresponds to the least significant pin in the port. 0x0c08 pgpdo2 port e port f 0x0c0c pgpdo3 port g port h 1. siu base address is 0xc3f9_0000. to calcul ate register address add offset to base address table 152. pgpdo0 ? pgpdo3 register map (continued) offset (1) register field 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 table 153. pgpdi0 ? pgpdi3 register map offset (1) 1. siu base address is 0xc3f9_0000. to calcul ate register address add offset to base address register field 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x0c40 pgpdi0 port a port b 0x0c44 pgpdi1 port c port d 0x0c48 pgpdi2 port e port f 0x0c4c pgpdi3 port g port h system integration un it lite (siul) RM0017 343/904 doc id 14629 rev 8 for example in table 153 , the pgpdi0 register contains fields for port a and port b. bit 0 is mapped to port a[0], bit 1 is mapped to port a[1] and so on, through bit 15, which is mapped to port a[15] bit 16 is mapped to port b[0], bit 17 is mapped to port b[1] and so on, through bit 31, which is mapped to port b[15]. masked parallel gpio pad data ou t register (mpgpdo0?mpgpdo7) the mpgpdo x registers are similar in operation to the pgpdo x ports described in section parallel gpio pad data out registers (pgpdo0 ? pgpdo3) , but with two significant differences: the mpgpdo x registers support masked port-wide changes to the data out on the pads of the respective port. masking effectively allows selective bitwise writes to the full 16-bit port. each 32-bit mpgpdo x register is associated to only one port. note: the mpgpdox registers may only be accessed with 32-bit writes. 8-bi t or 16-bit writes will not modify any bits in the register and will ca use a transfer error response by the module. read accesses return ?0?. table 154 shows the locations and structure of the mpgpdo x registers. each 32-bit mpgpdo x register contains two 16-bit fields (mask x and mppdo x ). the mask field is a bitwise mask for its associated port. the mppdo0 field contains the data to be written to the port. it is important to note the bit ordering of the ports in the parallel port registers. the most significant bit of the parallel port register corresponds to the least significant pin in the port. for example in table 154 , the mpgpdo0 register contai ns field mask0, which is the bitwise mask for port a and field mppdo0, which contains data to be written to port a. mpgpdo0[0] is the mask bit for port a[0], mpgpdo0[1] is the mask bit for port a[1] and so on, through mpgpdo0[15], which is the mask bit for port a[15] mpgpdo0[16] is the data bit mapped to port a[0], mpgpdo0[17] is mapped to port a[1] and so on, through mpgpdo0[31], which is mapped to port a[15]. table 154. mpgpdo0 ? mpgpdo7 register map offset (1) 1. siu base address is 0xc3f9_0000. to calcul ate register address add offset to base address register field 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x0c80 mpgpdo0 mask0 (port a) mppdo0 (port a) 0x0c84 mpgpdo1 mask1 (port b) mppdo1 (port b) 0x0c88 mpgpdo2 mask2 (port c) mppdo2 (port c) 0x0c8c mpgpdo3 mask3 (port d) mppdo3 (port d) 0x0c90 mpgpdo4 mask4 (port e) mppdo4 (port e) 0x0c94 mpgpdo5 mask5 (port f) mppdo5 (port f) 0x0c98 mpgpdo6 mask6 (port g) mppdo6 (port g) 0x0c9c mpgpdo7 mask7 (port h) mppdo7 (port h) RM0017 system integration unit lite (siul) doc id 14629 rev 8 344/904 caution: toggling several ios at the same time can significantly increase the current in a pad group. caution must be taken to avoid exceeding maximum current thresholds. please see datasheet. interrupt filter maximum counter registers (ifmc0?ifmc15) these registers are used to configure the filter counter associated with each digital glitch filter. note: for the pad transition to trigger an interrupt it must be steady for at least the filter period. table 155. mpgpdo0..mpgpdo7 field descriptions field description mask x [15:0] mask field each bit corresponds to one data bit in the mppdo x register at the same bit location. 0 associated bit value in the mppdo x field is ignored 1 associated bit value in the mppdo x field is written mppdo x [15:0] masked parallel pad data out write the data register that stores the value to be driven on the pad in output mode. accesses to this register location are coherent with accesses to the bitwise gpio pad data output registers (gpdo0_3?gpdo120_123). the x and bit index define which mppdo register bit is equivalent to which pdo register bit according to the following equation: mppdo[x][y] = pdo[(x*16)+y] figure 153. interrupt filter maximum counter registers (ifmc0?ifmc15) offset: 0x1000?0x103c) (16 regist ers) access: user read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000000 maxcntx w reset0000000000000000 system integration un it lite (siul) RM0017 345/904 doc id 14629 rev 8 interrupt filter clock prescaler register (ifcpr) this register is used to configure a clock prescaler which is used to select the clock for all digital filter counters in the siul. table 157. ifcpr field descriptions 19.6 functional description 19.6.1 pad control the siul controls the configuration and electrical characteristic of the device pads. it provides a consistent interface for all pads, both on a by-port and a by-bit basis. the pad configuration registers (pcr n , see section pad configuration registers (pcr0?pcr122) ) table 156. ifmc field descriptions field description maxcntx maximum interrupt filter counter setting filter period = t(ck)*maxcntx + n*t(ck) where (n can be ? 1 to 3) maxcntx can be 0 to 15 t(ck): prescaled filter clock period, whic h is firc clock prescaled to ifcp value t(firc): basic filter clock period: 62.5 ns (f firc = 16 mhz) figure 154. interrupt filter cl ock prescaler register (ifcpr) offsets:0x1080 access: user read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000000 ifcp w reset0000000000000000 field description ifcp interrupt filter clock prescaler setting prescaled filter clock period = t(firc) x (ifcp + 1) t(firc) is the fast internal rc oscillator period. ifcp can be 0 to 15. RM0017 system integration unit lite (siul) doc id 14629 rev 8 346/904 allow software control of the static electrical characteristics of external pins with a single write. these are used to configure the following pad features: open drain output enable slew rate control pull control pad assignment control of analog path switches safe mode behavior configuration 19.6.2 general purpose input and output pads (gpio) the siul manages up to 123 gpio pads orga nized as ports that can be accessed for data reads and writes as 32, 16 or 8-bit (p) . note: ports are organized as groups of 16 gpio pads, with the exception of port j, which has 5. a 32-bit r/w operation accesses two ports simultaneously. a 16-bit operation accesses a full port and an 8-bit access either the upper or lower byte of a port. as shown in figure 155 , all port accesses are identical with each read or write being performed only at a different location to access a different port width. figure 155. data port example arrangement showing configuration for different port width accesses the siul has separate data input (gpdi n_n , see section gpio pad data input registers (gpdi0_3?gpdi120_123) ) and data output (gpdo n_n , see section gpio pad data output registers (gpdo0_3?gpdo120_123) ) registers for all pads, allowing the possibility of reading back an inpu t or output value of a pad directly. this supports the ability to validate what is present on the pad rather than simply confirming the value that was written to the data register by accessing the data input registers. data output registers allow an output pad to be driven high or low (with the option of push- pull or open drain drive). input registers are read-only and reflect the respective pad value. when the pad is configured to use one of its al ternate functions, the data input value reflects the respective value of the pad. if a write operation is performed to the data output register for a pad configured as an alternate function (non-gpio), this write will not be reflected by the pad value until reconfigured to gpio. p. there are exceptions. some pads, e.g ., precision analog pads , are input only. 31 23 siul base+ 0x0c00 15 7 0 siul base+ 15 7 0 siul base+ 15 7 0 siul base+ 70 0x0c03 siul base+ 70 0x0c02 siul base+ 70 0x0c01 siul base+ 70 0x0c00 0x0c02 0x0c00 32-bit access (2 ports) 16-bit access (full port) 16-bit access (full port) 8-bit access (half port) 8-bit access (half port) 8-bit access (half port) 8-bit access (half port) system integration un it lite (siul) RM0017 347/904 doc id 14629 rev 8 the allocation of what input function is connected to the pin is defined by the psmi registers (pcr n , see section pad selection for multiplexed inputs registers (psmi0_3? psmi28_31) ). 19.6.3 external interrupts the siul supports 16 external interrupts, eirq0?eirq15. in the signal description chapter of this reference manual, mapping is shown for external interrupts to pads. the siul supports twointerrupt vectors to the interrupt controller. each vector interrupt has eight external interrupts combined together with the presence of flag generating an interrupt for that vector if enabled. all of the external interrupt pads within a single group have equal priority. see figure 156 for an overview of the external interrupt implementation. figure 156. external interrupt pad diagram 1. this value is valid in the 144-pin lqfp and the 208-pin packages, while there are 12 interrupts in the 100- pin lqfp packages each interrupt can be enabled or disabled independently. this can be performed using the irer. a pad defined as an external interrupt can be configured to recognize interrupts with an active rising edge, an acti ve falling edge or both edges being active. a setting of having both edge events disabled is reserved and should not be configured. the active eirq edge is controlled through the configuration of the registers ireer and ifeer. each external interrupt supports an individual flag which is held in the interrupt status flag register (isr). the bits in the isr[eif] fiel d are cleared by writing a ?1? to them; this prevents inadvertent overwriting of other flags in the register. interrupt controller interrupt vectors eif[15:8] 1 eif[7:0] ire[15:0] 1 pads iree[15:0] 1 interrupt edge enable ifee[15:0] 1 falling rising edge detection glitch filter ife[15:0] 1 maxcount[x] irq glitch filter enable glitch filter counter_n ifcp[3:0] glitch filter prescaler interrupt enable or or irq_15_08 1 irq_07_00 RM0017 system integration unit lite (siul) doc id 14629 rev 8 348/904 19.7 pin muxing for pin muxing, please see the signal description chapter of this reference manual. inter-integrated circuit bus controller module (i 2 c) RM0017 349/904 doc id 14629 rev 8 20 inter-integrated circuit bus controller module (i 2 c) 20.1 introduction 20.1.1 overview the inter-integrated circuit (i 2 c? or iic) bus is a two wire bidirectional serial bus that provides a simple and efficient method of data exchange between devices. it minimizes the number of external connections to devices and does not require an external address decoder. this bus is suitable for applications requ iring occasional communications over a short distance between a number of de vices. it also provides flexib ility, allowing additional devices to be connected to the bus for further expansion and system development. the interface is designed to operate up to 100 kbps in standard mode and 400 kbps in fast mode. the device is capable of operating at higher baud rates, up to a maximum of module clock/20 with reduced bus loading. actual baud rate can be less than the programmed baud rate and is dependent on the scl rise time. scl rise time is dependent on the external pullup resistor value and bus loading. the maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400 pf. 20.1.2 features the i 2 c module has the following key features: compatible with i 2 c bus standard multi-master operation software programmable for one of 256 different serial clock frequencies software selectable acknowledge bit interrupt driven byte-by-byte data transfer arbitration lost interrupt with automatic mode switching from master to slave calling address identification interrupt start and stop signal generation/detection repeated start signal generation acknowledge bit generation/detection bus busy detection features currently not supported: no support for general call address not compliant to ten-bit addressing 20.1.3 block diagram the block diagram of the i 2 c module is shown in figure 157 . RM0017 inter-integrated circuit bus controller module (i 2 c) doc id 14629 rev 8 350/904 figure 157. i 2 c block diagram 20.2 external signal description the inter-integrated circuit (i 2 c) module has two external pins, scl and sda. 20.2.1 scl this is the bidirectional serial clock line (scl) of the module, compatible with the i 2 c-bus specification. 20.2.2 sda this is the bidirectional serial data line (sda) of the module, compatible with the i 2 c-bus specification. 20.3 memory map and register description 20.3.1 module memory map the memory map for the i 2 c module is given below in table 158 . the total address for each register is the sum of the base address for the i 2 c module and the address offset for each register. in/out data shift register address compare sda interrupt clock control start stop arbitration control scl bus_clock i 2 c registers inter-integrated circuit bus controller module (i 2 c) RM0017 351/904 doc id 14629 rev 8 all registers are accessible via 8-bit, 16-bit or 32-bit accesses. however, 16-bit accesses must be aligned to 16-bit boundaries, and 32-bit accesses must be aligned to 32-bit boundaries. as an example, the ibdf register for the frequency divider is accessible by a 16-bit read/write to address base + 0x000, but performing a 16-bit access to base + 0x001 is illegal. 20.3.2 i 2 c bus address register (ibad) this register contains the address the i 2 c bus will respond to when addressed as a slave; note that it is not the address sent on the bus during the address transfer. table 158. i2c memory map base address: 0xffe3_0000 address offset register location 0x0 i 2 c bus address register (ibad) on page 20-351 0x1 i 2 c bus frequency divider register (ibfd) on page 20-352 0x2 i 2 c bus control register (ibcr) on page 20-358 0x3 i 2 c bus status register (ibsr) on page 20-359 0x4 i 2 c bus data i/o register (ibdr) on page 20-360 0x5 i 2 c bus interrupt config register (ibic) on page 20-361 figure 158. i 2 c bus address register (ibad) offset 0x0 access: read/write any time 76543210 r adr 0 w reset00000000 table 159. ibad field descriptions field description adr slave address. specific slave address to be used by the i 2 c bus module. note: the default mode of i 2 c bus is slave mode for an address match on the bus. RM0017 inter-integrated circuit bus controller module (i 2 c) doc id 14629 rev 8 352/904 20.3.3 i 2 c bus frequency divi der register (ibfd) figure 159. i 2 c bus frequency divi der register (ibfd) offset 0x1 access: read/write any time 76543210 r ibc w reset00000000 table 160. ibfd field descriptions field description ibc i-bus clock rate. this field is used to prescale the cl ock for bit rate selection. the bit clock generator is implemented as a prescale divider. the ibc bits ar e decoded to give the tap and prescale values as follows: 7?6 select the prescaled shift register (see table 161 ) 5?3 select the prescaler divider (see table 162 ) 2?0 select the shift register tap point (see ta b l e 1 6 3 ) table 161. i-bus multiplier factor ibc7 ? 6mul 00 01 01 02 10 04 11 reserved table 162. i-bus prescaler divider values ibc5 ? 3 scl2start (clocks) scl2stop (clocks) scl2tap (clocks) tap2tap (clocks) 0002741 0012742 0102964 0116968 100 14171416 101 30333032 110 62656264 111 126 129 126 128 inter-integrated circuit bus controller module (i 2 c) RM0017 353/904 doc id 14629 rev 8 the number of clocks from the falling edge of scl to the first tap (tap[1]) is defined by the values shown in the scl2tap column of table 162 . all subsequent tap points are separated by 2 ibc5-3 as shown in the tap2tap column in table 162 . the scl tap is used to generate the scl period and the sda tap is used to de termine the delay from the falling edge of scl to the change of state of sda i.e. the sda hold time. figure 160. sda hold time table 163. i-bus tap and prescale values ibc2-0 scl tap (clocks) sda tap (clocks) 000 5 1 001 6 1 010 7 2 011 8 2 100 9 3 101 10 3 110 12 4 111 15 4 scl divider sda hold scl sda RM0017 inter-integrated circuit bus controller module (i 2 c) doc id 14629 rev 8 354/904 figure 161. scl divider and sda hold the equation used to generate the divide r values from the ibfd bits is: equation 3 scl divider = mul x {2 x (scl2tap + [(scl_tap -1) x tap2tap] + 2)} the sda hold delay is equal to the cpu cloc k period multiplied by the sda hold value shown in ta b l e 1 6 4 . the equation used to generate the sda hold value from the ibfd bits is: equation 4 sda hold = mul x {scl2tap + [(sda_tap - 1) x tap2tap] + 3} the equation for scl hold values to generate the start and stop conditions from the ibfd bits is: equation 5 scl hold(start) = mul x [scl2start + (scl_tap - 1) x tap2tap] equation 6 scl hold(stop) = mul x [scl2stop + (scl_tap - 1) x tap2tap] sda scl start condition stop condition scl hold(start) scl hold(stop) inter-integrated circuit bus controller module (i 2 c) RM0017 355/904 doc id 14629 rev 8 table 164. i 2 c divider and hold values ibc7 ? 0 (hex) scl divider (clocks) sda hold (clocks) scl hold (start) scl hold (stop) mul = 1 00 20 7 6 11 01 22 7 7 12 02 24 8 8 13 03 26 8 9 14 04 28 9 10 15 05 30 9 11 16 06 34 10 13 18 07 40 10 16 21 08 28 7 10 15 09 32 7 12 17 0a 36 9 14 19 0b 40 9 16 21 0c 44 11 18 23 0d 48 11 20 25 0e 56 13 24 29 0f 68 13 30 35 10 48 9 18 25 11 56 9 22 29 12 64 13 26 33 13 72 13 30 37 14 80 17 34 41 15 88 17 38 45 16 104 21 46 53 17 128 21 58 65 18 80 9 38 41 19 96 9 46 49 1a 112 17 54 57 1b 128 17 62 65 1c 144 25 70 73 1d 160 25 78 81 1e 192 33 94 97 1f 240 33 118 121 20 160 17 78 81 21 192 17 94 97 22 224 33 110 113 23 256 33 126 129 24 288 49 142 145 25 320 49 158 161 26 384 65 190 193 27 480 65 238 241 28 320 33 158 161 29 384 33 190 193 2a 448 65 222 225 2b 512 65 254 257 2c 576 97 286 289 2d 640 97 318 321 2e 768 129 382 385 2f 960 129 478 481 30 640 65 318 321 31 768 65 382 385 32 896 129 446 449 33 1024 129 510 513 34 1152 193 574 577 35 1280 193 638 641 36 1536 257 766 769 37 1920 257 958 961 38 1280 129 638 641 39 1536 129 766 769 3a 1792 257 894 897 3b 2048 257 1022 1025 3c 2304 385 1150 1153 3d 2560 385 1278 1281 3e 3072 513 1534 1537 3f 3840 513 1918 1921 RM0017 inter-integrated circuit bus controller module (i 2 c) doc id 14629 rev 8 356/904 mul = 2 40 40 14 12 22 41 44 14 14 24 42 48 16 16 26 43 52 16 18 28 44 56 18 20 30 45 60 18 22 32 46 68 20 26 36 47 80 20 32 42 48 56 14 20 30 49 64 14 24 34 4a 72 18 28 38 4b 80 18 32 42 4c 88 22 36 46 4d 96 22 40 50 4e 112 26 48 58 4f 136 26 60 70 50 96 18 36 50 51 112 18 44 58 52 128 26 52 66 53 144 26 60 74 54 160 34 68 82 55 176 34 76 90 56 208 42 92 106 57 256 42 116 130 58 160 18 76 82 59 192 18 92 98 5a 224 34 108 114 5b 256 34 124 130 5c 288 50 140 146 5d 320 50 156 162 5e 384 66 188 194 5f 480 66 236 242 60 320 28 156 162 61 384 28 188 194 62 448 32 220 226 63 512 32 252 258 64 576 36 284 290 65 640 36 316 322 66 768 40 380 386 67 960 40 476 482 68 640 28 316 322 69 768 28 380 386 6a 896 36 444 450 6b 1024 36 508 514 6c 1152 44 572 578 6d 1280 44 636 642 6e 1536 52 764 770 6f 1920 52 956 962 70 1280 36 636 642 71 1536 36 764 770 72 1792 52 892 898 73 2048 52 1020 1026 74 2304 68 1148 1154 75 2560 68 1276 1282 76 3072 84 1532 1538 77 3840 84 1916 1922 78 2560 36 1276 1282 79 3072 36 1532 1538 7a 3584 68 1788 1794 7b 4096 68 2044 2050 7c 4608 100 2300 2306 7d 5120 100 2556 2562 7e 6144 132 3068 3074 7f 7680 132 3836 3842 table 164. i 2 c divider and hold values ibc7 ? 0 (hex) scl divider (clocks) sda hold (clocks) scl hold (start) scl hold (stop) inter-integrated circuit bus controller module (i 2 c) RM0017 357/904 doc id 14629 rev 8 mul = 4 80 80 28 24 44 81 88 28 28 48 82 96 32 32 52 83 104 32 36 56 84 112 36 40 60 85 120 36 44 64 86 136 40 52 72 87 160 40 64 84 88 112 28 40 60 89 128 28 48 68 8a 144 36 56 76 8b 160 36 64 84 8c 176 44 72 92 8d 192 44 80 100 8e 224 52 96 116 8f 272 52 120 140 90 192 36 72 100 91 224 36 88 116 92 256 52 104 132 93 288 52 120 148 94 320 68 136 164 95 352 68 152 180 96 416 84 184 212 97 512 84 232 260 98 320 36 152 164 99 384 36 184 196 9a 448 68 216 228 9b 512 68 248 260 9c 576 100 280 292 9d 640 100 312 324 9e 768 132 376 388 9f 960 132 472 484 a0 640 68 312 324 a1 768 68 376 388 a2 896 132 440 452 a3 1024 132 504 516 a4 1152 196 568 580 a5 1280 196 632 644 a6 1536 260 760 772 a7 1920 260 952 964 a8 1280 132 632 644 a9 1536 132 760 772 aa 1792 260 888 900 ab 2048 260 1016 1028 ac 2304 388 1144 1156 ad 2560 388 1272 1284 ae 3072 516 1528 1540 af 3840 516 1912 1924 30 2560 260 1272 1284 b1 3072 260 1528 1540 b2 3584 516 1784 1796 b3 4096 516 2040 2052 b4 4608 772 2296 2308 b5 5120 772 2552 2564 b6 6144 1028 3064 3076 b7 7680 1028 3832 3844 b8 5120 516 2552 2564 b9 6144 516 3064 3076 ba 7168 1028 3576 3588 bb 8192 1028 4088 4100 bc 9216 1540 4600 4612 bd 10240 1540 5112 5124 be 12288 2052 6136 6148 bf 15360 2052 7672 7684 table 164. i 2 c divider and hold values ibc7 ? 0 (hex) scl divider (clocks) sda hold (clocks) scl hold (start) scl hold (stop) RM0017 inter-integrated circuit bus controller module (i 2 c) doc id 14629 rev 8 358/904 20.3.4 i 2 c bus control register (ibcr) figure 162. i 2 c bus control register (ibcr) offset 0x2 access: read/write any time 76543210 r mdis ibie mssl txrx noack 0 dmaen 0 wrsta reset10000000 table 165. ibcr field descriptions field description mdis module disable. this bit controls the software reset of the entire i 2 c bus module. 1 the module is reset and disabled. this is the po wer-on reset situation. when high, the interface is held in reset, but registers can still be accessed. status register bits (ibsr) are not valid when module is disabled. 0 the i 2 c bus module is enabled. this bit must be cleared before any other ibcr bits have any effect note: if the i 2 c bus module is enabled in the middle of a byte transfer, the interface behaves as follows: slave mode ignores the current transfer on the bus and starts operating whenever a subsequent start condition is detec ted. master mode will not be aware that the bus is busy, hence if a start cycle is initiated then the cu rrent bus cycle may become corrupt. this would ultimately result in either t he current bus master or the i 2 c bus module losing arbitration, after which, bus operation would return to normal. ibie i-bus interrupt enable. 1 interrupts from the i 2 c bus module are enabled. an i 2 c bus interrupt occurs provided the ibif bit in the status register is also set. 0 interrupts from the i 2 c bus module are disabled. note that this does not clear any currently pending interrupt condition mssl master/slave mode select. upon rese t, this bit is cleared. when this bit is changed from 0 to 1, a start signal is generated on the bus and the master mode is selected. when this bit is changed from 1 to 0, a stop signal is generated and the operat ion mode changes from master to slave. a stop signal should be generated only if the ibif flag is set. mssl is cleared without generating a stop signal when the master loses arbitration. 1 master mode 0slave mode txrx transmit/receive mode select. this bit selects t he direction of master and slave transfers. when addressed as a slave this bit should be set by softwa re according to the srw bi t in the status register. in master mode this bit should be set according to the type of transfer requir ed. therefore, for address cycles, this bit will always be high. 1transmit 0 receive noack data acknowledge disable. this bit specifies the value driven onto sda during data acknowledge cycles for both master and slave receivers. the i 2 c module will always acknowledge address matches, provided it is enabled, regardless of the value of noack. note that va lues written to this bit are only used when the i 2 c bus is a receiver, not a transmitter. 1 no acknowledge signal response is sent (i.e., acknowledge bit = 1) 0 an acknowledge signal will be sent out to the bus at the 9th clock bit after receiving one byte of data inter-integrated circuit bus controller module (i 2 c) RM0017 359/904 doc id 14629 rev 8 20.3.5 i 2 c bus status register (ibsr) rsta repeat start. writing a 1 to this bit will generate a repeated start condition on the bus, provided it is the current bus master. this bit will always be read as a low. attempting a repeated start at the wrong time, if the bus is owned by another master, will result in loss of arbitration. 1 generate repeat start cycle 0 no effect dmaen dma enable. when this bit is set, the dma tx and rx lines will be asserted when the i 2 c module requires data to be read or written to the data re gister. no transfer done interrupts will be generated when this bit is set, however an interrupt will be g enerated if the loss of arbitration or addressed as slave conditions occur. the dma mode is only valid when the i 2 c module is configured as a master and the dma transfer still requires cpu intervention at the start and the e nd of each frame of data. see the dma application information section for more details. 1 enable the dma tx/rx request signals 0 disable the dma tx/rx request signals figure 163. i 2 c bus status register (ibsr) offset 0x3 access: read-write 76543210 r tcf iaas ibb ibal 0 srw ibif rxak w w1c w1c reset10000000 table 166. ibsr field descriptions field description tcf transfer complete. while one byte of data is being transferred, this bit is cleared. it is set by the falling edge of the 9th clock of a byte transfer. note that th is bit is only valid during or immediately following a transfer to the i 2 c module or from the i 2 c module. 1 transfer complete 0 transfer in progress iaas addressed as a slave. when its own specific addre ss (i-bus address register) is matched with the calling address, this bit is set. the cpu is interr upted provided the ibie is set. then the cpu needs to check the srw bit and set its tx/rx mode accordingly. writing to the i-bus control register clears this bit. 1 addressed as a slave 0 not addressed ibb bus busy. this bit indicates the status of the bus. when a start signal is detected, the ibb is set. if a stop signal is detected, ibb is cleared and the bus enters idle state. 1bus is busy 0 bus is idle table 165. ibcr field descriptions (continued) field description RM0017 inter-integrated circuit bus controller module (i 2 c) doc id 14629 rev 8 360/904 20.3.6 i 2 c bus data i/o register (ibdr) in master transmit mode, when data is written to ibdr, a data transfer is initiated. the most significant bit is sent first. in master receive mode, reading this register initiates next byte data receiving. in slave mode, the same functions are available after an address match has occurred. note that the ibcr[txrx] field must correctly reflect the desired direction of transfer in master and slave modes for the transmission to begin. for instance, if the i 2 c is ibal arbitration lost. the arbitration lost bit (ibal) is se t by hardware when the arbitration procedure is lost. arbitration is lost in the following circumstances: ? sda is sampled low when the master drives a high during an address or data transmit cycle. ? sda is sampled low when the master drives a high during the acknowledge bit of a data receive cycle. ? a start cycle is attempte d when the bus is busy. ? a repeated start cycle is requested in slave mode. ? a stop condition is detected wh en the master did not request it. srw slave read/write. when iaas is set, this bit indica tes the value of the r/w command bit of the calling address sent from the master. this bit is only valid when the i-bus is in slave mode, a complete address transfer has occurred with an address match and no other transfers have been initiated. by programming this bit, the cpu can select slave tr ansmit/receive mode according to the command of the master. 1 slave transmit, master reading from slave 0 slave receive, master writing to slave ibif i-bus interrupt flag. the ibif bit is set w hen one of the following conditions occurs: ? arbitration lost (ibal bit set) ? byte transfer complete (tcf bit set - check w/ design if this is the case (only tcf)) ? addressed as slave (iaas bit set) ? noack from slave (ms & tx bits set) ?i 2 c bus going idle (ibb high-low transition and enabled by biie) a processor interrupt request will be caused if the ibie bit is set. rxak received acknowledge. this is the value of sda during the acknowledge bit of a bus cycle. if the received acknowledge bit (rxak) is low, it indicates an acknowledge signal has been received after the completion of 8 bits data transmission on the bus. if rxak is high, it means no acknowledge signal is detected at the 9th clock. this bit is valid only after transfer is complete. 1 no acknowledge received 0 acknowledge received figure 164. i 2 c bus data i/o register (ibdr) offset 0x4 access: read/write any time 76543210 r data w reset00000000 table 166. ibsr field descriptions (continued) field description inter-integrated circuit bus controller module (i 2 c) RM0017 361/904 doc id 14629 rev 8 configured for master transmit but a master receive is desired, then reading the ibdr will not initiate the receive. reading the ibdr will return the la st byte received while the i 2 c is configured in either master receive or slave receive modes. the ibdr does not reflect every byte that is transmitted on the i 2 c bus, nor can software verify that a byte has been written to the ibdr correctly by reading it back. in master transmit mode, the first byte of data written to ibdr following assertion of ms/sl is used for the address transfer and should co mprise the calling address (in position d7?d1) concatenated with the required r/w bit (in position d0). 20.3.7 i 2 c bus interrupt conf ig register (ibic) 20.4 functional description 20.4.1 i-bus protocol the i 2 c bus system uses a serial data line (sda) and a serial clock line (scl) for data transfer. all devices connected to it must have open drain or open collector outputs. a logical and function is exercised on both lines with external pull-up resistors. the value of these resistors is system dependent. normally, a standard communication is composed of four parts: start signal, slave address transmission, data transfer and stop signal. they are described briefly in the following sections and illustrated in figure 166 . figure 165. i 2 c bus interrupt config register (ibic) offset 0x5 access: read/write any time 76543210 r biie (1) 1. this bit cannot be set in reset state, when i2c is in slave mode. it can be set to 1 only when i2c is in master mode. this information is missing from the spec. 0000000 w reset00000000 table 167. ibic field descriptions field description biie bus idle interrupt enable bit. this config bit can be used to enable the generation of an interrupt once the i 2 c bus becomes idle. once this bit is set, an ibb high-low transition will set the ibif bit. this feature can be used to signal to the cpu the completion of a stop on the i 2 c bus. 1 bus idle interrupts enabled 0 bus idle interrupts disabled RM0017 inter-integrated circuit bus controller module (i 2 c) doc id 14629 rev 8 362/904 figure 166. i 2 c bus transmission signals start signal when the bus is free, i.e. no master device is engaging the bus (both scl and sda lines are at logical high), a master may initiate communication by sending a start signal. as shown in figure 166 , a start signal is defined as a high-to-low transition of sda while scl is high. this signal denotes the beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle states. figure 167. start and stop conditions scl sda start signal ack bit 12345678 msb lsb 12345678 msb lsb stop signal no scl sda 1234567 8 msb lsb 1 2 5 678 msb lsb repeated 34 9 9 ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w xxx d7 d6 d5 d4 d3 d2 d1 d0 calling address read/ data byte ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w new calling address 99 xx ack bit write start signal start signal ack bit calling address read/ write stop signal no ack bit read/ write sda scl start condition stop condition inter-integrated circuit bus controller module (i 2 c) RM0017 363/904 doc id 14629 rev 8 slave address transmission the first byte of data transfer immediately after the start signal is the slave address transmitted by the master. this is a seven-bit calling address followed by a r/w bit. the r/w bit tells the slave the desired direction of data transfer. 1 = read transfer - the slave transmits data to the master 0 = write transfer - the master transmits data to the slave only the slave with a calling address that matc hes the one transmitted by the master will respond by sending back an acknowledge bit. this is done by pulling the sda low at the 9th clock (see figure 166 ). no two slaves in the system may have the same address. if the i 2 c bus is master, it must not transmit an address that is equal to its own slave address. the i 2 c bus cannot be master and slave at the same time. however, if arbitration is lost during an address cycle the i 2 c bus will revert to slave mode and operate corr ectly, even if it is being addressed by another master. data transfer once successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a direction specified by the r/w bit sent by the calling master. all transfers that come after an address cycle ar e referred to as data transfers, even if they carry sub-address information for the slave device. each data byte is 8 bits long. data may be changed only while scl is low and must be held stable while scl is high as shown in figure 166 . there is one clock pulse on scl for each data bit, the msb being transferred first. each data byte must be followed by an acknowledge bit, which is sign alled from the receiving device by pulling the sda low at the ninth clock. therefore, one complete data byte transfer needs nine clock pulses. if the slave receiver does not acknowledge the master, the sda line must be left high by the slave. the master can then generate a stop signal to abort the data transfer or a start signal (repeated start) to commence a new calling. if the master receiver does not acknowledge the slave transmitter after a byte transmission, it means 'end of data' to the slave, so the slave releases the sda line for the master to generate a stop or start signal. stop signal the master can terminate the communication by generating a stop signal to free the bus. however, the master may generate a start si gnal followed by a calling command without generating a stop signal first. this is calle d repeated start. a stop signal is defined as a low-to-high transition of sda wh ile scl is at logical ?1? (see figure 166 ). the master can generate a stop even if the slave has generated an acknowledge, at which point the slave must release the bus. repeated start signal as shown in figure 166 , a repeated start signal is a start signal generated without first generating a stop signal to terminate the communication. this is used by the master to communicate with another slave or with the same slave in different mode (transmit/receive mode) without releasing the bus. RM0017 inter-integrated circuit bus controller module (i 2 c) doc id 14629 rev 8 364/904 arbitration procedure the inter-ic bus is a true multi-master bus that allows more than one master to be connected on it. if two or more masters try to control the bus at the same time, a clock synchronization procedure determines the bus clock, for which the low period is equal to the longest clock low period and the high is equal to the shortest one among the masters. the relative priority of the contending masters is determined by a data arbitration procedure. a bus master loses arbitration if it transmits logic ?1? while another master transmits logic ?0?. the losing masters immediately switch over to slave receive mode and stop driving the sda output. in this case, the transition from master to slave mode does not generate a stop condition. meanwhile, a status bit is set by hardware to indicate loss of arbitration. clock synchronization since wire-and logic is performed on the scl line, a high-to-low transition on the scl line affects all the devices connected on the bus. the devices start counting their low period and once a device's clock has gone low, it holds the scl line low until the clock high state is reached. however, the change of low to high in this device clock may not change the state of the scl line if another device clock is still within its low period. t herefore, synchronized clock scl is held low by the device with th e longest low period. devices with shorter low periods enter a high wait state during this time (see figure 168 ). when all devices concerned have counted off their low period, the synchronized clock scl line is released and pulled high. there is then no difference between the device clocks and the state of the scl line and all the devices start counting their high periods. the first device to complete its high period pulls the scl line low again. figure 168. i 2 c bus clock synchronization handshaking the clock synchronization mechanism can be us ed as a handshake in data transfer. slave devices may hold the scl low after completion of o ne byte transfer (9 bits). in such cases, it halts the bus clock and forces the master clock into wait state until the slave releases the scl line. scl1 scl2 scl internal counter reset wait start counting high period inter-integrated circuit bus controller module (i 2 c) RM0017 365/904 doc id 14629 rev 8 clock stretching the clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. after the master has driven scl low, the slave can drive scl low for the required period and then release it. if the slave scl low period is greater than the master scl low period then the resulting scl bus signal low period is stretched. 20.4.2 interrupts general the i 2 c uses only one interrupt vector. interrupt description there are five types of internal interrupts in the i 2 c. the interrupt service routine can determine the interrupt type by reading the status register. i 2 c interrupt can be generated on arbitration lost condition (ibal bit set) byte transfer condition (tcf bit set and dmaen bit not set) address detect condition (iaas bit set) no acknowledge from slave received when expected bus going idle (ibb bit not set) the i 2 c interrupt is enabled by the ibie bit in the i 2 c control register. it must be cleared by writing ?1? to the ibif bit in the interrupt service routine. the bus going idle interrupt needs to be additionally enabled by the biie bit in the ibic register. 20.5 initialization/app lication information 20.5.1 i 2 c programming examples initialization sequence reset will put the i 2 c bus control register to its default state. before the interface can be used to transfer serial data, an initialization procedure must be carried out, as follows: table 168. interrupt summary interrupt offset vector priority source description i 2 c interrupt ??? ibal, tcf, iaas, ibb bits in ibsr register when any of ibal, tcf or i aas bits is set an interrupt may be caused based on arbitration lost, transfer complete or address detect conditions. if enabled by biie, the deassertion of ibb can also cause an interrupt, indicating that the bus is idle. RM0017 inter-integrated circuit bus controller module (i 2 c) doc id 14629 rev 8 366/904 1. update the frequency divider register (ibfd) and select the required division ratio to obtain scl frequency from system clock. 2. update the i 2 c bus address register (ibad) to define its slave address. 3. clear the ibcr[mdis] field to enable the i 2 c interface system. 4. modify the bits of the i 2 c bus control register (ibcr) to select master/slave mode, transmit/receive mode and interrupt enable or not. optionally also modify the bits of the i 2 c bus interrupt config register (ibic) to further refine the interrupt behavior. generation of start after completion of the initialization procedure, serial data can be transmitted by selecting the 'master transmitter' mode. if the device is connected to a multi-master bus system, the state of the i 2 c bus busy bit (ibb) must be tested to check whether the serial bus is free. if the bus is free (ibb=0), the start condition and the first byte (the slave address) can be sent. the data wri tten to the data register comprises th e slave calling address and the lsb, which is set to indicate the direction of transfer required from the slave. the bus free time (i.e., the time between a stop condition and the following start condition) is built into the hardware that generates the start cycle. depending on the relative frequencies of the system clock and the scl period, it may be necessary to wait until the i 2 c is busy after writing the calling address to the ibdr before proceeding with the following instructions. this is illu strated in the following example. an example of the sequence of events which generates the start signal and transmits the first byte of data (slave address) is shown below: while (bit 5, ibsr ==1)// wait in loop for ibb flag to clear bit4 and bit 5, ibcr = 1// set transmit and master mode, i.e. generate start condition ibdr = calling_address// send the calling address to the data register while (bit 5, ibsr ==0)// wait in loop for ibb flag to be set post-transfer software response transmission or reception of a byte will set th e data transferring bit (tcf) to 1, which indicates one byte communication is finished. the i 2 c bus interrupt bit (ibif) is set also; an interrupt will be generated if the interrupt function is enabled du ring initialization by setting the ibie bit. the ibif (interrupt flag) can be cleared by writing 1 (in the interrupt service routine, if interrupts are used). the tcf bit will be cleared to i ndicate data transfer in progre ss whenever data register is written to in transmit mode, or during reading out from data register in receive mode. the tcf bit should not be used as a data transfer complete flag as the flag timing is dependent on a number of factors including the i 2 c bus frequency. this bit may not conclusively provide an indication of a transfer complete situation. it is recommended that transfer complete situations are detected using the ibif flag software may service the i 2 c i/o in the main program by monitoring the ibif bit if the interrupt function is disabled. note that pollin g should monitor the ibif bit rather than the tcf bit since their operation is di fferent when arbitration is lost. note that when a ?transfer complete? interrupt occurs at the end of the address cycle, the master will always be in transmit mode, i.e. th e address is transmitte d. if master receive mode is required, indicated by r/w bit sent with slave calling address, then the tx/rx bit at master side should be toggled at this stage. if master does not receive an ack from slave, then transmission must be re-initiated or terminated. inter-integrated circuit bus controller module (i 2 c) RM0017 367/904 doc id 14629 rev 8 in slave mode, iaas bit will get set in ibsr if slave address (ibad) matches the master calling address. this is an indi cation that master-slave data communication can now start. during address cycles (i aas=1), the srw bit in the status r egister is read to determine the direction of the subsequent transfer and the tx/rx bit is programmed accordingly. for slave mode data cycles (iaas=0), the srw bit is not valid. the tx/rx bit in the control register should be read to determine the direction of the current transfer. transmit/receive sequence follow this sequence in case of master transmit(address/data): 1. clear ibsr[ibif]. 2. write data in data register (ibdr). 3. ibsr[tcf] bit will get cleared when transfer is in progress. 4. ibsr[tcf] bit will get set when transfer is complete. 5. wait for ibsr[ibif] to get set, then read ibsr register to determine its source: ? tcf = 1 i.e. transfer is complete. ? no acknowledge conditio n (rxak = 1) is found. ? ibb = 0 i.e. bus has transitioned from busy to idle state. ? if ibb = 1, ignore check of arbitration loss (ibal = 1). ? ignore address detect (iaas = 1) for mast er mode (valid on ly for slave mode). 6. check rxak in ibsr for an acknowledge from slave. follow this sequence in case of slave receive(address/data): 1. clear ibsr[ibif]. 2. ibsr[tcf] will get cleared when transfer is in progress for address transfer. 3. ibsr[tcf] will get set when transfer is complete. 4. wait for ibsr[ibif] to get set. then read ibsr register to determine its source: ? address detect has occurred (iaas = 1) - determination of slave mode. 5. clear ibif. 6. wait until ibsr[tcf] bit gets cleared (that is, "transfer under progress" condition is reached for data transfer). 7. wait until ibsr[tcf] bit gets cleared(proof that transfer completes from "transfer under progress" state). 8. wait until ibsr[ibif] bit gets set. to find its source, check if: ? tcf = 1 i.e. reception is complete ? ibsr[ibb] = 0, that is, bus has transitioned from busy to idle state ? ignore arbitration loss (ibal = 1) for ibb = 1 ? ignore no acknowle dge condition (rxak = 1) for receiver 9. read the data register (ibdr) to determine data received from master. sequence followed in case of slave transmit (steps 1?4 of slave receive for address detect, followed by 1?6 of master transmit for data transmit). sequence followed in case of master receive (steps 1?6 of master transmit for address dispatch, followed by 5?8 of slave receive for data receive). RM0017 inter-integrated circuit bus controller module (i 2 c) doc id 14629 rev 8 368/904 generation of stop a data transfer ends with a stop signal generated by the 'master' device. a master transmitter can simply generate a stop signal after all the data has been transmitted. the following is an example showing how a stop condition is generated by a master transmitter. if (tx_count == 0) or// check to see if all data bytes have been transmitted (bit 0, ibsr == 1) {// or if no ack generated clear bit 5, ibcr// generate stop condition } else { ibdr = data_to_transmit// write byte of data to data register tx_count --// decrement counter }// return from interrupt if a master receiver wants to terminate a data transfer, it must inform the slave transmitter by not acknowledging the last byte of data which can be done by setting the transmit acknowledge bit (txak) before re ading the 2nd last byte of da ta. before reading the last byte of data, a stop signal must first be generated. the following is an example showing how a stop signal is generated by a master receiver. rx_count --// decrease the rx counter if (rx_count ==1)// 2nd last byte to be read ? bit 3, ibcr = 1// disable ack if (rx_count == 0)// last byte to be read ? bit 5, ibcr = 0// generate stop signal else data_received = ibdr// read rx data and store generation of repeated start at the end of data transfer, if the master still wants to communicate on the bus, it can generate another start signal followed by another slave address without first generating a stop signal. a program example is as shown. bit 2, ibcr = 1// generate another start ( restart) ibdr == calling_address// transmit the calling address slave mode in the slave interrupt service routine, the module addressed as slave bi t (iaas) should be tested to check if a calling of it s own address has just been rece ived. if iaas is set, software should set the transmit/receive mode select bit (tx/rx bit of ibcr) according to the r/w command bit (srw). writing to the ibcr clears iaas automatically. note that the only time iaas is read as set is from th e interrupt at the end of the address cycle where an address match occurred. interrupts resu lting from subsequent data tr ansfers will have iaas cleared. a data transfer may now be initiated by writin g information to ibdr for slave transmits or dummy reading from ibdr in slave receive mode. the slave will drive scl low in-between byte transfers scl is released when the ibdr is accessed in the required mode. in slave transmitter routine, the received ackno wledge bit (rxak) must be tested before transmitting the next byte of data. setting rxak means an 'end of data' signal from the master receiver, after which it must be switched from transmitter mode to receiver mode by software. a dummy read then releases the scl line so that the master can generate a stop signal. inter-integrated circuit bus controller module (i 2 c) RM0017 369/904 doc id 14629 rev 8 arbitration lost if several masters try to engage the bus simultaneously, only one master wins and the others lose arbitration. the devices that lost arbitration are immediately switched to slave receive mode by the hardware. their data output to the sda line is stopped, but scl is still generated until the end of the byte during which arbitration was lost. an interrupt occurs at the falling edge of the ninth clock of this transfer with ibal=1 and ms/sl=0. if one master attempts to start transmission, while the bus is being engaged by another master, the hardware will inhibit the transmission, switch th e ms/sl bit from 1 to 0 without generating a stop condition, generate an interrupt to cpu and set the ibal to indicate that the attempt to engage the bus is failed. when considering these cases, the slave service routine should test the ibal first and the software should clear the ibal bit if it is set. RM0017 inter-integrated circuit bus controller module (i 2 c) doc id 14629 rev 8 370/904 figure 169. flow-chart of typical i 2 c interrupt routine clear master mode ? tx/rx ? last byte transmitted ? rxak=0 ? end of addr cycle (master rx) ? write next byte to ibdr switch to rx mode dummy read from ibdr generate stop signal read data from ibdr and store set txak =1 generate stop signal 2nd last byte to be read ? last byte to be read ? arbitration lost ? clear ibal iaas=1 ? iaas=1 ? srw=1 ? tx/rx ? set tx mode write data to ibdr set rx mode dummy read from ibdr ack from receiver ? tx next byte read data from ibdr and store switch to rx mode dummy read from ibdr rti yn y y y y y y y y y n n n n n n n n n y tx rx rx tx (write) (read) n ibif address transfer data transfer lin controller (linflex) RM0017 371/904 doc id 14629 rev 8 21 lin controller (linflex) 21.1 introduction the linflex (local interconnect network flexible) controller interfaces the lin network and supports the lin protocol versions 1.3; 2.0 and 2.1; and j2602 in both master and slave modes. linflex includes a lin mode that provides additional features (compared to standard uart) to ease lin implementation, improve system robustness, minimize cpu load and allow slave node resynchronization. 21.2 main features 21.2.1 lin mode features supports lin protocol versions 1.3, 2.0, 2.1 and j2602 master mode with autonomous message handling classic and enhanced checksum calculation and check single 8-byte buffer for transmission/reception extended frame mode for in-application programming (iap) purposes wake-up event on dominant bit detection true lin field state machine advanced lin error detection header, response and frame timeout slave mode (q) ? autonomous header handling ? autonomous transmit/receive data handling lin automatic resynchronizat ion, allowing oper ation with 16 mhz fast internal rc oscillator as clock source 16 identifier filters for autonomous message handling in slave mode q 21.2.2 uart mode features full duplex communication 8- or 9-bit with parity 4-byte buffer for reception, 4-byte buffer for transmission 8-bit counter for timeout management q. only linflex0 supports slave mode. RM0017 lin controller (linflex) doc id 14629 rev 8 372/904 21.2.3 features common to lin and uart fractional baud rate generator 3 operating modes for power saving and configuration registers lock: ? initialization ?normal ?sleep 2 test modes: ? loop back ?self test maskable interrupts 21.3 general description the increasing number of communication peripherals embedded on microcontrollers, for example can, lin and spi, requires more and more cpu resources for communication management. even a 32-bit microcontroller is overloaded if its peripherals do not provide high-level features to autonomously handle the communication. even though the lin protocol with a maximum baud rate of 20 kbit/s is relatively slow, it still generates a non-negligible load on the cpu if the lin is implemented on a standard uart, as usually the case. to minimize the cpu load in master mode, linflex handles the lin messages autonomously. in master mode, once the software has triggered the header transmission, linflex does not request any software intervention until the next header transmission request in transmission mode or until the checksum reception in reception mode. to minimize the cpu load in slave mode, linf lex requires software intervention only to: trigger transmission or reception or data discard depending on the identifier write data into the buffer (transmission mode) or read data from the buffer (reception mode) after checksum reception if filter mode is activated for slave mode, linflex requires software intervention only to write data into the buffer (transmission mode) or read data from the buffer (reception mode) the software uses the control, status and configuration registers to: configure lin parameters (for example, baud rate or mode) request transmissions handle receptions manage interrupts configure lin error and timeout detection process diagnostic information the message buffer stores transmitted or received lin frames. lin controller (linflex) RM0017 373/904 doc id 14629 rev 8 figure 170. lin topology network figure 171. linflex block diagram 21.4 fractional baud rate generation the baud rates for the receiver and transmitter are both set to the same value as programmed in the mantissa (linibrr) and fraction (linfbrr) registers. lin master node lin slave node 1 lin slave node n lin lin lin rx tx lin transceiver linflex controller mcu lin bus application lin protocol handler register model / application interface lin status baud rate filter configuration message slave lin control configuration message handler master message handler identifier filters (1) control status buffer interface 1. filter activation optional RM0017 lin controller (linflex) doc id 14629 rev 8 374/904 equation 7 lfdiv is an unsigned fixed point number. the 12-bit mantissa is coded in the linibrr and the fraction is coded in the linfbrr. the following examples show how to derive lfdiv from linibrr and linfbrr register values: example 1 deriving lfdiv from linibrr and linfbrr register values if linibrr = 27d and linfbrr = 12d, then mantissa (lfdiv) = 27d fraction (lfdiv) = 12/16 = 0.75d therefore lfdiv = 27.75d example 2 programming lfdiv from linibrr and linfbrr register values to program lfdiv = 25.62d, linfbrr = 16 0.62 = 9.92, nearest real number 10d = 0xa linibrr = mantissa (25.620d) = 25d = 0x19 note: the baud counters are updated with the new value of the baud registers after a write to linibrr. hence the baud register value must not be changed during a transaction. the linfbrr (containing the fraction bits) must be programmed before the linibrr. note: lfdiv must be greater than or equal to 1.5d, i.e. linibrr = 1 and linfbrr = 8. therefore, the maximum possible baudrate is fperiph_set_1_clk / 24. tx/ rx baud = f periph_set_1_clk (16 lfdiv) table 169. error calculation for programmed baud rates baud rate f periph_set_1_clk = 64 mhz f periph_set_1_clk = 16 mhz actual value programmed in the baud rate register % error = (calculated ? desired) baud rate / desired baud rate actual value programmed in the baud rate register % error = (calculated ? desired) baud rate / desired baud rate linibrr linfbrr linibrr linfbrr 2400 2399.97 1666 11 ?0.001 2399.88 416 11 ?0.005 9600 9599.52 416 11 ?0.005 9598.08 104 3 ?0.02 10417 10416.7 384 0 ?0.003 10416.7 96 0 ?0.003 19200 19201.9 208 5 0.01 19207.7 52 1 0.04 57600 57605.8 69 7 0.01 57554 17 6 ?0.08 115200 115108 34 12 ?0.08 115108 8 11 ?0.08 230400 230216 17 6 ?0.08 231884 4 5 0.644 460800 460432 8 11 ?0.08 457143 2 3 ?0.794 921600 927536 4 5 0.644 941176 1 1 2.124 lin controller (linflex) RM0017 375/904 doc id 14629 rev 8 21.5 operating modes linflex has three main operating modes: initialization, normal and sleep. after a hardware reset, linflex is in sleep mode to reduce power consumption. the software instructs linflex to enter initialization mo de or sleep mode by setting th e init bit or sleep bit in the lincr1. figure 172. linflex operating modes 21.5.1 initialization mode the software can be initialized while the hardware is in init ialization mode. to enter this mode the software sets the init bit in the lincr1. to exit initialization mode, the software clears the init bit. while in initialization mode, all message transfers to and from the lin bus are stopped and the status of the lin bus output lintx is recessive (high). entering initialization mode does not change any of the configuration registers. to initialize the linflex contro ller, the software selects the mode (lin master, lin slave or uart), sets up the baud rate register and, if lin slave mode with filter activation is selected, initializes the identifier list. 21.5.2 normal mode once initilization is complete, so ftware clears the init bit in the lincr1 to put the hardware into normal mode. 21.5.3 low power mode (sleep) to reduce power consumption, linflex has a low power mode called sleep mode. to enter sleep mode, software sets the sleep bit in the lincr1. in this mode, the linflex clock is sleep initialization normal s l e e p s l e e p * i n i t reset s l e e p l i n r x d o m i n a n t s l e e p * i n i t sl eep * i n i t RM0017 lin controller (linflex) doc id 14629 rev 8 376/904 stopped. conseque ntly, the linflex will not update the status bits but software can still access the linflex registers. linflex can be awakened (exit sleep mode) eit her by software clearing the sleep bit or on detection of lin bus activity if automatic wake-up mode is enabled (awum bit is set). on lin bus activity detection, hardware autom atically performs the wake-up sequence by clearing the sleep bit if the awum bit in the lincr1 is set. to exit from sleep mode if the awum bit is cleared, software clears the sleep bit when a wake-up event occurs. 21.6 test modes two test modes are available to the user: loop back mode and self test mode. they can be selected by the lbkm and sftm bits in the lincr1. these bits must be configured while linflex is in initialization mode. once one of the two test modes has been selected, linflex must be started in normal mode. 21.6.1 loop back mode linflex can be put in loop back mode by setting the lbkm bit in the lincr. in loop back mode, the linflex treats its own transm itted messages as re ceived messages. figure 173. linflex in loop back mode this mode is provided for self test functions. to be independent of external events, the lin core ignores the linrx signal. in this mode, the linflex performs an internal feedback from its tx output to its rx input. the actual value of the linrx input pin is disregarded by the linflex. the transmitted messages can be monitored on the lintx pin. 21.6.2 self test mode linflex can be put in self test mode by setting the lbkm and sftm bits in the lincr. this mode can be used for a ?hot self test?, meaning the linflex can be tested as in loop back mode but without affecting a runni ng lin system connected to the lintx and linrx pins. in this mode, the linrx pin is disconnected from the linflex and the lintx pin is held recessive. lintx linrx linflex tx rx lin controller (linflex) RM0017 377/904 doc id 14629 rev 8 figure 174. linflex in self test mode 21.7 memory map and registers description 21.7.1 memory map see the ?memory map? chapter of this reference manual for the base addresses for the linflex modules. table 170 shows the linflex memory map. linflex lintx linrx tx rx =1 table 170. linflex memory map address offset register location 0x0000 lin control register 1 (lincr1) on page 21-378 0x0004 lin interrupt enable register (linier) on page 21-381 0x0008 lin status register (linsr) on page 21-383 0x000c lin error status register (linesr) on page 21-386 0x0010 uart mode control register (uartcr) on page 21-387 0x0014 uart mode status register (uartsr) on page 21-389 0x0018 lin timeout control st atus register (lintcsr) on page 21-391 0x001c lin output compare register (linocr) on page 21-392 0x0020 lin timeout control register (lintocr) on page 21-392 0x0024 lin fractional baud rate register (linfbrr) on page 21-393 0x0028 lin integer baud rate register (linibrr) on page 21-394 0x002c lin checksum field register (lincfr) on page 21-395 0x0030 lin control register 2 (lincr2) on page 21-395 0x0034 buffer identifier register (bidr) on page 21-397 0x0038 buffer data register lsb (bdrl) (1) on page 21-398 0x003c buffer data register msb (bdrm) (2) on page 21-398 0x0040 identifier filter enable register (ifer) on page 21-399 RM0017 lin controller (linflex) doc id 14629 rev 8 378/904 lin control register 1 (lincr1) 0x0044 identifier filter match index (ifmi) on page 21-400 0x0048 identifier filter mode register (ifmr) on page 21-401 0x004c identifier filter control register 0 (ifcr0) on page 21-402 0x0050 identifier filter control register 1 (ifcr1) on page 21-403 0x0054 identifier filter control register 2 (ifcr2) on page 21-403 0x0058 identifier filter control register 3 (ifcr3) on page 21-403 0x005c identifier filter control register 4 (ifcr4) on page 21-403 0x0060 identifier filter control register 5 (ifcr5) on page 21-403 0x0064 identifier filter control register 6 (ifcr6) on page 21-403 0x0068 identifier filter control register 7 (ifcr7) on page 21-403 0x006c identifier filter control register 8 (ifcr8) on page 21-403 0x0070 identifier filter control register 9 (ifcr9) on page 21-403 0x0074 identifier filter control register 10 (ifcr10) on page 21-403 0x0078 identifier filter control register 11 (ifcr11) on page 21-403 0x007c identifier filter control register 12 (ifcr12) on page 21-403 0x0080 identifier filter control register 13 (ifcr13) on page 21-403 0x0084 identifier filter control register 14 (ifcr14) on page 21-403 0x0088 identifier filter control register 15 (ifcr15) on page 21-403 0x008c?0x000f reserved 1. lsb: least significant byte 2. msb: most significant byte table 170. linflex memory map (continued) address offset register location figure 175. lin control register 1 (lincr1) offset: 0x0000 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ccd cfd lase awum mbl bf sftm lbkm mme sbdt rblm sleep init w reset0000000010000010 lin controller (linflex) RM0017 379/904 doc id 14629 rev 8 table 171. lincr1 field descriptions field description ccd checksum calculation disable this bit disables the checksum calculation (see table 172 ). 0 checksum calculation is done by hardware. when this bit is 0, the lincfr is read-only. 1 checksum calculation is disabled. when this bit is set the lincfr is read/write. user can program this register to send a software-calculated crc (provided cfd is 0). note: this bit can be written in initialization mode only. it is read-only in normal or sleep mode. cfd checksum field disable this bit disables the checksum field transmission (see table 172 ). 0 checksum field is sent after the required number of data bytes is sent. 1 no checksum field is sent. note: this bit can be written in initialization mode only. it is read-only in normal or sleep mode. lase lin slave automatic re synchronization enable 0 automatic resynchro nization disable. 1 automatic resynchronization enable. note: this bit can be written in initialization mode only. it is read-only in normal or sleep mode. awum automatic wake-up mode this bit controls the behavior of t he linflex hardware during sleep mode. 0 the sleep mode is exited on software request by clearing the sleep bit of the lincr. 1 the sleep mode is exited automatically by ha rdware on linrx dominant state detection. the sleep bit of the lincr is cleared by hardware whenever wuf bit in the linsr is set. note: this bit can be written in initialization mode only. it is read-only in normal or sleep mode. mbl lin master break length this field indicates the break length in master mode (see ta bl e 1 7 3 ). note: this field can be written in initialization mode only. it is read-only in normal or sleep mode. bf bypass filter 0 no interrupt if identifier does not match any filter. 1 an rx interrupt is generated on identifier not matching any filter. note: ? if no filter is activated, this bit is reserved and always reads 1. ? this bit can be written in initialization mode only. it is read-only in normal or sleep mode. sftm self test mode this bit controls the self test mode. for more details, see section 21.6.2, self test mode. 0 self test mode disable. 1 self test mode enable. note: this bit can be written in initialization mode only. it is read-only in normal or sleep mode. lbkm loop back mode this bit controls the loop back mode. for more details see section 21.6.1, loop back mode. 0 loop back mode disable. 1 loop back mode enable. note: this bit can be written in initialization mode only. it is read-only in normal or sleep mode RM0017 lin controller (linflex) doc id 14629 rev 8 380/904 mme master mode enable 0 slave mode enable. 1 master mode enable. note: this bit can be written in initialization mode only. it is read-only in normal or sleep mode. sbdt slave mode break detection threshold 0 11-bit break. 1 10-bit break. note: this bit can be written in initialization mode only. it is read-only in normal or sleep mode. rblm receive buffer locked mode 0 receive buffer not locked on overrun. once the slave receive buffer is full the next incoming message overwrites the previous one. 1 receive buffer locked against overrun. once the receive buffer is full the next incoming message is discarded. note: this bit can be written in initialization mode only. it is read-only in normal or sleep mode. sleep sleep mode request this bit is set by software to re quest linflex to enter sleep mode. this bit is cleared by software to exit sleep mode or by hardware if the awum bit in lincr1 and the wuf bit in linsr are set (see ta bl e 1 7 4 ). init initialization request the software sets this bit to switch hardware in to initialization mode. if the sleep bit is reset, linflex enters normal mode when clearing the init bit (see ta b l e 1 7 4 ). table 172. checksum bits configuration cfd ccd lincfr checksum sent 1 1 read/write none 1 0 read-only none 0 1 read/write programmed in lincfr by bits cf[0:7] 0 0 read-only hardware calculated table 173. lin master break length selection mbl length 0000 10-bit 0001 11-bit 0010 12-bit 0011 13-bit 0100 14-bit 0101 15-bit 0110 16-bit 0111 17-bit table 171. lincr1 field descriptions (continued) field description lin controller (linflex) RM0017 381/904 doc id 14629 rev 8 lin interrupt enable register (linier) 1000 18-bit 1001 19-bit 1010 20-bit 1011 21-bit 1100 22-bit 1101 23-bit 1110 36-bit 1111 50-bit table 174. operating mode selection sleep init operating mode 1 0 sleep (reset value) x 1 initialization 00normal table 173. lin master break length selection (continued) mbl length figure 176. lin interrupt enable register (linier) offset: 0x0004 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r szie ocie beie ceie heie 00 feie boie lsie wuie dbfie dbeie drie dtie hrie w reset0000000000000000 table 175. linier field descriptions field description szie stuck at zero interrupt enable 0 no interrupt when szf bit in linesr or uartsr is set. 1 interrupt generated when szf bit in linesr or uartsr is set. RM0017 lin controller (linflex) doc id 14629 rev 8 382/904 ocie output compare interrupt enable 0 no interrupt when ocf bit in linesr or uartsr is set. 1 interrupt generated when ocf bit in linesr or uartsr is set. beie bit error interrupt enable 0 no interrupt when bef bit in linesr is set. 1 interrupt generated when bef bit in linesr is set. ceie checksum error interrupt enable 0 no interrupt on checksum error. 1 interrupt generated when checksum error flag (cef) in linesr is set. heie header error interrupt enable 0 no interrupt on break delimiter error, synch field error, identifier field error. 1 interrupt generated on break delimiter error, synch field error, identifier field error. feie framing error interrupt enable 0 no interrupt on framing error. 1 interrupt generated on framing error. boie buffer overrun interrupt enable 0 no interrupt on buffer overrun. 1 interrupt generated on buffer overrun. lsie lin state interrupt enable 0 no interrupt on lin state change. 1 interrupt generated on lin state change. this interrupt can be used for debugging purposes. it has no status flag but is reset when writing ?1111? into lins[0:3] in the linsr. wuie wake-up interrupt enable 0 no interrupt when wuf bit in linsr or uartsr is set. 1 interrupt generated when wuf bit in linsr or uartsr is set. dbfie data buffer full interrupt enable 0 no interrupt when buffer data register is full. 1 interrupt generated when data buffer register is full. dbeie data buffer empty interrupt enable 0 no interrupt when buffer data register is empty. 1 interrupt generated when data buffer register is empty. drie data reception comple te interrupt enable 0 no interrupt when data reception is completed. 1 interrupt generated when data received flag (drf) in linsr or uartsr is set. dtie data transmitted interrupt enable 0 no interrupt when data transmission is completed. 1 interrupt generated when data transmitted flag (dtf) is set in linsr or uartsr. hrie header received interrupt enable 0 no interrupt when a valid lin header has been received. 1 interrupt generated when a valid lin header has been received, that is, hrf bit in linsr is set. table 175. linier field descriptions (continued) field description lin controller (linflex) RM0017 383/904 doc id 14629 rev 8 lin status register (linsr) figure 177. lin status register (linsr) offset: 0x0008 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rlins 00rmb0 rbsy rps wuf dbff dbef drf dtf hrf ww1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000001000000 RM0017 lin controller (linflex) doc id 14629 rev 8 384/904 t table 176. linsr field descriptions field description lins lin modes / normal mode states 0000: sleep mode linflex is in sleep mode to save power consumption. 0001: initialization mode linflex is in initialization mode. normal mode states 0010: idle this state is entered on several events: ? sleep bit and init bit in lincr1 have been cleared by software, ? a falling edge has been received on rx pin and awum bit is set, ? the previous frame reception or transmission has been completed or aborted. 0011: break in slave mode, a falling edge followed by a dominant state has been detected. receiving break. note: in slave mode, in case of error new lin state can be either idle or break depending on last bit state. if last bit is dominant new lin state is break, otherwise idle. in master mode, break transmission ongoing. 0100: break delimiter in slave mode, a valid break has been detected. see section , lin control register 1 (lincr1) for break length configuration (10-bit or 11-bit). waiting for a rising edge. in master mode, break transmission has been completed. break delimiter transmission is ongoing. 0101: synch field in slave mode, a valid break delimiter has been detected (recessive state for at least one bit time). receiving synch field. in master mode, synch field transmission is ongoing. 0110: identifier field in slave mode, a valid synch field has been received. receiving identifier field. in master mode, identifier transmission is ongoing. 0111: header reception/transmission completed in slave mode, a valid header has been received and identifier field is available in the bidr. in master mode, header transmission is completed. 1000: data reception/transmission response reception/transmission is ongoing. 1001: checksum data reception/transmission completed. checksum reception/transmission ongoing. in uart mode, only the following stat es are flagged by the lin state bits: ?init ? sleep ?idle ? data transmission/reception lin controller (linflex) RM0017 385/904 doc id 14629 rev 8 rmb release message buffer 0 buffer is free. 1 buffer ready to be read by software. this bit must be cleared by software after reading data received in the buffer. this bit is cleared by hardware in initialization mode. rbsy receiver busy flag 0 receiver is idle 1 reception ongoing note: in slave mode, after header reception, if bi dr[dir] = 0 and reception starts then this bit is set. in this case, user cannot program lincr2[dtrq] = 1. rps lin receive pin state this bit reflects the current status of linrx pin for diagnostic purposes. wuf wake-up flag this bit is set by hardware and indicates to th e software that linflex has detected a falling edge on the linrx pin when: ? slave is in sleep mode ? master is in sleep mode or idle state this bit must be cleared by software. it is reset by hardware in initialization mode. an interrupt is generated if wuie bit in linier is set. dbff data buffer full flag this bit is set by hardware and indicates the buffer is full. it is set only when receiving extended frames (dfl > 7). this bit must be cleared by software. it is reset by hardware in initialization mode. dbef data buffer empty flag this bit is set by hardware and indicates the buffer is empty. it is set only when transmitting extended frames (dfl > 7). this bit must be cleared by software, once buffer has been filled again, in order to start transmission. this bit is reset by hardware in initialization mode. drf data reception completed flag this bit is set by hardware and indicates the data reception is completed. this bit must be cleared by software. it is reset by hardware in initialization mode. note: this flag is not set in case of bit error or framing error. dtf data transmission completed flag this bit is set by hardware and indicates the data transmission is completed. this bit must be cleared by software. it is reset by hardware in initialization mode. note: this flag is not set in case of bit error if iobe bit is reset. table 176. linsr field descriptions (continued) field description RM0017 lin controller (linflex) doc id 14629 rev 8 386/904 lin error status register (linesr) hrf header reception flag this bit is set by hardware and indicates a valid header reception is completed. this bit must be cleared by software. this bit is reset by hardware in initialization mode and at end of completed or aborted frame. note: if filters are enabled, this bit is set only when identifier software filter ing is required, that is to say: ? all filters are inactive and bf bit in lincr1 is set ? no match in any filter and bf bit in lincr1 is set ? tx filter match table 176. linsr field descriptions (continued) field description figure 178. lin error status register (linesr) offset: 0x000c access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r szf ocf bef cef sfef bdef idpef fef bof 0 0 0 000nf w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 table 177. linesr field descriptions field description szf stuck at zero flag this bit is set by hardware when the bus is dominant for more than a 100-bit time. if the dominant state continues, szf flag is set again after 87-bit time. it is cleared by software. ocf output compare flag 0 no output compare event occurred 1 the content of the counter has matched the content of oc1[0:7] or oc2[0:7] in linocr. if this bit is set and iot bit in lintcsr is set, linflex moves to idle state. if ltom bit in lintcsr is set, then ocf is cleared by hardware in initialization mode. if ltom bit is cleared, then ocf maintains it s status whatever the mode is. bef bit error flag this bit is set by hardware and indicates to the software that linflex has detected a bit error. this error can occur during response field transmission (slave and master modes) or during header transmission (in master mode). this bit is cleared by software. lin controller (linflex) RM0017 387/904 doc id 14629 rev 8 uart mode control register (uartcr) cef checksum error flag this bit is set by hardware and indicates that the received checksum does not match the hardware calculated checksum. this bit is cleared by software. note: this bit is never set if ccd or cfd bit in lincr1 is set. sfef synch field error flag this bit is set by hardware and indicates that a synch field error occurred (inconsistent synch field). bdef break delimiter error flag this bit is set by hardware and indicates that the received break delimiter is too short (less than one bit time). idpef identifier parity error flag this bit is set by hardware and indicates that a identifier parity error occurred. note: header interrupt is triggered when sfef or bd ef or idpef bit is set and heie bit in linier is set. fef framing error flag this bit is set by hardware and indicates to the so ftware that linflex has detected a framing error (invalid stop bit). this error can occur during reception of any data in the response field (master or slave mode) or during reception of synch field or identifier field in slave mode. bof buffer overrun flag this bit is set by hardware when a new data byte is received and the buffer full flag is not cleared. if rblm in lincr1 is set then the new byte received is discarded. if rblm is reset then the new byte overwrites the buffer. it can be cleared by software. nf noise flag this bit is set by hardware when noise is detected on a received character. this bit is cleared by software. table 177. linesr field descriptions (continued) field description figure 179. uart mode co ntrol register (uartcr) offset: 0x0010 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 tdfl 0 rdfl 00 00 rxen txen op pce wl uart w reset0000000000000000 RM0017 lin controller (linflex) doc id 14629 rev 8 388/904 table 178. uartcr field descriptions field description tdfl transmitter data field length this field sets the number of bytes to be transm itted in uart mode. it can be programmed only when the uart bit is set. tdfl[0:1] = transmit buffer size ? 1. 00 transmit buffer size = 1. 01 transmit buffer size = 2. 10 transmit buffer size = 3. 11 transmit buffer size = 4. rdfl receiver data field length this field sets the number of bytes to be received in uart mode. it can be programmed only when the uart bit is set. rdfl[0:1] = receive buffer size ? 1. 00 receive buffer size = 1. 01 receive buffer size = 2. 10 receive buffer size = 3. 11 receive buffer size = 4. rxen receiver enable 0 receiver disable. 1 receiver enable. this bit can be programmed only when the uart bit is set. txen transmitter enable 0 transmitter disable. 1 transmitter enable. this bit can be programmed only when the uart bit is set. note: transmission starts when this bit is set and when writing data0 in the bdrl register. op odd parity 0 sent parity is even. 1 sent parity is odd. this bit can be programmed in initialization mode only when the uart bit is set. pce parity control enable 0 parity transmit/check disable. 1 parity transmit/check enable. this bit can be programmed in initialization mode only when the uart bit is set. wl word length in uart mode 0 7-bit data + parity bit. 1 8-bit data (or 9-bi t if pce is set). this bit can be programmed in initialization mode only when the uart bit is set. uart uart mode enable 0 lin mode. 1 uart mode. this bit can be programmed in initialization mode only. lin controller (linflex) RM0017 389/904 doc id 14629 rev 8 uart mode status register (uartsr) figure 180. uart mode st atus register (uartsr) offset: 0x0014 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r szf ocf pe3 pe2 pe1 pe0 rmb fef bof rps wuf 0 0 drf dtf nf ww1cw1cw1cw1cw1cw1cw1cw1cw1cw1cw1c w1c w1c w1c reset0000000000000000 table 179. uartsr field descriptions field description szf stuck at zero flag this bit is set by hardware when the bus is dominant for more than a 100-bit time. it is cleared by software. ocf ocf output compare flag 0 no output compare event occurred. 1 the content of the counter has matched the co ntent of oc1[0:7] or oc2[0:7] in linocr. an interrupt is generated if the ocie bit in linier register is set. pe3 parity error flag rx3 this bit indicates if there is a parity error in the corresponding received byte (rx3). see section , buffer in uart mode. no interrupt is generated if this error occurs. 0 no parity error. 1 parity error. pe2 parity error flag rx2 this bit indicates if there is a parity error in the corresponding received byte (rx2). see section , buffer in uart mode. no interrupt is generated if this error occurs. 0 no parity error. 1 parity error. pe1 parity error flag rx1 this bit indicates if there is a parity error in the corresponding received byte (rx1). see section , buffer in uart mode. no interrupt is generated if this error occurs. 0 no parity error. 1 parity error. pe0 parity error flag rx0 this bit indicates if there is a parity error in the corresponding received byte (rx0). see section , buffer in uart mode. no interrupt is generated if this error occurs. 0 no parity error. 1 parity error. RM0017 lin controller (linflex) doc id 14629 rev 8 390/904 rmb release message buffer 0buffer is free. 1 buffer ready to be read by software. this bit must be cleared by software after reading data received in the buffer. this bit is cleared by hardware in initialization mode. fef framing error flag this bit is set by hardware and indicates to the software that linflex has detected a framing error (invalid stop bit). bof buffer overrun flag this bit is set by hardware when a new data byte is received and the buffer full flag is not cleared. if rblm in lincr1 is set then the new byte receiv ed is discarded. if rblm is reset then the new byte overwrites buffer. it can be cleared by software. rps lin receive pin state this bit reflects the current status of linrx pin for diagnostic purposes. wuf wake-up flag this bit is set by hardware and indicates to the software that linflex has detected a falling edge on the linrx pin in sleep mode. this bit must be cleared by software. it is reset by hardware in initialization mode. an interrupt i generated if wuie bit in linier is set. drf data reception completed flag this bit is set by hardware and indicates the data reception is completed, that is, the number of bytes programmed in rdfl[0:1] in uartcr have been received. this bit must be cleared by software. it is reset by hardware in initialization mode. an interrupt is generated if drie bit in linier is set. note: in uart mode, this flag is set in case of framing error, parity error or overrun. dtf data transmission completed flag this bit is set by hardware and indicates the data tr ansmission is completed, that is, the number of bytes programmed in tdfl[0:1] have been transmitted. this bit must be cleared by software. it is reset by hardware in initialization mode. an interrupt is generated if dtie bit in linier is set. nf noise flag this bit is set by hardware when noise is detected on a received character. this bit is cleared by software. table 179. uartsr field descriptions (continued) field description lin controller (linflex) RM0017 391/904 doc id 14629 rev 8 lin timeout control status register (lintcsr) figure 181. lin timeout control status register (lintcsr) offset: 0x0018 access: user read/write 01234 5 6 7 89101112131415 r 0000 000 0 0000 0000 w reset000000 0 0 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 0 lto m iot toce cnt w reset000000 1 0 00000000 table 180. lintcsr field descriptions field description lto m lin timeout mode 0 lin timeout mode (header, response and frame timeout detection). 1 output compare mode. this bit can be set/cleared in initialization mode only. iot idle on timeout 0 lin state machine not reset to idle on timeout event. 1 lin state machine reset to idle on timeout event. this bit can be set/cleared in initialization mode only. toce timeout counter enable 0 timeout counter disable. ocf bit in linesr or uartsr is not set on an output compare event. 1 timeout counter enable. ocf bit is set if an output compare event occurs. toce bit is configurable by software in initializati on mode. if lin state is not init and if timer is in lin timeout mode, then hardware takes control of toce bit. cnt counter value this field indicates the lin timeout counter value. RM0017 lin controller (linflex) doc id 14629 rev 8 392/904 lin output compare register (linocr) lin timeout control register (lintocr) figure 182. lin output compare register (linocr) offset: 0x001c access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r oc2 (1) 1. if lintcsr[ltom] = 1, this field is read-only. oc1 (1) w reset11111111 11111111 table 181. linocr field descriptions field description oc2 output compare 2 value these bits contain the value to be compared to the value of bits cnt[0:7] in lintcsr. oc1 output compare 1 value these bits contain the value to be compared to the value of bits cnt[0:7] in lintcsr. figure 183. lin timeout control register (lintocr) offset: 0x0020 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 rto 0 hto w reset0000111000101100 lin controller (linflex) RM0017 393/904 doc id 14629 rev 8 lin fractional baud rate register (linfbrr) table 182. lintocr field descriptions field description rto response timeout value this field contains the response timeout duration (in bit time) for 1 byte. the reset value is 0xe = 14, corresponding to t response_maximum =1.4t response_nominal hto header timeout value this field contains the header timeout duration (in bit time). this value does not include the break and the break delimiter. the reset value is the 0x2c = 44, corresponding to t header_maximum. programming linsr[mme] = 1 changes the hto value to 0x1c = 28. this field can be written only in slave mode. figure 184. lin fractional baud rate register (linfbrr) offset: 0x0024 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 0000 0000 div_f w reset0000000000000000 table 183. linfbrr field descriptions field description div_f fraction bits of lfdiv the 4 fraction bits define the value of t he fraction of the linflex divider (lfdiv). fraction (lfdiv) = decimal value of div_f / 16. this field can be written in initialization mode only. RM0017 lin controller (linflex) doc id 14629 rev 8 394/904 lin integer baud rate register (linibrr) figure 185. lin integer baud rate register (linibrr) offset: 0x0028 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000 div_m w reset0000000000000000 table 184. linibrr field descriptions field description div_m lfdiv mantissa this field defines the linflex di vider (lfdiv) mantissa value (see ta b l e 1 8 5 ). this field can be written in initialization mode only. table 185. integer baud rate selection div_m[0:12] mantissa 0x0000 lin clock disabled 0x0001 1 ... ... 0x1ffe 8190 ox1fff 8191 lin controller (linflex) RM0017 395/904 doc id 14629 rev 8 lin checksum field register (lincfr) lin control register 2 (lincr2) figure 186. lin checksum field register (lincfr) offset: 0x002c access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 0000 cf w reset0000000000000000 table 186. lincfr field descriptions field description cf checksum bits when lincr1[ccd] = 0, this field is read-only. when lincr1[ccd] = 1, this field is read/write. see ta b l e 1 7 2 . figure 187. lin control register 2 (lincr2) offset: 0x0030 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 iobe iope 0 0 0 0 0 0 0 0 0 0 0 0 0 w wurq ddrq dtrq abrq htrq reset0110000000000000 RM0017 lin controller (linflex) doc id 14629 rev 8 396/904 table 187. lincr2 field descriptions field description iobe idle on bit error 0 bit error does not reset lin state machine. 1 bit error reset lin state machine. this bit can be set/cleared in initialization mode only. iope idle on identifier parity error 0 identifier parity error does not reset lin state machine. 1 identifier parity error reset lin state machine. this bit can be set/cleared in initialization mode only. wurq wake-up generation request setting this bit generates a wake-up pulse. it is reset by hardware when the wake-up character has been transmitted. the character sent is copied fr om data0 in bdrl buffer . note that this bit cannot be set in sleep mode. software has to exit sleep mode before requesting a wake-up. bit error is not checked when transmitting the wake-up request. ddrq data discard request set by software to stop data reception if the fram e does not concern the node. this bit is reset by hardware once linflex has moved to idle state. in slave mode, this bit can be set only when hrf bit in linsr is set and identif ier did not match any filter. dtrq data transmission request set by software in slave mode to request the transmission of the lin data field stored in the buffer data register. this bit can be set only when hrf bit in linsr is set. cleared by hardware when the request has been comp leted or aborted or on an error condition. in master mode, this bit is set by hardware when bidr[dir] = 1 and header transmission is completed. abrq abort request set by software to abort the current transmission. cleared by hardware when the transmission has been aborted. linflex aborts the transmission at the end of the current bit. this bit can also abort a wake-up request. it can also be used in uart mode. htrq header transmission request set by software to request the transmission of the lin header. cleared by hardware when the request has been completed or aborted. this bit has no effect in uart mode. lin controller (linflex) RM0017 397/904 doc id 14629 rev 8 buffer identifier register (bidr) figure 188. buffer identifier register (bidr) offset: 0x0034 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dfl dir ccs 00 id w reset0000000000000000 table 188. bidr field descriptions field description dfl data field length this field defines the number of data bytes in the response part of the frame. dfl = number of data bytes ? 1. normally, lin uses only df l[2:0] to manage frames with a maximum of 8 bytes of data. identifier filters are compatible with dfl[ 2:0] only. dfl[5:3] are provided to manage extended frames. dir direction this bit controls the direction of the data field. 0 linflex receives the data and co pies them in the bdr registers. 1 linflex transmits the data from the bdr registers. ccs classic checksum this bit controls the type of checksum applied on the current message. 0 enhanced checksum covering identifier and data fiel ds. this is compatible with lin specification 2.0 and higher. 1 classic checksum covering data fields only. this is compatible with lin specification 1.3 and earlier. in lin slave mode (mme bit cleared in lincr1), th is bit must be configured before the header reception. if the slave has to manage frames with 2 types of checksum, filters must be configured. id identifier identifier part of the identifier field without the identifier parity. RM0017 lin controller (linflex) doc id 14629 rev 8 398/904 buffer data register lsb (bdrl) buffer data register msb (bdrm) figure 189. buffer data register lsb (bdrl) offset: 0x0038 access: user read/write 0123456789101112131415 r data3 data2 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r data1 data0 w reset0000000000000000 table 189. bdrl field descriptions field description data3 data byte 3 data byte 3 of the data field. data2 data byte 2 data byte 2 of the data field. data1 data byte 1 data byte 1 of the data field. data0 data byte 0 data byte 0 of the data field. figure 190. buffer data register msb (bdrm) offset: 0x003c access: user read/write 0123456789101112131415 r data7 data6 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r data5 data4 w reset0000000000000000 lin controller (linflex) RM0017 399/904 doc id 14629 rev 8 identifier filter enable register (ifer) table 190. bdrm field descriptions field description data7 data byte 7 data byte 7 of the data field. data6 data byte 6 data byte 6 of the data field. data5 data byte 5 data byte 5 of the data field. data4 data byte 4 data byte 4 of the data field. figure 191. identifier filter enable register (ifer) offset: 0x0040 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 0000 fact w reset0000000000000000 table 191. ifer field descriptions field description fact filter activation (see table 192 ) 0 filters 2 n and 2 n + 1 are deactivated. 1 filters 2 n and 2 n + 1 are activated. this field can be set/cleared in initialization mode only. table 192. ifer[fact] configuration bit value result fact[0] 0 filters 0 and 1 are deactivated. 1 filters 0 and 1 are activated. fact[1] 0 filters 2 and 3 are deactivated. 1 filters 2 and 3 are activated. RM0017 lin controller (linflex) doc id 14629 rev 8 400/904 identifier filter match index (ifmi) fact[2] 0 filters 4 and 5 are deactivated. 1 filters 4 and 5 are activated. fact[3] 0 filters 6 and 7 are deactivated. 1 filters 6 and 7 are activated. fact[4] 0 filters 8 and 9 are deactivated. 1 filters 8 and 9 are activated. fact[5] 0 filters 10 and 11 are deactivated. 1 filters 10 and 11 are activated. fact[6] 0 filters 12 and 13 are deactivated. 1 filters 12 and 13 are activated. fact[7] 0 filters 14 and 15 are deactivated. 1 filters 14 and 15 are activated. table 192. ifer[fact] configuration (continued) bit value result figure 192. identifier filter match index (ifmi) address: base + 0x0044 access: user read-only 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 0 0000 0 0 0 0 ifmi[0:4] w reset0000000000000000 table 193. ifmi field descriptions field description 0:26 reserved ifmi[0:4] 27:31 filter match index this register contains the index corresponding to th e received identifier. it can be used to directly write or read the data in sram (see section , slave mode for more details). when no filter matches, ifmi[0:4] = 0. when filter n is matching, ifmi[0:4] = n +1. lin controller (linflex) RM0017 401/904 doc id 14629 rev 8 identifier filter mode register (ifmr) figure 193. identifier filter mode register (ifmr) offset: 0x0048 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 0 0000 0 ifm w reset0000000000000000 table 194. ifmr field descriptions field description ifm filter mode (see table 195 ). 0filters 2 n and 2 n + 1 are in identifier list mode. 1filters 2 n and 2 n + 1 are in mask mode (filter 2 n + 1 is the mask for the filter 2 n ). table 195. ifmr[ifm] configuration bit value result ifm[0] 0 filters 0 and 1 are in identifier list mode. 1 filters 0 and 1 are in mask mode (filter 1 is the mask for the filter 0). ifm[1] 0 filters 2 and 3 are in identifier list mode. 1 filters 2 and 3 are in mask mode (filter 3 is the mask for the filter 2). ifm[2] 0 filters 4 and 5 are in identifier list mode. 1 filters 4 and 5 are in mask mode (filter 5 is the mask for the filter 4). ifm[3] 0 filters 6 and 7 are in identifier list mode. 1 filters 6 and 7 are in mask mode (filter 7 is the mask for the filter 6). ifm[4] 0 filters 8 and 9 are in identifier list mode. 1 filters 8 and 9 are in mask mode (filter 9 is the mask for the filter 8). ifm[5] 0 filters 10 and 11 are in identifier list mode. 1 filters 10 and 11 are in mask mode (f ilter 11 is the mask for the filter 10). ifm[6] 0 filters 12 and 13 are in identifier list mode. 1 filters 12 and 13 are in mask mode (f ilter 13 is the mask for the filter 12). RM0017 lin controller (linflex) doc id 14629 rev 8 402/904 identifier filter control register (ifcr2 n ) note: this register can be writte n in initialization mode only. ifm[7] 0 filters 14 and 15 are in identifier list mode. 1 filters 14 and 15 are in mask mode (f ilter 15 is the mask for the filter 14). table 195. ifmr[ifm] configuration (continued) bit value result figure 194. identifier filter control register (ifcr2 n ) offsets : 0x004c?0x0084 (8 registers) access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000 dfl dir ccs 00 id w w1c reset0000000000000000 table 196. ifcr2 n field descriptions field description dfl data field length this field defines the number of data bytes in the response part of the frame. dir direction this bit controls the direction of the data field. 0 linflex receives the data and copies them in the bdrl and bdrm registers. 1 linflex transmits the data from the bdrl and bdrm registers. ccs classic checksum this bit controls the type of checksum applied on the current message. 0 enhanced checksum covering identifier and data fi elds. this is compatible with lin specification 2.0 and higher. 1 classic checksum covering data fields only. this is compatible with lin specification 1.3 and earlier. id identifier identifier part of the identifier fi eld without the identifier parity. lin controller (linflex) RM0017 403/904 doc id 14629 rev 8 identifier filter control register (ifcr2 n +1) note: this register can be writte n in initialization mode only. 21.8 functional description 21.8.1 uart mode the main features in the uart mode are full duplex communication 8- or 9-bit data with parity 4-byte buffer for reception, 4-byte buffer for transmission 8-bit counter for timeout management figure 195. identifier filter control register (ifcr2 n +1) offsets: 0x0050?0x0088 (8 registers) access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000 dfl dir ccs 00 id w w1c reset0000000000000000 table 197. ifcr2 n + 1 field descriptions field description dfl data field length this field defines the number of data by tes in the response part of the frame. dfl = number of data bytes ? 1. dir direction this bit controls the direction of the data field. 0 linflex receives the data and copies them in the bdrl and bdrm registers. 1 linflex transmits the data from the bdrl and bdrm registers. ccs classic checksum this bit controls the type of chec ksum applied on the current message. 0 enhanced checksum covering identifier and da ta fields. this is compatible with lin specification 2.0 and higher. 1 classic checksum covering data field only. this is compatible with li n specification 1.3 and earlier. id identifier identifier part of the identifier fi eld without the identifier parity RM0017 lin controller (linflex) doc id 14629 rev 8 404/904 8-bit data frames : the 8th bit can be a data or a parity bit. even/odd parity can be selected by the odd parity bit in the uartcr. an even parity is set if the modulo-2 sum of the 7 data bits is 1. an odd parity is cleared in this case. figure 196. uart mode 8-bit data frame 9-bit frames : the 9th bit is a parity bit. even/odd parity can be selected by the odd parity bit in the uartcr. an even parity is set if the modulo-2 sum of the 8 data bits is 1. an odd parity is cleared in this case. figure 197. uart mode 9-bit data frame buffer in uart mode the 8-byte buffer is divided into two parts: one for receiver and one for transmitter as shown in table 198 . uart transmitter in order to start transmission in uart mode, you must program the uart bit and the transmitter enable (txen) bit in the uartcr to 1. transmission starts when data0 (least start bit d0 d7 stop bit byte field ? data bit ? parity bit d1 d2 d3 d4 d5 d6 start bit d0 d7 stop bit byte field ? parity bit d1 d2 d3 d4 d5 d6 d8 table 198. message buffer buffer data register lin mode uart mode bdrl[0:31] transmit/receive buffer data0[0:7] transmit buffer tx0 data1[0:7] tx1 data2[0:7] tx2 data3[0:7] tx3 bdrm[0:31] data4[0:7] receive buffer rx0 data5[0:7] rx1 data6[0:7] rx2 data7[0:7] rx3 lin controller (linflex) RM0017 405/904 doc id 14629 rev 8 significant data byte) is programmed. the number of bytes transmitted is equal to the value configured by uartcr[tdfl] (see table 178 ). the transmit buffer is 4 bytes, hence a 4-byte maximum transmission can be triggered. once the programmed number of bytes has been transmitted, the uartsr[dtf] bit is set. if uartcr[txen] is reset during a transmission then the current transmission is completed and no further transmission can be invoked. uart receiver the uart receiver is active as soon as th e user exits initialization mode and programs uartcr[rxen] = 1. there is a dedicated 4-byte data buffer for received data bytes. once the programmed number (rdfl bits) of bytes has been received, the uartsr[drf] bit is set. if the rxen bit is reset during a reception then the current reception is completed and no further reception can be invoked until rxen is set. if a parity error occurs during reception of any byte, then the corresponding pe x bit in the uartsr is set. no interrupt is generated in this case. if a framing error occurs in any byte (uartsr[fe] = 1) then an interrupt is generated if the linier[feie] bit is set. if the last received frame has not been read from the buffer (that is, rmb bit is not reset by the user) then upon reception of the next byte an overrun error occurs (uartsr[bof] = 1) and one message will be lost. which message is lost depends on the configuration of lincr1[rblm]. if the buffer lock function is disabled (lincr1[rblm] = 0) the last message stored in the buffer is overwritten by the new incoming message. in this ca se the latest message is always available to the application. if the buffer lock function is enabled (lincr1[rblm] = 1) the most recent message is discarded and the previous message is available in the buffer. an interrupt is generated if the linier[boie] bit is set. clock gating the linflex clock can be gated from the mode entry module (mc_me). in uart mode, the linflex controller acknowledges a clock gating request once the data transmission and data reception are completed, that is, once the transmit buffer is empty and the receive buffer is full. 21.8.2 lin mode lin mode comprises four submodes: master mode slave mode (r) slave mode with identifier filtering (r) slave mode with automatic resynchronization (r) these submodes are described in the following pages. r. only linflex0 supports slave mode RM0017 lin controller (linflex) doc id 14629 rev 8 406/904 master mode in master mode the application uses the message buffer to handle the lin messages. master mode is se lected when the lincr1[mme] bit is set. lin header transmission according to the lin protocol any communication on the lin bus is triggered by the master sending a header. the header is transmitted by the master task while the data is transmitted by the slave task of a node. to transmit a header with linflex the application must set up the identifier, the data field length and configure the message (direction and checksum type) in the bidr before requesting the header transmission by setting lincr2[htrq]. data transmission (transceiver as publisher) when the master node is publisher of the data corresponding to the identifier sent in the header, then the slave task of the master has to send the data in the response part of the lin frame. therefore, the application must provide the data to linflex before requesting the header transmission. the application stores the data in the message buffer bdr. according to the data field length, linflex transmits the data and the checksum. the application uses the bdr[ccs] bit to configure the checksum type (classic or enhanced) for each message. if the response has been sent successfully, the linsr[dtf] bi t is set. in case of error, the dtf flag is not set and the corresponding error flag is set in the linesr (see section , error handling ). it is possible to handle frames with a response size larger than 8 bytes of data (extended frames). if the data field length in the bidr is configured with a value higher than 8 data bytes, the linsr[dbef] bit is set after the first 8 bytes have been transmitted. the application has to update the buffer bdr before resetting the dbef bit. the transmission of the next bytes starts when the dbef bit is reset. after the last data byte (or the checksum byte) has been sent, the dtf flag is set. the direction of the message buffer is controlled by the bidr[dir] bit. when the application sets this bit the response is sent by linflex (publisher). resetting this bit configures the message buffer as subscriber. data reception (transceiver as subscriber) to receive data from a slave node, the master sends a header with the corresponding identifier. linflex stores the data received from the slave in the message buffer and stores the message status in the linsr. if the response has been re ceived successfully, the linsr[drf] is set. in case of error, the drf flag is not set and the corresponding error flag is set in the linesr (see section , error handling ). it is possible to handle frames with a response size larger than 8 bytes of data (extended frames). if the data field length in the bidr is configured with a value higher than 8 data bytes, the linsr[dbff] bit is set once the first 8 bytes have been received. the application has to read the buffer bdr before resetting the dbff bit. once the last data byte (or the checksum byte) has been received, the drf flag is set. lin controller (linflex) RM0017 407/904 doc id 14629 rev 8 data discard to discard data from a slave, the bidr[d ir] bit must be reset and the lincr2 [ddrq] bit must be set before starting the header transmission. error detection linflex is able to detect and handle lin communication errors. a code stored in the lin error status register (linesr) signals the errors to the software. in master mode, the following errors are detected: bit error : during transmission, the value read back from the bus differs from the transmitted value. framing error : a dominant state has been sampled on the stop bit of the currently received character (synch field, identifier field or data field). checksum error : the computed checksum does not match the received one. response and frame timeout : see section 21.8.3, 8-bit timeout counter , for more details. error handling in case of bit error detection during transmission, linflex stops the transmission of the frame after the corrupted bit. linflex returns to idle state and an interrupt is generated if linier[beie] = 1. during reception, a framing error leads linflex to discard the current frame. linflex returns immediately to idle state. an in terrupt is generated if linier[feie] = 1. during reception, a checksum error leads linf lex to discard the received frame. linflex returns to idle state. an interrupt is generated if linier[ceie] = 1. slave mode in slave mode the application uses the message buffer to handle the lin messages. slave mode is selected when lincr1[mme] = 0. data transmission (transceiver as publisher) when linflex receives the identifier, the lins r[hrf] is set and, if linier[hrie] = 1, an rx interrupt is generated. the software must read the received identifier in the bidr, fill the bdr registers, specify the data field length using the bidr[dfl] and trigger the data transmission by setting the lincr2[dtrq] bit. one or several identifier filters can be configured for transmission by setting the ifcr x [dir] bit and activated by setting one or several bits in the ifer. when at least one identifier filter is configured in transmission and activated, and if the received identifier matches the filter, a specific tx interrupt (instead of an rx interrupt) is generated. typically, the application has to copy the data from sram locations to the bdar. to copy the data to the right location, the application has to identify the data by means of the identifier. to avoid this and to ease the access to the sram locations, the linflex controller provides a filter match index. this index value is the number of the filter that matched the received identifier. RM0017 lin controller (linflex) doc id 14629 rev 8 408/904 the software can use the index in the ifmi register to directly access the pointer that points to the right data array in the sram area and copy this data to the bdar (see figure 199 ). using a filter avoids the software having to configure the direction, the data field length and the checksum type in the bidr. the softwa re fills the bdar a nd triggers the data transmission by programming lincr2[dtrq] = 1. if linflex cannot provide enough tx identifier filters to handle all identifiers the software has to transmit data for, then a filter can be configured in mask mode (see section , slave mode with identifier filtering ) in order to manage several identifiers with one filter only. data reception (transceiver as subscriber) when linflex receives the identifier, the lins r[hrf] bit is set and, if linier[hrie] = 1, an rx interrupt is generated. the software must read the received identifier in the bidr and specify the data field length using the bidr[dfl] field before receiving the stop bit of the first byte of data field. when the checksum reception is completed, an rx interrupt is generated to allow the software to read the received data in the bdr registers. one or several identifier filters can be configured for reception by programming ifcr x [dir] = 0 and activated by setting one or several bits in the ifer. when at least one identifier filter is configured in reception and activated, and if the received identifier matches the filter, an rx interrupt is generated after the checksum reception only. typically, the application has to copy the data from the bdar to sram locations. to copy the data to the right location, the application has to identify the data by means of the identifier. to avoid this and to ease the access to the sram locations, the linflex controller provides a filter match index. this index value is the number of the filter that matched the received identifier. the software can use the index in the ifmi register to directly access the pointer that points to the right data array in the sram area and copy this data from the bdar to the sram (see figure 199 ). using a filter avoids the software reading the id value in the bidr, and configuring the direction, the data field length and the checksum type in the bidr. if linflex cannot provide enough rx identifier filters to handle all identifiers the software has to receive the data for, then a filter can be configured in mask mode (see section , slave mode with identifier filtering ) in order to manage several id entifiers with one filter only. data discard when linflex receives the identifier, the lins r[hrf] bit is set and, if linier[hrie] = 1, an rx interrupt is generated. if the received identifier does not concern the node, you must program lincr2[ddrq] = 1. linflex returns to idle state after bit ddrq is set. lin controller (linflex) RM0017 409/904 doc id 14629 rev 8 error detection in slave mode, the following errors are detected: header error : an error occurred during header reception (break delimiter error, inconsistent synch field, header timeout). bit error : during transmission, the value read back from the bus differs from the transmitted value. framing error : a dominant state has been sampled on the stop bit of the currently received character (synch field, identifier field or data field). checksum error : the computed checksum does not match the received one. error handling in case of bit error detection during transmission, linflex stops the transmission of the frame after the corrupted bit. linflex returns to idle state and an interrupt is generated if the beie bit in the linier is set. during reception, a framing error leads linflex to discard the current frame. linflex returns immediately to idle state. an in terrupt is generated if linier[feie] = 1. during reception, a checksum error leads linf lex to discard the received frame. linflex returns to idle state. an interrupt is generated if linier[ceie] = 1. during header reception, a break delimiter error, an inconsistent synch field or a timeout error leads linflex to discard the header. an interrupt is generated if linier[heie] = 1. linflex returns to idle state. valid header a received header is considered as valid when it has been received correctly according to the lin protocol. if a valid break field and break delimiter come before the end of the current header or at any time during a data field, the current header or data is discarded and the state machine synchronizes on this new break. valid message a received or transmitted message is considered as valid when the data has been received or transmitted without error according to the lin protocol. overrun once the message buffer is full, the next valid message reception leads to an overrun and a message is lost. the hardware sets the bof bit in the linsr to signal the overrun condition. which message is lost depends on the configuration of the rx message buffer: if the buffer lock function is disabled (lincr1[rblm] = 0) the last message stored in the buffer is overwritten by the new incoming message. in this ca se the latest message is always available to the application. if the buffer lock function is enabled (lincr1[rblm] = 0) the most recent message is discarded and the previous message is available in the buffer. slave mode with identifier filtering in the lin protocol the identifier of a message is not associated with the address of a node but related to the content of the message. consequently a transmitter broadcasts its RM0017 lin controller (linflex) doc id 14629 rev 8 410/904 message to all receivers. on header reception a slave node decides ? depending on the identifier value ? whether the software needs to receive or send a response. if the message does not target the node, it must be discarded without software intervention. to fulfill this requirem ent, the linflex co ntroller provides configurab le filters in order to request software intervention only if needed. this hardware filterin g saves cpu resources that would otherwise be needed by software for filtering. filter mode usually each of the eight ifcr registers filters one dedicated identifier, but this limits the number of identifiers linflex can handle to the number of ifcr registers implemented in the device. therefore, in order to be able to handle more identifiers, the filters can be configured in mask mode. in identifier list mode (the default mode), both filter registers are used as identifier registers. all bits of the incoming identifier must match the bits specified in the filter register. in mask mode , the identifier registers are associated with mask registers specifying which bits of the identifier are handled as ?must match? or as ?don?t care?. for the bit mapping and registers organization, please see figure 198 . figure 198. filter configuration?register organization identifier filter mode configuration the identifier filters are configured in the ifcr x registers. to configure an identifier filter the filter must first be deactivated by programming ifer[fact] = 0.. the identifier list or identifier mask mode for the corresponding ifcr x registers is configured by the ifmr[ifm] bit. for each filter, the ifcr x register configures the id (or the mask), the direction (tx or rx), the data field length, and the checksum type. ifcr n identifier id bit mapping identifier filter register organization 15 0 dfl ccs dir identifier filter configuration ifcr2 n identifier identifier ifcr2 n +1 ifm = 0 identifier filter mode ifcr2 n identifier mask ifcr2 n +1 ifm = 1 identifier list mode mask mode lin controller (linflex) RM0017 411/904 doc id 14629 rev 8 if no filter is active, an rx interrupt is generated on any received identifier event. if at least one active filter is configured as tx, all received identifiers matching this filter generate a tx interrupt. if at least one active filter is configured as rx, all received identifiers matching this filter generate an rx interrupt. if no active filter is configured as rx, all received identifiers not matching tx filter(s) generate an rx interrupt. figure 199. identifier match index slave mode with automatic resynchronization automatic resynchronization must be enabled in slave mode if f periph_set_1_clk tolerance is greater than 1.5%. this feature compensates a f periph_set_1_clk deviation up to 14%, as specified in lin standard. table 199. filter to interrupt vector correlation number of active filters number of active filters configured as tx number of active filters configured as rx interrupt vector 0 0 0 rx interrupt on all identifiers a (a > 0) a0 ? tx interrupt on identifiers matching the filters, ? rx interrupt on all other identifiers if bf bit is set, no rx interrupt if bf bit is reset n (n=a+b) a (a > 0) b (b > 0) ? tx interrupt on identifiers matching the tx filters, ? rx interrupt on identifiers matching the rx filters, ? all other identifiers discarded (no interrupt) b (b > 0) 0b ? rx interrupt on identifiers matching the filters, ? tx interrupt on all other identifiers if bf bit is set, no tx interrupt if bf bit is reset ifmi message0 message1 message2 data pointers table sram @ + RM0017 lin controller (linflex) doc id 14629 rev 8 412/904 this mode is similar to sl ave mode as described in section , slave mode , with the addition of automatic resynchronization enabled by the lase bit. in this mode linflex adjusts the fractional baud rate generator after each synch field reception. automatic resynchr onization method when automatic resynchronization is enabled, after each lin break, the time duration between five falling edges on rdi is sampled on f periph_set_1_clk and the result of this measurement is stored in an internal 19-bit register called sm (not user accessible) (see figure 200 ). then the lfdiv value (and its associated registers linibrr and linfbrr) are automatically updated at the end of the fifth falling ed ge. during lin synch field measurement, the linflex state machine is stopped and no data is transferred to the data register. figure 200. lin synch field measurement lfdiv is an unsigned fixed point number. the mantissa is coded on 12 bits in the linibrr and the fraction is coded on 4 bits in the linfbrr. if lase bit = 1 then lfdiv is automatically updated at the end of each lin synch field. three internal registers (not user-accessible) manage the auto-update of the linflex divider (lfdiv): lfdiv_nom (nominal value written by soft ware at linibrr and linfbrr addresses) lfdiv_meas (results of th e field synch measurement) lfdiv (used to generate the local baud rate) on transition to idle, break or break delimiter state due to any error or on reception of a complete frame, hardware reloads lfdiv with lfdiv_nom. deviation error on the synch field the deviation error is checked by comparing the current baud rate (relative to the slave oscillator) with the received lin synch field (r elative to the master oscillator). two checks are performed in parallel. lin break break bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit lin synch field measurement = 8.t br =sm.t periph_set_1_clk lfdiv(n) lfdiv(n+1) lfdiv = t br / (16.t periph_set_1_clk ) = rounding (sm / 128) t periph_set_1_clk = clock period t br = baud rate period t br t br = 16.lfdiv.t periph_set_1_clk sm = synch measurement register (19 bits) delim. lin controller (linflex) RM0017 413/904 doc id 14629 rev 8 the first check is based on a measurement between the first falling edge and the last falling edge of the synch field: if d1 > 14.84%, lhe is set. if d1 < 14.06%, lhe is not set. if 14.06% < d1 < 14.84%, lhe can be either set or reset depending on the dephasing between the signal on linflex_rx pin the f periph_set_1_clk clock. the second check is based on a measurement of time betw een each falling edge of the synch field: if d2 > 18.75%, lhe is set. if d2 < 15.62%, lhe is not set. if 15.62% < d2 < 18.75%, lhe can be either set or reset depending on the dephasing between the signal on linflex_rx pin the f periph_set_1_clk clock. note that the linflex does not need to check if the next edge occurs slower than expected. this is covered by the check for deviation error on the full synch byte. clock gating the linflex clock can be gated from the mode entry module (mc_me). in lin mode, the linflex controller acknowledges a clock gating request once the frame transmission or reception is completed. 21.8.3 8-bit timeout counter lin timeout mode setting the ltom bit in the lintcsr enable s the lin timeout mode. the linocr becomes read-only, and oc1 and oc2 output compare values in the linocr are automatically updated by hardware. this configuration detects header timeout, response timeout, and frame timeout. depending on the lin mode (selected by the lincr1[mme] bit), the 8-bit timeout counter will behave differently. lin timeout mode must not be enabled during lin extended frames transmission or reception (that is, if the data field length in the bidr is configured with a value higher than 8 data bytes). lin master mode the lintocr[rto] field can be used to tune response timeout and frame timeout values. header timeout value is fixed to hto = 28-bit time. field oc1 checks t header and t response and field oc2 checks t frame (see figure 201 ). when linflex moves from break delimiter state to synch field state (see section , lin status register (linsr) ): oc1 is updated with the value of oc header (oc header = cnt + 28), oc2 is updated with the value of oc frame (oc frame =cnt+28+rto9 (frame timeout value for an 8-byte frame), the toce bit is set. RM0017 lin controller (linflex) doc id 14629 rev 8 414/904 on the start bit of the first response data byte (and if no error occurred during the header reception), oc1 is updated with the value of oc response (oc response = cnt + rto 9 (response timeout value for an 8-byte frame)). on the first response byte is received, oc1 and oc2 are automatically updated to check t response and t frame according to rto (tolerance) and dfl. on the checksum reception or in case of error in the header or response, the toce bit is reset. if there is no response, frame timeout value does not take into account the dfl value, and an 8-byte response (dfl = 7) is always assumed. lin slave mode the lintocr[rto] field can be used to tune response timeout and frame timeout values. header timeout value is fixed to hto. oc1 checks t header and t response and oc2 checks t frame (see figure 201 ). when linflex moves from break state to break delimiter state (see section , lin status register (linsr) ): oc1 is updated with the value of oc header (oc header =cnt+hto), oc2 is updated with the value of oc frame (oc frame =cnt+hto +rto9 (frame timeout value for an 8-byte frame)), the toce bit is set. on the start bit of the first response data byte (and if no error occurred during the header reception), oc1 is updated with the value of oc response (oc response = cnt + rto 9 (response timeout value for an 8-byte frame)). once the first response byte is received, oc1 and oc2 are automatically updated to check t response and t frame according to rto (tolerance) and dfl. on the checksum reception or in case of error in the header or data field, the toce bit is reset. figure 201. header and response timeout oc frame oc header oc response header response break frame oc1 oc2 response space lin controller (linflex) RM0017 415/904 doc id 14629 rev 8 output compare mode programming lintcsr[ltom] = 0 enables the output compare mode. this mode allows the user to fully customize the use of the counter. oc1 and oc2 output compare values can be updated in the lintocr by software. 21.8.4 interrupts table 200. linflex interrupt control interrupt event event flag bit enable control bit interrupt vector header received interrupt hrf hrie rxi (1) 1. in slave mode, if at least one filt er is configured as tx and enabled, header received interrupt vector is rxi or txi depending on the value of identifier received. data transmitted interrupt dtf dtie txi data received interrupt drf drie rxi data buffer empty interrupt dbef dbeie txi data buffer full interrupt dbff dbfie rxi wake-up interrupt wupf wupie rxi lin state interrupt (2) 2. for debug and validation purposes lsf lsie rxi buffer overrun interrupt bof boie err framing error interrupt fef feie err header error interrupt hef heie err checksum error interrupt cef ceie err bit error interrupt bef beie err output compare interrupt ocf ocie err stuck at zero interrupt szf szie err RM0017 flexcan doc id 14629 rev 8 416/904 22 flexcan 22.1 introduction the flexcan module is a communication controller implementing the can protocol according to the can 2.0b protocol specific ation. a general block diagram is shown in figure 202 , which describes the main sub-blocks implemented in the flexcan module, including two embedded memories, one for storing message buffers (mb) and another one for storing rx individual mask registers. support for up to 64 message buffers is provided. the functions of the submodules are described in subsequent sections. figure 202. flexcan block diagram 22.1.1 overview the can protocol was primarily, but not only, de signed to be used as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the emi environment of a vehicle, cost-effectiveness and required bandwidth. the flexcan module is a full implem entation of the can protocol specification, version 2.0 b, which supports both standard and extended message frames. a flexible number of message 288/544/1056- bus interface unit max mb # (0?63) ip bus interface can message can tx can rx mb1 mb0 mb62 mb63 clocks, address & data buses, interrupt and test signals buffer management protocol interface byte sram message buffer storage 64/128/256- rximr1 rximr0 rximr62 rximr63 byte sram id mask storage flexcan RM0017 417/904 doc id 14629 rev 8 buffers (16, 32 or 64) is also supported. the message buffers are stored in an embedded sram dedicated to the flexcan module. the can protocol interface (cpi) submodule manages the serial communication on the can bus, requesting sram access for receiving and transmitting message frames, validating received messages and performing error handling. the message buffer management (mbm) submodule handles message buffer selection for reception and transmission, taking care of arbitration and id matching algorithms. the bus interface unit (biu) submodule controls the access to and from the internal interface bus, in order to establish connection to the cpu and to other blocks. clocks, address and data buses, interrupt outputs and test signals are accessed through the bus interface unit. 22.1.2 flexcan module features the flexcan module includes these distinctive features: full implementation of the can protocol specification, version 2.0b ? standard data and remote frames ? extended data and remote frames ? 0?8 bytes data length ? programmable bit rate up to 1 mbit/s ? content-related addressing flexible message buffers (up to 64) of zero to eight bytes data length each mb configurable as rx or tx, all supporting standard and extended messages individual rx mask registers per message buffer includes either 1056 bytes (64 mbs) of sram used for mb storage includes either 256 bytes (64 mbs) of sram used for individual rx mask registers full featured rx fifo with storage capacity for 6 frames and internal pointer handling powerful rx fifo id filtering, capable of matching incoming ids against either 8 extended, 16 stan dard or 32 partial (8 bits) ids, with individual masking capability selectable backwards compatibilit y with previous flexcan version programmable clock source to the can protocol interface, either bus clock or crystal oscillator unused mb and rx mask register spac e can be used as general purpose sram space listen-only mode capability programmable loop-back mode supporting self-test operation programmable transmission priority scheme: lowest id, lowest buffer number or highest priority time stamp based on 16-bit free-running timer global network time, synchronized by a specific message maskable interrupts independent of the transmission medium (an external transceiver is assumed) short latency time due to an arbitration scheme for high-priority messages low power mode hardware cancellation on tx message buffers RM0017 flexcan doc id 14629 rev 8 418/904 22.1.3 modes of operation the flexcan module has four functional m odes: normal mode (user and supervisor), freeze mode, listen-only mode and loop-back mode. there is also a low power mode: disable mode. normal mode (user or supervisor) in normal mode, the module operates receiving and/or transmitting message frames, errors are handled normally and all the can protocol functions are enabled. user and supervisor modes differ in the access to some restricted control registers. freeze mode it is enabled when the frz bit in the mcr is asserted. if enabled, freeze mode is entered when the halt bit in mcr is set or when debug mode is requested at mcu level. in this mode, no transmission or reception of frames is done and synchronicity to the can bus is lost. see section freeze mode for more information. listen-only mode the module enters this mode when the lom bit in the control register is asserted. in this mode, transmission is disabled, all error counters are frozen and the module operates in a can error passive mode. only messages acknowledged by another can station will be received. if flexcan detects a message that has not been acknowledged, it will flag a bi t0 error (without changing the re c), as if it was trying to acknowledge the message. loop-back mode the module enters this mode when the lpb bi t in the control register is asserted. in this mode, flexcan performs an internal loop back that can be used for self test operation. the bit stream output of the transmitter is internally fed back to the receiver input. the rx can input pin is ignored and the tx can output goes to the recessive state (logic ?1?). flexcan behaves as it normally does when transmitting and treats its own transmitted message as a message received from a remote node. in this mode, flexcan ignores the bit sent during the ack slot in the can frame acknowledge field to ensure proper reception of its own message. both transmit and receive interrupts are generated. module disable mode this low power mode is entered when the mdis bit in the mcr is asserted. when disabled, the module shuts down the clocks to the can protocol interface and message buffer management submodules. exit from this mode is done by negating the mdis bit in the mcr. see section module disable mode for more information. 22.2 external signal description 22.2.1 overview the flexcan module has two i/o signals c onnected to the external mcu pins. these signals are summarized in table 201 and described in more detail in the next subsections. flexcan RM0017 419/904 doc id 14629 rev 8 22.2.2 signal descriptions can rx this pin is the receive pin from the can bus transceiver. dominant state is represented by logic level ?0?. recessive state is represented by logic level ?1?. can tx this pin is the transmit pin to the can bus transceiver. dominant state is represented by logic level ?0?. recessive state is represented by logic level ?1?. 22.3 memory map and register description this section describes the registers and data structures in the flexcan module. the base address of the module depends on the particular memory map of the mcu. the addresses presented here are relative to the base address. the address space occupied by flexcan has 96 bytes for registers starting at the module base address, followed by mb storage space in embedded sram starting at address 0x0060, and an extra id mask storage space in a separate embedded sram starting at address 0x0880. 22.3.1 flexcan memory mapping the complete memory map for a flexcan m odule with 64 mbs capa bility is shown in table 202 . each individual register is identified by its complete name and the corresponding mnemonic. the access type can be supervisor (s) or unrestricted (u). most of the registers can be configured to have either supervisor or unrestricted access by programming the supv bit in the mcr. these registers are identified as s/u in the access column of table 202 . the iflag2 and imask2 regist ers are considered reserved space when flexcan is configured with 16 or 32 mbs. the rx glob al mask (rxgmask), rx buffer 14 mask (rx14mask) and the rx buffer 15 mask (rx15mask) registers are provided for backwards compatibility, and are not used when the bcc bit in mcr is asserted. the address ranges 0x0060?0x047f and 0x0880?0x097f are occupied by two separate embedded memories. these two ranges are completely occupied by sram (1056 and 256 bytes, respectively) only when flexcan is conf igured with 64 mbs. when it is configured with 16 mbs, the memory sizes are 288 and 64 bytes, so the address ranges 0x0180? 0x047f and 0x08c0?0x097f are considered reserved space. when it is configured with 32 mbs, the memory sizes are 544 and 128 bytes, so the address ranges 0x0280?0x047f and 0x0900?0x097f are considered reserved space. furthermore, if the bcc bit in mcr is table 201. flexcan signals signal name (1) 1. the actual mcu pins may have different names. direction description can rx input can receive pin can tx output can transmit pin RM0017 flexcan doc id 14629 rev 8 420/904 negated, then the whole rx individual mask registers address range (0x0880?0x097f) is considered reserved space. the flexcan module stores can messages for transmission and reception using a message buffer structure. each individual mb is formed by 16 bytes mapped on memory as described in ta b l e 2 0 3 . ta b l e 2 0 3 shows a standard/extended message buffer (mb0) memory map, using 16 bytes total (0x80 ? 0x8f space). table 202. flexcan memory map base addresses: 0xfffc_0000 (flexcan_0) 0xfffc_4000 (flexcan_1) 0xfffc_8000 (flexcan_2) 0xfffc_c000 (flexcan_3) 0xfffd_0000 (flexcan_4) 0xfffd_4000 (flexcan_5) address offset register location 0x0000 module configuration (mcr) on page 22-426 0x0004 control register (ctrl) on page 22-430 0x0008 free running timer (timer) on page 22-433 0x000c reserved 0x0010 rx global mask (rxgmask) on page 22-434 0x0014 rx buffer 14 mask (rx14mask) on page 22-435 0x0018 rx buffer 15 mask (rx15mask) on page 22-435 0x001c error counter register (ecr) on page 22-436 0x0020 error and status register (esr) on page 22-437 0x0024 interrupt masks 2 (imask2) on page 22-440 0x0028 interrupt masks 1 (imask1) on page 22-441 0x002c interrupt flags 2 (iflag2) on page 22-442 0x0030 interrupt flags 1 (iflag1) on page 22-443 0x0034?0x005f reserved 0x0060?0x007f reserved 0x0080?0x017f message buffers mb0 ? mb15 0x0180?0x027f message buffers mb16 ? mb31 0x0280?0x047f message buffers mb32 ? mb63 0x0480?0x087f reserved 0x0880?0x08bf rx individual mask registers rximr0?rximr15 on page 22-444 0x08c0?0x08ff rx individual mask registers rximr16?rximr31 on page 22-444 0x0900?0x097f rx individual mask registers rximr32?rximr63 on page 22-444 flexcan RM0017 421/904 doc id 14629 rev 8 22.3.2 message buffer structure the message buffer structure used by the flexcan module is represented in table 203 . both extended and standard frames (29-bit identifier and 11-bit identifier, respectively) used in the can specification (version 2.0 part b) are represented. table 203. message buf fer mb0 memory mapping address offset mb field 0x80 control and status (c/s) 0x84 identifier field 0x88 ? 0x8f data field 0 ? data field 7 (1 byte each) figure 203. message buffer structure 012345678910111213141516171819202122232425262728293031 0x0 code srr ide rtr length time stamp 0x4 prio id (standard/extended) id (extended) 0x8 data byte 0 data byte 1 data byte 2 data byte 3 0x c data byte 4 data byte 5 data byte 6 data byte 7 = unimplemented or reserved table 204. message buffer structure field description field description code message buffer code this 4-bit field can be accessed (read or write) by the cpu and by the flexcan module itself, as part of the message buffer matching and arbitration process. the encoding is shown in table 205 and ta bl e 2 0 6 . see section 22.4 functional description for additional information. srr substitute re mote request fixed recessive bit, used only in extended format. it must be set to ?1? by the user for transmission (tx buffers) and will be stored with the value received on the can bus for rx receiving buffers. it can be received as either recessive or dominant. if flexcan receives this bit as dominant, then it is interpreted as arbitration loss. 1 = recessive value is compulsory for transmission in extended format frames 0 = dominant is not a valid value for transmission in extended format frames ide id extended bit this bit identifies whether the fram e format is standard or extended. 1 = frame format is extended 0 = frame format is standard RM0017 flexcan doc id 14629 rev 8 422/904 rtr remote transmission request this bit is used for requesting transmissions of a data frame. if flexcan transmits this bit as ?1? (recessive) and receives it as ?0? (dominant), it is interpreted as arbitration loss. if this bit is transmitted as ?0? (dominant), then if it is rece ived as ?1? (recessive), the flexcan module treats it as bit error. if the value received matches the valu e transmitted, it is considered as a successful bit transmission. 1 = indicates the current mb has a remote frame to be transmitted 0 = indicates the current mb has a data frame to be transmitted length length of data in bytes this 4-bit field is the length (in bytes) of the rx or tx data, which is loca ted in offset 0x8 through 0xf of the mb space (see ta bl e 2 0 3 ). in reception, this field is written by the flexcan module, copied from the dlc (data length code) field of the received frame. in transmission, this field is written by the cpu and corresponds to the dlc fi eld value of the frame to be transmitted. when rtr=1, the frame to be transmitted is a remote frame and does not include the data field, regardless of the length field. time stamp free-running counter time stamp this 16-bit field is a copy of the free-running ti mer, captured for tx and rx frames at the time when the beginning of the identifier field appears on the can bus. prio local priority this 3-bit field is only used when lprio_en bit is set in mcr and it only makes sense for tx buffers. these bits are not transmitted. they are appended to the regular id to define the transmission priority. see section 22.4.4 arbitration process . id frame identifier in standard frame format, only the 11 most si gnificant bits (3 to 13) are used for frame identification in both receive and transmit cases. the 18 least significant bits are ignored. in extended frame format, all bits are used for fr ame identification in both receive and transmit cases. data data field up to eight bytes can be used for a data frame. for rx frames, the data is stored as it is received from the can bus. for tx frames, the cpu pre pares the data field to be transmitted within the frame. table 204. message buffer structure field description (continued) field description flexcan RM0017 423/904 doc id 14629 rev 8 table 205. message buffer code for rx buffers rx code before rx new frame description rx code after rx new frame comment 0000 inactive: mb is not active. ? mb does not participate in the matching process. 0100 empty: mb is active and empty. 0010 mb participates in the matching process. when a frame is received successfully, the code is automatically updated to full. 0010 full: mb is full. 0010 the act of reading the c/s word followed by unlocking the mb does not make the code return to empty. it remains full. if a new frame is written to the mb after the c/s word was read and the mb was unlocked, the code still remains full. 0110 if the mb is full and a new frame is overwritten to this mb before the cpu had time to read it, the code is automatically updated to overrun. refer to section 22.4.6 matching process for details about overrun behavior. 0110 overrun: a frame was overwritten into a full buffer. 0010 if the code indicates overrun but the cpu reads the c/s word and then unlocks the mb, when a new frame is written to the mb the code returns to full. 0110 if the code already indicates overrun, and yet another new frame must be written, the mb will be overwritten again, and the code will remain overrun. refer to section 22.4.6 matching process for details about overrun behavior. 0xy1 (1) 1. note that for tx mbs (see table 206 ), the busy bit should be ignored upon read, ex cept when aen bit is set in the mcr. busy: flexcan is updating the contents of the mb. the cpu must not access the mb. 0010 an empty buffer was written with a new frame (xy was 01). 0110 a full/overrun buffer was overwritten (xy was 11). table 206. message buffer code for tx buffers rtr initial tx code code after successful transmission description x 1000 ? inactive: mb does not participate in the arbitration process. x 1001 ? abort: mb was configured as tx and cpu aborted the transmission. this code is only valid when aen bit in mcr is asserted. mb does not participate in the arbitration process. 0 1100 1000 transmit data frame unconditionally once. after transmission, the mb automatically returns to the inactive state. RM0017 flexcan doc id 14629 rev 8 424/904 22.3.3 rx fifo structure when the fen bit is set in the mcr, the memory area from 0x80 to 0xfc (which is normally occupied by mbs 0 to 7) is used by the reception fifo engine. ta b l e 2 0 4 shows the rx fifo data structure. the region 0x80?0x8c c ontains an mb structure which is the port through which the cpu reads data from the fifo (the oldest frame received and not read yet). the region 0x90?0xdc is reserved for in ternal use of the fifo engine. the region 0xe0?0xfc contains an 8-entry id table that specifies filtering criteria for accepting frames into the fifo. ta b l e 2 0 5 shows the three different formats that the elements of the id table can assume, depending on the idam field of the mcr. note that all elements of the table must have the same format. see section 22.4.8 rx fifo for more information. 1 1100 0100 transmit remote frame unconditionally once. after transmission, the mb automatically becomes an rx mb with the same id. 0 1010 1010 transmit a data frame whenever a remote request frame with the same id is received. this mb participates simultaneously in both the matching and arbitration processes. the matching process compares the id of the incoming remote request frame with the id of the mb. if a match occurs this mb is allowed to participate in the current arbitration process and the code field is automatically updated to ?1110? to allow the mb to participate in future arbitration runs. when the frame is eventually transmitted successfully, the code automatically returns to ?1010? to restart the process again. 0 1110 1010 this is an intermediate code that is automatically written to the mb by the mbm as a result of match to a remote request frame. the data frame will be transmitted unconditionally once and then the code will automatically return to ?1010?. the cpu can also write this code with the same effect. table 206. message buffer code for tx buffers (continued) rtr initial tx code code after successful transmission description flexcan RM0017 425/904 doc id 14629 rev 8 figure 204. rx fifo structure 012345678910111213141516171819202122232425262728293031 0x80 srr ide rtr length time stamp 0x84 id (standard/extended) id (extended) 0x88 data byte 0 data byte 1 data byte 2 data byte 3 0x8c data byte 4 data byte 5 data byte 6 data byte 7 0x90 reserved to 0xdc 0xe0 id table 0 0xe4 id table 1 0xe8 id table 2 0xec id table 3 0xf0 id table 4 0xf4 id table 5 0xf8 id table 6 0xfc id table 7 = unimplemented or reserved figure 205. id table 0 ? 7 012345678910111213141516171819202122232425262728293031 a rem ext rxida (standard = 2-12, extended = 2-30) b rem ext rxidb_0 (standard =2-12, extended = 2-15) rem ext rxidb_1 (standard = 18-28, extended = 18-31) c rxidc_0 (std/ext = 0-7) rxidc_1 (std/ext = 8-15) rxidc_2 (std/ext = 16-23) rxidc_3 (std/ext = 24-31) = unimplemented or reserved RM0017 flexcan doc id 14629 rev 8 426/904 22.3.4 register description the flexcan registers are described in this section in ascending address order. module configuration register (mcr) this register defines global system configur ations, such as the module operation mode (e.g., low power) and maximum message buffer configuration. this register can be accessed at any time, however some fields must be changed only during freeze mode. find more information in the fields descriptions ahead. table 207. rx fifo stru cture field description field description rem remote frame this bit specifies if remote frames are accept ed into the fifo if they match the target id. 1 = remote frames can be accepted and data frames are rejected 0 = remote frames are rejected and data frames can be accepted ext extended frame specifies whether extended or standard frames are ac cepted into the fifo if they match the target id. 1 = extended frames can be accepted and standard frames are rejected 0 = extended frames are rejected and standard frames can be accepted rxida rx frame identifier (format a) specifies an id to be used as acceptance criteria for the fifo. in the standard frame format, only the 11 most significant bits (3 to 13)are used for frame identification. in the extended frame format, all bits are used. rxidb_0, rxidb_1 rx frame identifier (format b) specifies an id to be used as acceptance criter ia for the fifo. in the standard frame format, the 11 most significant bits (a full standard id) (3 to 13)are used for frame identification. in the extended frame format, all 14 bits of the field are compared to the 14 most significant bits of the received id. rxidc_0, rxidc_1, rxidc_2, rxidc_3 rx frame identifier (format c) specifies an id to be used as acceptance cr iteria for the fifo. in both standard and extended frame formats, all 8 bits of the field are compared to the 8 most significant bits of the received id. flexcan RM0017 427/904 doc id 14629 rev 8 figure 206. module configuration register (mcr) offset: 0x0000 access: read/write 0123456789101112131415 r mdis frz fen halt not_rdy 0 soft_rst frz_ack supv 0 wrn_en lpm_ack 00 srx_dis bcc w reset note (1) 1. reset value of this bit is different on various platforms. consult the specific mcu document ation to determine its value. 101100 note (2) 2. different on various platforms, but it is always the opposite of the mdis reset value. 100 note (3) 3. different on various platforms, but it is always the same as the mdis reset value. 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 lprio_en aen 00 idam 00 maxmb w reset 0000000000001111 table 208. mcr field descriptions field description mdis module disable this bit controls whether flexcan is enabled or not. when disabled, flexcan shuts down the clocks to the can protocol interface and messa ge buffer management submodules. this is the only bit in mcr not affected by soft reset. see section module disable mode for more information. 1 = disable the flexcan module 0 = enable the flexcan module frz freeze enable the frz bit specifies the flexcan behavior when the halt bit in the mcr is set or when debug mode is requested at mcu level. when frz is asserted, flexcan is enabled to enter freeze mode. negation of this bit field causes flexcan to exit from freeze mode. 1 = enabled to enter freeze mode 0 = not enabled to enter freeze mode fen fifo enable this bit controls whether the fifo feature is enabled or not. when fen is set, mbs 0 to 7 cannot be used for normal reception and transmission because the corresponding memory region (0x80? 0xff) is used by the fifo engine. see section 22.3.3 rx fifo structure and section 22.4.8 rx fifo for more information. this bit must be written in freeze mode only. 1 = fifo enabled 0 = fifo not enabled RM0017 flexcan doc id 14629 rev 8 428/904 halt halt flexcan assertion of this bit puts the flexcan module into freeze mode. the cpu should clear it after initializing the message buffers and control register. no reception or transmission is performed by flexcan before this bit is cleared. while in freeze mode, the cpu has write access to the error counter register, that is otherwise read-only. freeze mode cannot be entered while flexcan is in the low power mode. see section freeze mode for more information. 1 = enters freeze mode if the frz bit is asserted. 0 = no freeze mode request. not_rdy flexcan not ready this read-only bit indicates that flexcan is either in disable mode or freeze mode. it is negated once flexcan has exited these modes. 1 = flexcan module is either in disable mode or freeze mode 0 = flexcan module is either in normal mode, listen-only mode or loop-back mode soft_rst soft reset when this bit is asserted, flexcan resets its internal state machines and some of the memory mapped registers. the following registers are re set: mcr (except the mdis bit), timer, ecr, esr, imask1, imask2, iflag1, iflag2 . configuration registers that control the interface to the can bus are not affected by soft reset. the following registers are unaffected: ?ctrl ? rximr0?rximr63 ? rxgmask, rx14mask, rx15mask ? all message buffers the soft_rst bit can be asserted directly by the cpu when it writes to the mcr, but it is also asserted when global soft reset is requested at mcu level. since soft reset is synchronous and has to follow a request/acknowledge procedure across clock domains, it may take some time to fully propagate its effect. the soft_rst bit rema ins asserted while reset is pending, and is automatically negated when reset completes. theref ore, software can poll this bit to know when the soft reset has completed. soft reset cannot be applied while clocks are shut down in the low power mode. the module should be first removed from low power mode, and then soft reset can be applied. 1 = resets the registers marked as ?affected by soft reset? in ta bl e 2 0 2 0 = no reset request frz_ack freeze mode acknowledge this read-only bit indicates that flexcan is in freeze mode and its prescaler is stopped. the freeze mode request cannot be granted until current transmission or reception processes have finished. therefore the software can poll the fr z_ack bit to know when flexcan has actually entered freeze mode. if freeze mode request is negated, then this bit is negated once the flexcan prescaler is running again. if freeze mode is requested while flexcan is in the low power mode, then the frz_ack bit will only be set when the low power mode is exited. see section freeze mode for more information. 1 = flexcan in freeze mode, prescaler stopped 0 = flexcan not in freeze mode, prescaler running table 208. mcr field de scriptions (continued) field description flexcan RM0017 429/904 doc id 14629 rev 8 supv supervisor mode this bit configures some of the flexcan regist ers to be either in supervisor or unrestricted memory space. the regist ers affected by this bit are marked as s/u in the access type column of ta b l e 2 0 2 . reset value of this bit is ?1?, so the affected registers start with supervisor access restrictions.this bit should be written in freeze mode only. 1 = affected registers are in su pervisor memory space. any access without supervisor permission behaves as though the access was done to an unimplemented register location 0 = affected registers are in unrestricted memory space wrn_en warning interrupt enable when asserted, this bit enables the generation of the twrn_int and rwrn_int flags in the error and status register. if wrn_en is neg ated, the twrn_int and rwrn_int flags will always be zero, independent of the values of the error counters, and no warning interrupt will ever be generated. this bit must be written in freeze mode only. 1 = twrn_int and rwrn_int bits are set when the respective error counter transition from < 96 to 96. 0 = twrn_int and rwrn_int bits are zero, independent of the values in the error counters. lpm_ack low power mode acknowledge this read-only bit indicates that flexcan is in disable mode. this low power mode cannot be entered until all current transmission or reception processes have finished, so the cpu can poll the lpm_ack bit to know when flexcan has actually entered low power mode. see section module disable mode for more information. 1 = flexcan is in disable mode. 0 = flexcan is not in disable mode srx_dis self reception disable this bit defines whether flexcan is allowed to receive frames transmitted by itself. if this bit is asserted, frames transmitted by the module will no t be stored in any mb, regardless if the mb is programmed with an id that matches the transmitted frame, and no interrupt flag or interrupt signal will be generated due to the frame reception. this bit must be written in freeze mode only. 1 = self reception disabled 0 = self reception enabled bcc backwards compatibility configuration this bit is provided to support backwards compatibility with previous flexcan versions. when this bit is negated, the following configuration is applied: ? for mcus supporting individual rx id masking, th is feature is disabled. instead of individual id masking per mb, flexcan uses its previous masking scheme with rxgmask, rx14mask and rx15mask. ? the reception queue feature is disabled. upon receiving a message, if the first mb with a matching id that is found is still occupied by a previous unread message, flexcan will not look for another matching mb. it will override this mb with the new message and set the code field to ?0110? (overrun). upon reset this bit is negated, allowing legacy software to work without modification. this bit must be written in freeze mode only. 1 = individual rx masking and queue feature are enabled. 0 = individual rx masking and queue feature are disabled. table 208. mcr field de scriptions (continued) field description RM0017 flexcan doc id 14629 rev 8 430/904 control register (ctrl) this register is defined for specific flexcan control features related to the can bus, such as bit-rate, programmable sampling point within an rx bit, loop-back mode, listen-only mode, bus off recovery behavior and interrupt enabling (bus-off, error, warning). it also determines the division factor for the clock prescaler. this register can be accessed at any time, however some fields must be changed only during either disable mode or freeze mode. find more information in the fields descriptions ahead. lprio_en local priority enable this bit is provided for backwards compatibility r easons. it controls whet her the local priority feature is enabled or not. it is used to extend th e id used during the arbitration process. with this extended id concept, the arbitration process is done based on the full 32-bit word, but the actual transmitted id still has 11-bit for standard frames and 29-bit for extended frames. this bit must be written in freeze mode only. 1 = local priority enabled 0 = local priority disabled 19 aen abort enable this bit is supplied for backwards compatibility reasons. when asserted, it enables the tx abort feature. this feature guarantees a safe procedure for aborting a pending transmission, so that no frame is sent in the can bus without notification. this bit must be written in freeze mode only. 1 = abort enabled 0 = abort disabled idam id acceptance mode this 2-bit field identifies the format of the elem ents of the rx fifo filter table, as shown in ta b l e 2 0 9 . note that all elements of the table are configured at the same time by this field (they are all the same format). see section 22.3.3 rx fifo structure . this bit must be written in freeze mode only. maxmb maximum number of message buffers this 6-bit field defines the maximum number of me ssage buffers that will take part in the matching and arbitration processes. the reset value (0x0f) is equivalent to 16 mb configuration. this field must be changed only while the module is in freeze mode. maximum mbs in use = maxmb + 1 note: maxmb must be programmed with a value smaller or equal to the number of available message buffers, otherwise flexcan can transmit and receive wrong messages. table 209. idam coding idam format explanation 00 a one full id (standard or extended) per filter element 01 b two full standard ids or two partial 14-bit extended ids per filter element 10 c four partial 8-bit ids (standard or extended) per filter element 11 d all frames rejected table 208. mcr field de scriptions (continued) field description flexcan RM0017 431/904 doc id 14629 rev 8 figure 207. control register (ctrl) offset: 0x0004 access: read/write 0123 4 5 6789101112131415 r presdiv rjw pseg1 pseg2 w reset0000 0 0 0000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r boff_msk err_ msk clk_src lpb twrn_msk rwrn_msk 00 smp boff_rec tsyn lbuf lom propseg w reset0000 0 0 0000000000 table 210. ctrl field descriptions field description presdiv prescaler division factor this field defines the ratio between the cpi cl ock frequency and the serial clock (sclock) frequency. the sclock period defines the time quantum of the can protocol. for the reset value, the sclock frequency is equal to the cpi clock frequ ency. the maximum value of this register is 0xff, that gives a minimum sclock frequency equal to the cpi clock frequency divided by 256. for more information refer to section protocol timing . this bit must be written in freeze mode only. sclock frequency = cpi clock frequency / (presdiv + 1) rjw resync jump width this field defines the maximum number of time quanta (1) that a bit time can be changed by one resynchronization. the valid programmable values are 0 ? 3. this bit must be written in freeze mode only. resync jump width = rjw + 1. pseg1 pseg1 ? phase segment 1 this field defines the length of phase buffer se gment 1 in the bit time. the valid programmable values are 0 ? 7. this bit must be written in freeze mode only. phase buffer segment 1 = (pseg1 + 1) x time-quanta. pseg2 pseg2 ? phase segment 2 this field defines the length of phase buffer se gment 2 in the bit time. the valid programmable values are 1 ? 7. this bit must be written in freeze mode only. phase buffer segment 2 = (pseg2 + 1) x time-quanta. boff_msk bus off mask this bit provides a mask for the bus off interrupt. 1= bus off interrupt enabled 0 = bus off interrupt disabled RM0017 flexcan doc id 14629 rev 8 432/904 err_msk error mask this bit provides a mask for the error interrupt. 1 = error interrupt enabled 0 = error interrupt disabled clk_src can engine clock source this bit selects the clock source to the can prot ocol interface (cpi) to be either the peripheral clock (driven by the fmpll) or the crystal oscillat or clock. the selected cloc k is the one fed to the prescaler to generate the serial clock (sclock). in order to guarantee reliable operation, this bit should only be changed while the module is in disable mode. see section protocol timing for more information. 1 = the can engine clock source is the bus clock 0 = the can engine clock source is the oscillator clock note: this clock selection feature may not be available in all mcus. a particular mcu may not have a fmpll, in which case it would have only the oscillator clock, or it may use only the fmpll clock feeding the flexcan module. in t hese cases, this bit has no effect on the module operation. lpb loop back this bit configures flexcan to operate in loop- back mode. in this mode, flexcan performs an internal loop back that can be used for self test operation. the bit stream output of the transmitter is fed back internally to the receiver input. the rx can input pin is ignored and the tx can output goes to the recessive state (logic ?1?). flexcan behaves as it normally does when transmitting, and treats its own transmitted message as a message received from a remote node. in this mode, flexcan ignores the bit sent during the ack slot in the can frame acknowledge field, generating an internal acknowledge bit to ensure proper reception of its own message. both transmit and receive interrupts are generated. this bit must be written in freeze mode only. 1 = loop back enabled 0 = loop back disabled twrn_msk tx warning interrupt mask this bit provides a mask for the tx warning interrupt associated with the twrn_int flag in the error and status register. this bit has no effect if the wrn_en bit in mcr is negated and it is read as zero when wrn_en is negated. 1 = tx warning interrupt enabled 0 = tx warning interrupt disabled rwrn_msk rx warning interrupt mask this bit provides a mask for the rx warning in terrupt associated with the rwrn_int flag in the error and status register. this bit has no effect if the wrn_en bit in mcr is negated and it is read as zero when wrn_en is negated. 1 = rx warning interrupt enabled 0 = rx warning interrupt disabled smp sampling mode this bit defines the sampling mode of can bits at th e rx input. this bit must be written in freeze mode only. 1 = three samples are used to determine the value of the received bit: the regular one (sample point) and two preceding samples, a majority rule is used 0 = just one sample is used to determine the bit value table 210. ctrl field descriptions (continued) field description flexcan RM0017 433/904 doc id 14629 rev 8 free running timer (timer) this register represents a 16-bit free running counter that can be read and written by the cpu. the timer starts from 0x0000 after reset, counts linearly to 0xffff, and wraps around. boff_rec bus off recovery mode this bit defines how flexcan recovers from bu s off state. if this bit is negated, automatic recovering from bus off state occurs according to the can specificatio n 2.0b. if the bit is asserted, automatic recovering from bus off is disabled and the module remains in bus off state until the bit is negated by the user. if the negation occurs before 128 sequences of 11 recessive bits are detected on the can bus, then bus off recovery happens as if the boff_rec bit had never been asserted. if the negation occurs after 128 sequences of 11 recessive bits occurred, then flexcan will resynchronize to the bus by waiting for 11 recessive bits before joining the bus. after negation, the boff_rec bit can be re-asser ted again during bus off, but it will only be effective the next time the module enters bus off. if boff_rec was negated when the module entered bus off, asserting it during bus off will no t be effective for the current bus off recovery. 1 = automatic recovering from bus off state disabled 0 = automatic recovering from bus off state enabled, according to can spec 2.0 part b tsyn timer sync mode this bit enables a mechanism that resets the free-running timer each time a message is received in message buffer 0. this feature provides means to synchronize multiple flexcan stations with a special ?sync? message (that is, global networ k time). if the fen bit in mcr is set (fifo enabled), mb8 is used for timer synchronization instead of mb0. this bit must be written in freeze mode only. 1 = timer sync feature enabled 0 = timer sync feature disabled lbuf lowest buffer tr ansmitted first this bit defines the ordering mechanism for message buffer transmission. when asserted, the lprio_en bit does not affect the priority arbitrat ion. this bit must be written in freeze mode only. 1 = lowest number buffer is transmitted first 0 = buffer with highest priority is transmitted first lom listen-only mode this bit configures flexcan to operate in li sten-only mode. in this mode, transmission is disabled, all error counters are frozen and the module operates in a can error passive mode. only messages acknowledged by another can station will be received. if flexcan detects a message that has not been acknowledged, it will flag a bit0 error (without changing the rec), as if it was trying to acknowledge the message. this bit must be written in freeze mode only. 1 = flexcan module operates in listen-only mode 0 = listen-only mode is deactivated propseg propagation segment this field defines the length of the prop agation segment in the bit time. the valid programmable values are 0?7. this bit must be written in freeze mode only. propagation segment time = (propseg + 1) * time-quanta. time-quantum = one sclock period. 1. one time quantum is equal to the sclock period. table 210. ctrl field descriptions (continued) field description RM0017 flexcan doc id 14629 rev 8 434/904 the timer is clocked by the flexcan bit-clock (which defines the baud rate on the can bus). during a message transmission/reception, it incr ements by one for each bit that is received or transmitted. when there is no message on the bus, it counts using the previously programmed baud rate. during freeze mode, the timer is not incremented. the timer value is captured at the beginning of the identifier field of any frame on the can bus. this captured value is written into the time stamp entry in a message buffer after a successful reception or tr ansmission of a message. writing to the timer is an indirect operation. the data is first written to an auxiliary register and then an internal request/acknowledge proc edure across clock domains is executed. all this is transparent to the user, except for the fact that the da ta will take some time to be actually written to the register. if desired, software can poll the register to discover when the data was actually written. rx global mask (rxgmask) this register is provided for legacy support and for low cost mcus that do not have the individual masking per message buffer feature. for mcus supporting individual masks per mb, setting the bcc bit in mcr causes the rxgmask register to have no effect on the module operation. for mcus not supporting indivi dual masks per mb, this register is always effective. rxgmask is used as acceptance mask for all rx mbs, excluding mbs 14 ? 15, which have individual mask registers. when the fen bit in mcr is set (fifo enabled), the rxgmask also applies to all elements of the id filter table, except elements 6?7, which have individual masks. refer to section 22.4.8 rx fifo for important details on us age of rxgmask on filtering process for rx fifo. the contents of this register must be programmed while the module is in freeze mode, and must not be modified when the module is transmitting or receiving frames. figure 208. free running timer (timer) offset: 0x0008 access: read/write 0123456789101112131415 r0000000000000000 w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r timer w reset 0000000000000000 flexcan RM0017 435/904 doc id 14629 rev 8 rx 14 mask (rx14mask) this register is provided for legacy support and for low cost mcus that do not have the individual masking per message buffer feature. for mcus supporting individual masks per mb, setting the bcc bit in mcr causes the rx 14mask register to have no effect on the module operation. rx14mask is used as acceptance mask for the identifier in message buffer 14. when the fen bit in mcr is set (fifo en abled), the rxg14mask also applies to element 6 of the id filter table. this register has the same structure as the rx global mask register. refer to section 22.4.8 rx fifo for important details on usa ge of rx14mask on filtering process for rx fifo. it must be programmed while the module is in freeze mode, and must not be modified when the module is transmitti ng or receiving frames. address offset: 0x14 reset value: 0xffff_ffff rx 15 mask (rx15mask) this register is provided for legacy support and for low cost mcus that do not have the individual masking per message buffer feature. for mcus supporting individual masks per mb, setting the bcc bit in mcr causes the rx 15mask register to have no effect on the module operation. figure 209. rx global mask register (rxgmask) offset: 0x0010 access: read/write 0123456789101112131415 r mi31 mi30 mi29 mi28 mi27 mi26 mi25 mi24 mi23 mi22 mi21 mi20 mi19 mi18 mi17 mi16 w reset1111111111111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r mi15 mi14 mi13 mi12 mi11 mi10 mi9 mi8 mi7 mi6 mi5 mi4 mi3 mi2 mi1 mi0 w reset1111111111111111 table 211. rxgmask field description field description mi31?mi0 mask bits for normal rx mbs, the mask bits affect the id fi lter programmed on the mb. for the rx fifo, the mask bits affect all bits programmed in the filter table (id, ide, rtr). 1 = the corresponding bit in the filter is checked against the one received 0 = the corresponding bit in the filter is ?don?t care? RM0017 flexcan doc id 14629 rev 8 436/904 when the bcc bit is negated, rx15mask is used as acceptance mask for the identifier in message buffer 15. when the fe n bit in mcr is set (fifo enabled), the rxg14mask also applies to element 7 of the id filter table. this register has the same structure as the rx global mask register. see section 22.4.8 rx fifo for important details on us age of rxg15mask on filtering process for rx fifo. it must be programmed while the module is in freeze mode, and must not be modified when the module is transmitti ng or receiving frames. address offset: 0x18 reset value: 0xffff_ffff error counter register (ecr) this register has two 8-bit fields reflecting the value of two flexcan error counters: transmit error counter (tx_err_counter fi eld) and receive error counter (rx_err_counter field). the rules for incr easing and decreasing these counters are described in the can protocol and are completely implemented in the flexcan module. both counters are read only except in freeze mode, where they can be written by the cpu. writing to the error counter register while in freeze mode is an indirect operation. the data is first written to an auxiliary register and then an internal request/acknowledge procedure across clock domains is executed. all this is transparent to the user, except for the fact that the data will take some ti me to be actually written to the r egister. if desired, software can poll the register to discover when the data was actually written. flexcan responds to any bus state as described in the protocol, e.g. transmit ?error active? or ?error passive? flag, delay its transmission start time (?error passive?) and avoid any influence on the bus when in ?bus off? stat e. the following are the basic rules for flexcan bus state transitions. if the value of tx_err_counter or rx_err_counter increases to be greater than or equal to 128, the flt_conf field in the error and status register is updated to reflect ?error passive? state. if the flexcan state is ?error pass ive?, and either tx_err_counter or rx_err_counter decrements to a value less than or equal to 127 while the other already satisfies this condition, the flt_conf field in the error and status register is updated to reflect ?error active? state. if the value of tx_err_counter increases to be greater than 255, the flt_conf field in the error and status register is updated to reflect ?bus off? state, and an interrupt may be issued. the value of tx_err_counter is then reset to zero. if flexcan is in ?bus off? state, then tx_err_counter is ca scaded together with another internal counter to count the 128th occurrences of 11 consecutive recessive bits on the bus. hence, tx_err_counter is reset to zero and counts in a manner where the internal counter counts 11 such bits and then wraps around while incrementing the tx_err_counter. when tx_err_counter reaches the value of 128, the flt_conf field in the error and status register is updated to be ?error active? and both error counters are reset to zero. at any instance of dominant bit following a stream of less than 11 consecutive recessive bits, the internal counter resets itself to zero without affecting the tx_err_counter value. if during system start-up, only one node is operating, then its tx_err_counter increases in each message it is trying to transmit, as a result of acknowledge errors (indicated by the ack_err bit in the error and status register). after the transition to flexcan RM0017 437/904 doc id 14629 rev 8 ?error passive? state, the tx_err_counter does not increment anymore by acknowledge errors. therefore the device never goes to the ?bus off? state. if the rx_err_counter increases to a value greater than 127, it is not incremented further, even if more errors are detected while being a receiver. at the next successful message reception, the counter is set to a value between 119 and 127 to resume to ?error active? state. error and status register (esr) this register reflects various error conditions, some general status of the device and it is the source of four interrupts to the cpu. the reported error conditions (bits 16?21) are those that occurred since the last time the cpu read this register. the cpu read action clears bits 16?23. bits 22?28 are status bits. most bits in this register are read only, except twrn_int, rwrn_int, boff_int, wak_int and err_int, that are interrupt flags that can be cleared by writing ?1? to them (writing ?0? has no effect). see section 22.4.11 interrupts for more details. figure 210. error counter register (ecr) offset: 0x001c access: read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rx_err_counter tx_err_counter w reset0000000000000000 RM0017 flexcan doc id 14629 rev 8 438/904 figure 211. error and status register (esr) offset: 0x0020 access: read/write 0123456789101112131415 r00000000000000 twrn_int rwrn_int w reset00000000000000 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r bit1_ err bit0_ err ack_ err crc_err frm_err stf_err tx_wrn rx_wrn idle txrx flt_conf 0 boff_int err_ int 0 w reset00000000000000 0 0 = unimplemented or reserved table 212. esr field descriptions field description twrn_int tx warning interrupt flag if the wrn_en bit in mcr is asserted, the twrn_int bit is set when the tx_wrn flag transition from ?0? to ?1?, meaning that the tx error co unter reached 96. if the corresponding mask bit in the control register (twrn_msk) is se t, an interrupt is generated to the cpu. this bit is cleared by writing it to ?1?. writ ing ?0? has no effect. 1 = the tx error counter transition from < 96 to 96 0 = no such occurrence rwrn_int rx warning interrupt flag if the wrn_en bit in mcr is asserted, the rwrn_ int bit is set when the rx_wrn flag transition from ?0? to ?1?, meaning that the rx error counters reached 96. if the corresponding mask bit in the control register (rwrn_msk) is set, an interrupt is generated to the cpu. this bit is cleared by writing it to ?1?. writ ing ?0? has no effect. 1 = the rx error counter transition from < 96 to 96 0 = no such occurrence bit1_err bit1 error this bit indicates when an inconsistency occurs between the transmitted and the received bit in a message. 1 = at least one bit sent as recessive is received as dominant 0 = no such occurrence note: this bit is not set by a transmitter in case of arbitration field or ack slot, or in case of a node sending a passive error flag that detects dominant bits. flexcan RM0017 439/904 doc id 14629 rev 8 bit0_err bit0 error this bit indicates when an inconsistency occurs between the transmitted and the received bit in a message. 1 = at least one bit sent as dominant is received as recessive 0 = no such occurrence ack_err acknowledge error this bit indicates that an acknowledge error has been detected by the transmitter node, i.e., a dominant bit has not been detected during the ack slot. 1 = an ack error occurred since last read of this register 0 = no such occurrence crc_err cyclic redundancy check error this bit indicates that a crc error has been detec ted by the receiver node, i.e., the calculated crc is different from the received. 1 = a crc error occurred since last read of this register. 0 = no such occurrence frm_err form error this bit indicates that a form error has been detected by the receiver node, i.e., a fixed-form bit field contains at least one illegal bit. 1 = a form error occurred since last read of this register 0 = no such occurrence stf_err stuffing error this bit indicates that a stuffing error has been detected. 1 = a stuffing error occurred sinc e last read of this register. 0 = no such occurrence. tx_wrn tx error warning this bit indicates when repetitive errors are occurring during message transmission. 1 = tx_err_counter 96 0 = no such occurrence rx_wrn rx error warning this bit indicates when repetitive errors are occurring during message reception. 1 = rx_err_counter 96 0 = no such occurrence idle can bus idle state this bit indicates when can bus is in idle state. 1 = can bus is now idle 0 = no such occurrence txrx current flexcan status (t ransmitting/receiving) this bit indicates if flexcan is transmitting or receiving a message when the can bus is not in idle state. this bit has no meaning when idle is asserted. 1 = flexcan is transmitting a message (idle = 0) 0 = flexcan is receiving a message (idle = 0) table 212. esr field descriptions (continued) field description RM0017 flexcan doc id 14629 rev 8 440/904 interrupt masks 2 register (imask2) this register allows any number of a range of 32 message buffer interrupts to be enabled or disabled. it contains one interrupt mask bit per buffer, enabling the cpu to determine which buffer generates an interrupt after a successful transmission or reception (i.e. when the corresponding iflag2 bit is set). flt_conf fault confinement state this field indicates the confinement state of the flexcan module, as shown in ta b l e 2 1 3 . if the lom bit in the control register is asserted, the flt_conf field will indicate ?error passive?. since the control register is not affected by soft rese t, the flt_conf field will not be affected by soft reset if the lom bit is asserted. boff_int bus off? interrupt this bit is set when flexcan enters ?bus off? state. if the corresponding mask bit in the control register (boff_msk) is set, an interrupt is generat ed to the cpu. this bit is cleared by writing it to ?1?. writing ?0? has no effect. 1 = flexcan module entered ?bus off? state 0 = no such occurrence err_int error interrupt this bit indicates that at least one of the error bits (bits 16?21) is set. if the corresponding mask bit in the control register (err_msk) is set, an inte rrupt is generated to the cpu. this bit is cleared by writing it to ?1?.writing ?0? has no effect. 1 = indicates setting of any error bit in the error and status register 0 = no such occurrence table 213. fault confinement state value meaning 00 error active 01 error passive 1x bus off table 212. esr field descriptions (continued) field description flexcan RM0017 441/904 doc id 14629 rev 8 interrupt masks 1 register (imask1) this register allows to enable or disable any number of a range of 32 message buffer interrupts. it contains one interrupt mask bit per buffer, enabling the cpu to determine which buffer generates an interrupt after a successful transmission or reception (i.e., when the corresponding iflag1 bit is set). figure 212. interrupt masks 2 register (imask2) offset: 0x0024 access: read/write 0123456789101112131415 r buf 63m buf 62m buf 61m buf 60m buf 59m buf 58m buf 57m buf 56m buf 55m buf 54m buf 53m buf 52m buf 51m buf 50m buf 49m buf 48m w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r buf 47m buf 46m buf 45m buf 44m buf 43m buf 42m buf 41m buf 40m buf 39m buf 38m buf 37m buf 36m buf 35m buf 34m buf 33m buf 32m w reset0000000000000000 table 214. imask2 field descriptions field description buf63m ? buf32m buffer mb i mask each bit enables or disables the respective flexcan message buffer (mb32 to mb63) interrupt. 1 = the corresponding buffer interrupt is enabled 0 = the corresponding buffer interrupt is disabled note: setting or clearing a bit in the imask2 register can assert or negate an interrupt request, if the corresponding iflag2 bit is set. RM0017 flexcan doc id 14629 rev 8 442/904 interrupt flags 2 register (iflag2) this register defines the flags for 32 message buffer interrupts. it contains one interrupt flag bit per buffer. each successful transmission or reception sets the corresponding iflag2 bit. if the corresponding imask 2 bit is set, an interrupt will be ge nerated. the interrupt flag must be cleared by writing it to ?1 ?. writing ?0? has no effect. when the aen bit in the mcr is set (abort enabled), while the iflag2 bit is set for a mb configured as tx, the writing access done by cpu into the corresponding mb will be blocked. figure 213. interrupt masks 1 register (imask1) offset: 0x0028 access: read/write 0123456789101112131415 r buf 31m buf 30m buf 29m buf 28m buf 27m buf 26m buf 25m buf 24m buf 23m buf 22m buf 21m buf 20m buf 19m buf 18m buf 17m buf 16m w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r buf 15m buf 14m buf 13m buf 12m buf 11m buf 10m buf 9m buf 8m buf 7m buf 6m buf 5m buf 4m buf 3m buf 2m buf 1m buf 0m w reset0000000000000000 table 215. imask1 field descriptions field description buf31m ? buf0m buf31m?buf0m ? buffer mb i mask each bit enables or disables the respective fl excan message buffer (mb0 to mb31) interrupt. 1 = the corresponding buffer interrupt is enabled 0 = the corresponding buffer interrupt is disabled note: setting or clearing a bit in the imask1 register can assert or negate an interrupt request, if the corresponding iflag1 bit is set. flexcan RM0017 443/904 doc id 14629 rev 8 interrupt flags 1 register (iflag1) this register defines the flags for 32 message buffer interrupts and fifo interrupts. it contains one interrupt flag bit per buffer. each successful transmission or reception sets the corresponding iflag1 bit. if the corr esponding imask1 bit is set, an interrupt will be generated. the interrupt flag must be cleared by writing it to ?1?. writing ?0? has no effect. when the aen bit in the mcr is set (abort enabled), while the iflag1 bit is set for a mb configured as tx, the writing access done by cpu into the corresponding mb will be blocked. when the fen bit in the mcr is set (fifo enabled), the function of the 8 least significant interrupt flags (buf7i ? buf0i) is changed to support the fifo operation. buf7i, buf6i and buf5i indicate operating conditions of the fifo, while buf4i to buf0i are not used. figure 214. interrupt flags 2 register (iflag2) offset: 0x002c access: read/write 0123456789101112131415 r buf 63i buf 62i buf 61i buf 60i buf 59i buf 58i buf 57i buf 56i buf 55i buf 54i buf 53i buf 52i buf 51i buf 50i buf 49i buf 48i w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r buf 47i buf 46i buf 45i buf 44i buf 43i buf 42i buf 41i buf 40i buf 39i buf 38i buf 37i buf 36i buf 35i buf 34i buf 33i buf 32i w reset0000000000000000 table 216. iflag2 field descriptions field description buf32i ? buf63i buffer mb i interrupt each bit flags the respective flexcan me ssage buffer (mb32 to mb63) interrupt. 1 = the corresponding buffer has successfully completed transmission or reception 0 = no such occurrence RM0017 flexcan doc id 14629 rev 8 444/904 rx individual mask registers (rximr0 ? rximr63) these registers are used as acceptance masks for id filtering in rx mbs and the fifo. if the fifo is not enabled, one mask register is provided for each available message buffer, figure 215. interrupt flags 1 register (iflag1) offset: 0x0030 access: read/write 0123456789101112131415 r buf 31i buf 30i buf 29i buf 28i buf 27i buf 26i buf 25i buf 24i buf 23i buf 22i buf 21i buf 20i buf 19i buf 18i buf 17i buf 16i w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r buf 15i buf 14i buf 13i buf 12i buf 11i buf 10i buf 9i buf 8i buf 7i buf 6i buf 5i buf 4i buf 3i buf 2i buf 1i buf 0i w reset0000000000000000 table 217. iflag1 field descriptions field description buf31i ? buf8i buffer mb i interrupt each bit flags the respective flexcan message buffer (mb8 to mb31) interrupt. 1 = the corresponding mb has successfully completed transmission or reception 0 = no such occurrence buf7i buffer mb7 inte rrupt or ?fifo overflow? if the fifo is not enabled, this bit flags the interrupt for mb7. if the fifo is enabled, this flag indicates an overflow condition in the fi fo (frame lost because fifo is full). 1 = mb7 completed transmission/ reception or fifo overflow 0 = no such occurrence buf6i buffer mb6 inte rrupt or ?fifo warning? if the fifo is not enabled, this bit flags the interrupt for mb6. if the fifo is enabled, this flag indicates that 5 out of 6 buffers of the fi fo are already occupied (fifo almost full). 1 = mb6 completed transmission/re ception or fifo almost full 0 = no such occurrence buf5i buffer mb5 inte rrupt or ?frames available in fifo? if the fifo is not enabled, this bit flags the interrupt for mb5. if the fifo is enabled, this flag indicates that at least one frame is available to be read from the fifo. 1 = mb5 completed transmission/receptio n or frames available in the fifo 0 = no such occurrence buf4i ? buf0i buffer mb i interrupt or ?reserved? if the fifo is not enable d, these bits flag the interrupts for mb 0 to mb4. if the fifo is enabled, these flags are not used and must be considered as reserved locations. 1 = corresponding mb completed transmission/reception 0 = no such occurrence flexcan RM0017 445/904 doc id 14629 rev 8 providing id masking capability on a per message buffer basis. when the fifo is enabled (fen bit in mcr is set), the first 8 mask registers apply to the 8 elements of the fifo filter table (on a one-to-one correspondence), while the rest of the registers apply to the regular mbs, starting from mb8. the individual rx mask registers are implemented in sram, so they are not affected by reset and must be explicitly initialized prior to any reception. furthermore, they can only be accessed by the cpu while the module is in freeze mode. out of freeze mode, write accesses are blocked and read accesses will retu rn ?all zeros?. furthermore, if the bcc bit in the mcr is negated, any read or write operation to these registers results in access error. 22.4 functional description 22.4.1 overview the flexcan module is a can protocol engi ne with a very flexible mailbox system for transmitting and receiving can frames. the mailbox system is composed by a set of up to 64 message buffers (mb) that store configuration and control data, time stamp, message id and data (see section 22.3.2 message buffer structure ). the memory corresponding to the first 8 mbs can be configured to support a fifo reception scheme with a powerful id filtering mechanism, capable of checking incoming frames against a table of ids (up to 8 extended ids or 16 standard ids or 32 8-bit id slices), each one with its own individual mask register. simultaneous reception through fifo and mailbox is supported. for mailbox reception, a matching algorithm makes it possible to store received frames only into mbs that have the same id programmed on its id field. a masking scheme makes it possible to match the id programmed on the mb with a range of ids on received can frames. for transmission, an arbitration algorithm decides the prioritization of mbs to be transmitted based on the message id (optionally augmented by 3 local priority bits) or the mb ordering. figure 216. rx individual mask registers (rximr0 ? rximr63) base + 0x0004 0123456789101112131415 mi31 mi30 mi29 mi28 mi27 mi26 mi25 mi24 mi23 mi22 mi21 mi20 mi19 mi18 mi17 mi16 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 mi15 mi14 mi13 mi12 mi11 mi10 mi9 m i8 mi7 mi6 mi5 mi4 mi3 mi2 mi1 mi0 table 218. rximr0 ? rximr63 field description field description mi31?mi0 mask bits for normal rx mbs, the mask bits affect the id fi lter programmed on the mb. for the rx fifo, the mask bits affect all bits programmed in the filter table (id, ide, rtr). 1 = the corresponding bit in the filter is checked against the one received 0 = the corresponding bit in the filter is ?don?t care? RM0017 flexcan doc id 14629 rev 8 446/904 before proceeding with the functional description, an important concept must be explained. a message buffer is said to be ?active? at a given time if it can participate in the matching and arbitration algorithms that are happening at that time. an rx mb with a ?0000? code is inactive (refer to ta bl e 2 0 5 ). similarly, a tx mb with a ?1000? or ?1001? code is also inactive (refer to table 206 ). an mb not programmed with ?0000? , ?1000? or ?1001? will be temporarily deactivated (will not participate in the current arbitration or matching run) when the cpu writes to the c/s field of that mb (see section message buffer deactivation ). 22.4.2 local priority transmission the term local priority refers to the priority of transmit messages of the host node. this allows increased control over the priority mechanism for transmitting messages. ta b l e 2 0 3 shows the placement of prio in the id part of the message buffer. an additional 3-bit field (prio) in the long-word id part of the message buffer structure has been added for local priority determination. they are prefixed to the regular id to define the transmission priority. these bits are not transmitted and are intended only for tx buffers. perform the following to use the local priority feature: 1. set the lprio_en bit in the canx_mcr. 2. write the additional prio bits in the id long-word of tx message buffers when configuring the tx buffers. with this extended id concept, the arbitrat ion process is based on the full 32-bit word. however, the actual transmitted id continues to have 11 bits for standard frames and 29 bits for extended frames. 22.4.3 transmit process in order to transmit a can frame, the cpu must prepare a message buffer for transmission by executing the following procedure: if the mb is active (transmission pending), write an abort code (?1001?) to the code field of the control and status word to r equest an abortion of the transmission, then read back the code field and the iflag register to check if the transmission was aborted (see section transmission abort mechanism ). if backwards compatibility is desired (aen in mcr negated), just write ?1000? to the code field to inactivate the mb but then the pending frame may be transmitted without notification (see section message buffer deactivation ). write the id word. write the data bytes. write the length, control and code fields of the control and status word to activate the mb. once the mb is activated in the fourth step, it will participate into the arbitration process and eventually be transmitted according to its priority. at the end of the successful transmission, the value of the free running timer is written into the time stamp field, the code field in the control and status word is updated, a status flag is set in the interrupt flag register and an interrupt is generated if allowed by the corresponding interrupt mask register bit. the new code field after transmission depends on the code that was used to activate the mb in step four (see ta b l e 2 0 5 and ta b l e 2 0 6 in section 22.3.2 message buffer structure ). when the abort feature is enabled (aen in mcr is asserted), after the interrupt flag is asserted for a mb configured as transmit buffer, the mb is blocked, therefore the cpu is not able to flexcan RM0017 447/904 doc id 14629 rev 8 update it until the interrupt flag be negated by cpu. it means that the cpu must clear the corresponding iflag before starting to prepare this mb for a new transmission or reception. 22.4.4 arbitration process the arbitration process is an algorithm executed by the mbm that scans the whole mb memory looking for the highest priority message to be transmitted. all mbs programmed as transmit buffers will be scanned to find the lowest id (s) or the lowest mb number or the highest priority, depending on the lbuf and lprio_en bits on the control register. the arbitration process is triggered in the following events: during the crc field of the can frame during the error delimiter field of the can frame during intermission, if the winner mb defined in a previous arbitration was deactivated, or if there was no mb to transmit, but the cpu wrote to the c/s word of any mb after the previous arbitration finished when mbm is in idle or bus off state and the cpu writes to the c/s word of any mb upon leaving freeze mode when lbuf is asserted, the lprio_en bit has no effect and the lowest number buffer is transmitted first. when lbuf and lprio_en are both negated, the mb with the lowest id is transmitted first but. if lbuf is negated and lprio_en is asserted, the prio bits augment the id used during the arbitration process. with this extended id concept, arbitration is done based on the full 32-bit id and the prio bits define which mb should be transmitted first, therefore mbs with prio = 000 have higher priority. if two or more mbs have the same priority, the regular id will determine the priori ty of transmission. if two or more mbs have the same priority (3 extra bi ts) and the same regular id, th e lowest mb will be transmitted first. once the highest priority mb is selected, it is transferred to a temporary storage space called serial message buffer (smb), which has the same structure as a normal mb but is not user accessible. this operation is called ?move-out? and after it is done, write access to the corresponding mb is blocked (if the aen bit in mcr is asserted). the write access is released in the following events: after the mb is transmitted flexcan enters in halt or bus off flexcan loses the bus arbitration or there is an error during the transmission at the first opportunity window on the can bus, the message on the smb is transmitted according to the can protocol rules. flexcan transmits up to eight data bytes, even if the dlc (data length code) value is bigger. 22.4.5 receive process to be able to receive can frames into the mailbox mbs, the cpu must prepare one or more message buffers for reception by executing the following steps: if the mb has a pending transmission, write an abort code (?1001?) to the code field of the control and status word to request an abortion of the transmission, then read back the code field and the iflag register to check if the transmission was aborted s. actually, if lbuf is negated, the ar bitration considers not only the id, but also the rtr and ide bits placed inside the id at the same positions they are transmitted in the can frame. RM0017 flexcan doc id 14629 rev 8 448/904 (see section transmission abort mechanism ). if backwards comp atibility is desired (aen in mcr negated), just write ?1000? to the code field to inactivate the mb, but then the pending frame may be transmitted without notification (see section message buffer deactivation ). if the mb already programmed as a receiver, just write ?0000? to the code field of the control and status word to keep the mb inactive. write the id word write ?0100? to the code field of the control and status word to activate the mb once the mb is activated in the third step, it will be able to receive frames that match the programmed id. at the end of a successful reception, the mb is updated by the mbm as follows: the value of the free running timer is written into the time stamp field the received id, data (8 bytes at most) and length fields are stored the code field in the control and status word is updated (see ta bl e 2 0 5 and ta bl e 2 0 6 in section 22.3.2 message buffer structure ) a status flag is set in the interrupt flag register and an interrupt is generated if allowed by the corresponding interrupt mask register bit upon receiving the mb interrupt, the cpu should service the received frame using the following procedure: read the control and status word (mandatory ? activates an internal lock for this buffer) read the id field (optional ? needed only if a mask was used) read the data field read the free running timer (optional ? releases the internal lock) upon reading the control and status word, if the busy bit is set in the code field, then the cpu should defer the access to the mb until this bit is negated. reading the free running timer is not mandatory. if not executed the mb remains locked, unless the cpu reads the c/s word of another mb. note that only a single mb is locked at a time. the only mandatory cpu read operation is the one on the control and status word to assure data coherency (see section 22.4.7 data coherence ). the cpu should synchronize to frame reception by the status flag bit for the specific mb in one of the iflag registers and not by the code field of that mb. polling the code field does not work because once a frame was received and the cpu services the mb (by reading the c/s word followed by unlocking the mb), the code field will not return to empty. it will remain full, as explained in ta bl e 2 0 5 . if the cpu tries to workaround this behavior by writing to the c/s word to force an empty code after reading the mb, the mb is actually deactivated from any currently ongoing matching process. as a result, a newly received frame matching the id of that mb may be lost. in summary: never do polling by reading directly the c/s word of the mbs. instead, read the iflag registers. note that the received id field is always stored in the matching mb, thus the contents of the id field in an mb may change if the match was due to masking. note also that flexcan does receive frames transmitted by itself if there exists an rx matching mb, provided the srx_dis bit in the mcr is not asserted. if srx_dis is asserted, flexcan will not store frames transmitted by itself in any mb, even if it contains a matching mb, and no interrupt flag or interrupt signal will be generated due to the frame reception. to be able to receive can frames through the fifo, the cpu must enable and configure the fifo during freeze mode (see section 22.4.8 rx fifo ). upon receiving the frames flexcan RM0017 449/904 doc id 14629 rev 8 available interrupt from fifo, the cpu should service the received frame using the following procedure: read the control and status word (optional ? needed only if a mask was used for ide and rtr bits) read the id field (optional ? needed only if a mask was used) read the data field clear the frames available interrupt (mandatory ? release the buffer and allow the cpu to read the next fifo entry) 22.4.6 matching process the matching process is an algorithm executed by the mbm that scans the mb memory looking for rx mbs programmed with the same id as the one received from the can bus. if the fifo is enabled, the 8-entry id table from fifo is scanned first and then, if a match is not found within the fifo table, the other mbs are scanned. in the event that the fifo is full, the matching algorithm will always look fo r a matching mb outside the fifo region. when the frame is received, it is temporarily stored in a hidden aux iliary mb called serial message buffer (smb). the matching process takes place during the crc field of the received frame. if a matching id is found in the fifo table or in one of the regular mbs, the contents of the smb will be transfe rred to the fifo or to the matched mb during the 6th bit of the end-of-frame field of the can protocol. this operation is called ?move-in?. if any protocol error (crc, ack, etc.) is detected, than the move-in operation does not happen. for the regular mailbox mbs, an mb is said to be ?free to receive? a new frame if the following conditions are satisfied: the mb is not locked (see section message buffer lock mechanism ) the code field is either empty or else it is full or overrun but the cpu has already serviced the mb (read the c/s word and then unlocked the mb) if the first mb with a matching id is not ?free to receive? the new frame, then the matching algorithm keeps looking for another free mb until it finds one. if it cannot find one that is free, then it will overwrite the last matching mb (unl ess it is locked) and set the code field to overrun (refer to ta b l e 2 0 5 and ta bl e 2 0 6 ). if the last matching mb is locked, then the new message remains in the smb, waiting for the mb to be unlocked (see section message buffer lock mechanism ). suppose, for example, that the fifo is disabled and there are two mbs with the same id, and flexcan starts receiving messages with that id. let us say that these mbs are the second and the fifth in the array. when the fi rst message arrives, the matching algorithm will find the first match in mb number 2. the code of this mb is empty, so the message is stored there. when the seco nd message arrives, the matching algorithm will find mb number 2 again, but it is not ?free to receive? , so it will keep looking and find mb number 5 and store the message there. if yet another message with the same id arrives, the matching algorithm finds out that there are no matching mbs that are ?free to receive?, so it decides to overwrite the last matched mb, which is number 5. in doing so, it sets the code field of the mb to indicate overrun. the ability to match the same id in more than one mb can be exploited to implement a reception queue (in addition to the full featured fifo) to allow more time for the cpu to service the mbs. by programming more than one mb with the same id, received messages will be queued into the mbs. the cpu can exam ine the time stamp fi eld of the mbs to determine the order in which the messages arrived. RM0017 flexcan doc id 14629 rev 8 450/904 the matching algorithm described above can be changed to be the same one used in previous versions of the flexcan module. when the bcc bit in mcr is negated, the matching algorithm stops at the first mb with a matching id that it founds, whether this mb is free or not. as a result, the message queueing feature does not work if the bcc bit is negated. matching to a range of ids is possible by using id acceptance masks. flexcan supports individual masking per mb. please refer to section rx individual mask registers (rximr0? rximr63) . during the matching algorithm, if a mask bit is asserted, then the corresponding id bit is compared. if the mask bit is negated, the corresponding id bit is ?don?t care?. please note that the individual mask registers are implemented in sram, so they are not initialized out of reset. also, they can only be programmed if the bcc bit is asserted and while the module is in freeze mode. flexcan also supports an alternate masking scheme with only three mask registers (rgxmask, rx14mask and rx15mask) for bac kwards compatibility. this alternate masking scheme is enabled when the bcc bit in the mcr is negated. 22.4.7 data coherence in order to maintain data coherency and flexcan proper operation, the cpu must obey the rules described in transmit process and section 22.4.5 receive process . any form of cpu accessing an mb structure within flexcan other than those specified may cause flexcan to behave in an unpredictable way. transmission abort mechanism the abort mechanism provides a safe way to request the abortion of a pending transmission. a feedback mechanism is provided to inform the cpu if the transmission was aborted or if the frame could not be aborted and was transmitted instead. in order to maintain backwards compatibilit y, the abort mechanism must be explicitly enabled by asserting the aen bit in the mcr. in order to abort a transmission, the cpu must write a specific abort code (1001) to the code field of the control and status word. when the abort mechanism is enabled, the active mbs configured as trasmission must be aborted first and then they may be updated. if the abort code is written to an mb that is current ly being transmitted, or to an mb that was already loaded into the smb for transmission, the write operation is blocked and the mb is not deactivated, but the abort request is captured and kept pending until one of the following conditions are satisfied: the module loses the bus arbitration there is an error during the transmission the module is put into freeze mode if none of conditions above are reached, the mb is transmitted correctly, the interrupt flag is set in the iflag register and an interrupt to the cpu is generated (if enabled). the abort request is automatically cleared when the interrupt flag is set. in the other hand, if one of the above conditions is reached, the frame is not transmitted, therefore the abort code is written into the code field, the interrupt flag is set in the iflag and an interrupt is (optionally) generated to the cpu. if the cpu writes the abort code before the transmission begins internally, then the write operation is not blocked, therefore the mb is updated and no interrupt flag is set. in this way the cpu just needs to read the abort code to make sure the active mb was deactivated. although the aen bit is asserted and the cpu wrote the abort code, in this case the mb is flexcan RM0017 451/904 doc id 14629 rev 8 deactivated and not aborted, because the transmission did not start yet. one mb is only aborted when the abort request is captured and kept pending until one of the previous conditions are satisfied. the abort procedure can be summarized as follows: cpu writes 1001 into the code field of the c/s word cpu reads the code field and compares it to the value that was written if the code field that was read is different from the value that was written, the cpu must read the corresponding iflag to check if the frame was transmitted or it is being currently transmitted. if the corresponding iflag is set, the frame was transmitted. if the corresponding iflag is reset, the cpu must wait for it to be set, and then the cpu must read the code field to check if the mb was aborted (code=1001) or it was transmitted (code=1000). message buffer deactivation deactivation is mechanism provided to maintain data coherence when the cpu writes to the control and status word of active mbs out of freeze mode. any cpu write access to the control and status word of an mb causes that mb to be excluded from the transmit or receive processes during the current matching or arbitration round. the deactivation is temporary, affecting only for the current match/arbitration round. the purpose of deactivation is data coherency. the match/arbitration process scans the mbs to decide which mb to transmit or receive. if the cpu updates the mb in the middle of a match or arbitration process, the data of that mb may no longer be coherent, therefore deactivation of that mb is done. even with the coherence mechanism described above, writing to the control and status word of active mbs when not in freeze mode may produce undesirable results. examples are: matching and arbitration are one-pass processes. if mbs are deactivated after they are scanned, no re-evaluation is done to determine a new match/winner. if an rx mb with a matching id is deactivated during the matchi ng process after it was scanned, then this mb is marked as invalid to receive the fr ame, and flexcan will keep looking for another matching mb within the ones it has not scanned yet. if it cannot find one, then the message will be lost. suppose, for example, that two mbs have a matching id to a received frame, and the user deactivated the first matching mb after flexcan has scanned the second. the received frame will be lost even if the second matching mb was ?free to receive?. if a tx mb containing the lowest id is deactivated after flexcan has scanned it, then flexcan will look for another winner within the mbs that it ha s not scanned yet. therefore, it may transmit an mb with id that may not be the lowest at the time because a lower id might be present in one of the mbs that it had already scanned before the deactivation. there is a point in time until which the deacti vation of a tx mb causes it not to be transmitted (end of move-out). after this point, it is transmitted but no interrupt is issued and the code field is not updated. in order to avoid this situation, the abort procedures described in section transmission abort mechanism should be used. message buffer lock mechanism besides mb deactivation, flexcan has another data coherence mechanism for the receive process. when the cpu reads the control and status word of an ?active not empty? rx mb, RM0017 flexcan doc id 14629 rev 8 452/904 flexcan assumes that the cpu wants to read the whole mb in an atomic operation, and thus it sets an internal lock flag for that mb. the lock is released when the cpu reads the free running timer (global unlock operation), or when it reads the control and status word of another mb. the mb locking is done to prevent a new frame to be written into the mb while the cpu is reading it. note: the locking mechanism only applies to rx mbs which have a code different than inactive (?0000?) or empty (t) (?0100?). also, tx mbs cannot be locked. suppose, for example, that the fifo is disabled and the second and the fifth mbs of the array are programmed with the same id, and flexcan has already received and stored messages into these two mbs. suppose now that the cpu decides to read mb number 5 and at the same time another message with the same id is arriving. when the cpu reads the control and status word of mb number 5, this mb is locked. the new message arrives and the matching algorithm finds out that there are no ?free to receive? mbs, so it decides to override mb number 5. however, this mb is locked, so the new message cannot be written there. it will remain in the smb waiting for the mb to be unlo cked, and only then will be written to the mb. if the mb is not unlocked in time and yet another new message with the same id arrives, then the new message overwr ites the one on the sm b and there will be no indication of lost messages either in the code field of the mb or in the error and status register. note: the flexcan module has 2 smbs thus if a message with another id arrives it is not lost. so overall the probability to lose message is very low unless a series of messages with the same id arrives, which is not common in flexcan. while the message is being moved-in from the smb to the mb, the busy bit on the code field is asserted. if the cpu reads the control and status word and finds out that the busy bit is set, it should defer accessing the mb until the busy bit is negated. note: if the busy bit is asserted or if the mb is empty, then reading the control and status word does not lock the mb. deactivation takes precedence over locking. if the cpu deactivates a locked rx mb, then its lock status is negated and the mb is marked as invalid for the current matching round. any pending message on the smb will not be transferred anymore to the mb. 22.4.8 rx fifo the receive-only fifo is enabled by asserting the fen bit in the mcr. the reset value of this bit is zero to maintain software backwar ds compatibility with previous versions of the module that did not have the fifo feature. when the fifo is enabled, the memory region normally occupied by the first 8 mbs (0x80?0xff) is now reserved for use of the fifo engine (see section 22.3.3 rx fifo structure ). management of read and write pointers is done internally by the fifo engine. the cpu can read the received frames sequentially, in the order they were received, by repeatedly accessing a message buffer structure at the beginning of the memory. the fifo can store up to 6 frames pending service by the cpu. an interrupt is sent to the cpu when new frames are available in the fifo. upon receiving the interrupt, the cpu must read the frame (accessing an mb in the 0x80 address) and then clear the interrupt. the act of clearing the interrupt triggers the fi fo engine to replace the mb in 0x80 with the t. in previous flexcan versions, reading the c/s word locked the mb even if it was empty. this behavior will be honored when the bcc bit is negated. flexcan RM0017 453/904 doc id 14629 rev 8 next frame in the queue, and then issue another interrupt to the cpu. if the fifo is full and more frames continue to be received, an overflow interrupt is issued to the cpu and subsequent frames are not accepted until the cpu creates space in the fifo by reading one or more frames. a warning interrupt is also generated when 5 frames are accumulated in the fifo. a powerful filtering scheme is provided to accept only frames intended for the target application, thus reducing the interrupt servicing work load. the filtering criteria is specified by programming a table of 8 32-bit registers that can be configured to one of the following formats (see also section 22.3.3 rx fifo structure ): format a: 8 extended or standard ids (including ide and rtr) format b: 16 standard ids or 16 extended 14-bit id slices (including ide and rtr) format c: 32 standard or extended 8-bit id slices note: a chosen format is applied to all 8 registers of the filter table. it is not possible to mix formats within the table. the eight elements of the filter table are individually affected by the first eight individual mask registers (rximr0 ? rximr7), allowing very powerful filtering criteria to be defined. the rest of the rximr, starting from rxim8, continue to affect the regular mbs, starting from mb8. if the bcc bit is negated (or if the rximr are not available for the particular mcu), then the fifo filter table is affected by the legacy mask registers as follows: element 6 is affected by rx14mask, element 7 is af fected by rx15mask and the other elements (0 to 5) are affected by rxgmask. 22.4.9 can protocol related features remote frames remote frame is a special kind of frame. the user can program a mb to be a request remote frame by writing the mb as transmit with the rtr bit set to ?1?. after the remote request frame is transmitted successfully, the mb becomes a receive message buffer, with the same id as before. when a remote request frame is received by flexcan, its id is compared to the ids of the transmit message buffers with the code field ?1010?. if there is a matching id, then this mb frame will be transmitted. note that if the ma tching mb has the rtr bit set, then flexcan will transmit a remote frame as a response. a received remote request frame is not stored in a receive buffer. it is only used to trigger a transmission of a frame in response. the mask registers are not used in remote frame matching, and all id bits (except rtr) of the incoming received frame should match. in the case that a remote request frame was received and matched an mb, this message buffer immediately enters the internal arbitration process, but is considered as normal tx mb, with no higher priority. the data length of this frame is independent of the dlc field in the remote frame that initiated its transmission. if the rx fifo is enabled (b it fen set in mcr), flexcan will not generate an automatic response for remote request frames that match the fifo filtering criteria. if the remote frame matches one of the target ids, it will be stored in t he fifo and presented to the cpu. note that for filtering formats a and b, it is possible to select whether remote frames are accepted or not. for format c, remote frames are always accepted (if they match the id). RM0017 flexcan doc id 14629 rev 8 454/904 overload frames flexcan does transmit overload frames due to detection of following conditions on can bus: detection of a dominant bit in the first/second bit of intermission detection of a dominant bit at the 7th bit (last) of end of frame field (rx frames) detection of a dominant bit at the 8th bit (last) of error frame delimiter or overload frame delimiter time stamp the value of the free running timer is sampled at the beginning of the identifier field on the can bus, and is stored at the end of ?move-in? in the time stamp field, providing network behavior with respect to time. note that the free running timer can be reset upon a specific frame reception, enabling network time synchronization. refer to tsyn description in section control register (ctrl) . protocol timing figure 217 shows the structure of the clock generation circuitry that feeds the can protocol interface (cpi) submodule. the clock source bi t (clk_src) in the ctrl register defines whether the internal clock is co nnected to the output of a cryst al oscillator (oscillator clock) or to the peripheral clock (generally from a fmpll). in order to guarantee reliable operation, the clock source should be selected while the module is in disable mode (bit mdis set in the module configuration register). figure 217. can engine clocking scheme the crystal oscillator clock should be selected whenever a tight tolerance (up to 0.1%) is required in the can bus timing. the crystal oscillator clock has better jitter performance than fmpll generated clocks. note: this clock selection featur e may not be available in all mcus. a particular mcu may not have a fmpll, in which case it would have only the oscillator clock, or it may use only the fmpll clock feeding the flexcan module. in these cases, the clk_src bit in the ctrl register has no effect on the module operation. the flexcan module supports a variety of means to setup bit timing parameters that are required by the can protocol. the control register has various fields used to control bit timing parameters: presdiv, pr opseg, pseg1, pseg2 and rjw. see section control register (ctrl) . peripheral clock (fmpll) oscillator clock (xtal) clk_src prescaler (1 .. 256) sclock cpi clock flexcan RM0017 455/904 doc id 14629 rev 8 the presdiv field controls a prescaler that generates the serial clock (sclock), whose period defines the ?time quantum? used to compose the can waveform. a time quantum is the atomic unit of time handled by the can engine. a bit time is subdivided into three segments (u) (reference figure 218 and table 219 ): sync_seg: this segment has a fixed length of one time quantum. signal edges are expected to happen within this section time segment 1: this segment includes the propagation segment and the phase segment 1 of the can standa rd. it can be programmed by setting the propseg and the pseg1 fields of the ctrl register so that their sum (plus 2) is in the range of 4 to 16 time quanta time segment 2: this segment represents the phase segment 2 of the can standard. it can be programmed by setting the pseg2 fiel d of the ctrl regist er (plus 1) to be 2 to 8 time quanta long figure 218. segments within the bit time u. for further explanation of the underlyi ng concepts please refer to iso/dis 11519 ? 1, section 10.3. reference also the bosch can 2.0a/b protocol spec ification dated september 1991 for bit timing. f tq f canclk prescaler value t () --------------------- --------------------- -------------- = bit rate f tq number of time quanta tt t () ------------------- ------------------ ----------------- ------------------ ---------------- - = t sync_seg time segment 1 time segment 2 1 4 ... 16 2 ... 8 8 ... 25 time quanta = 1 bit time nrz signal sample point (single or triple sampling) (prop_seg + pseg1 + 2) (pseg2 + 1) transmit point RM0017 flexcan doc id 14629 rev 8 456/904 table 220 is an example of the can compliant segment settings and the related parameter values. it refers to the official can specification. note: it is the user?s responsibility to ensure t he bit time settings are in compliance with the can standard. for bit time calculations, use an ipt (information processing time) of 2, which is the value implemented in the flexcan module. arbitration and matching timing during normal transmission or reception of frames, the arbitration, matching, move-in and move-out processes are executed during certain time windows inside the can frame, as shown in figure 219 . figure 219. arbitration, match and move time windows table 219. time segment syntax syntax description sync_seg system expects transitions to occur on the bus during this period. transmit point a node in transmit mode transfers a new value to the can bus at this point. sample point a node samples the bus at this point. if the three samples per bit option is selected, then this point marks the position of the third sample. table 220. can standard compliant bit time segment settings time segment 1 time segment 2 resynchronization jump width 5 .. 10 2 1 .. 2 4 .. 11 3 1 .. 3 5 .. 12 4 1 .. 4 6 .. 13 5 1 .. 4 7 .. 14 6 1 .. 4 8 .. 15 7 1 .. 4 9 .. 16 8 1 .. 4 crc (15) eof (7) interm start move matching/arbitration window (24 bits) move (bit 6) window flexcan RM0017 457/904 doc id 14629 rev 8 when doing matching and arbitration, flexcan needs to scan the whole message buffer memory during the available time slot. in order to have sufficient time to do that, the following requirements must be observed: a valid can bit timing must be programmed, as indicated in table 220 the peripheral clock frequency cannot be sm aller than the oscillator clock frequency, i.e. the fmpll cannot be programmed to divide down the oscillator clock there must be a minimum ratio between the peripheral clock frequency and the can bit rate, as specified in ta b l e 2 2 1 a direct consequence of the first requirement is that the minimum number of time quanta per can bit must be 8, so the oscillator clock freq uency should be at least 8 times the can bit rate. the minimum frequency ratio specified in table 221 can be achieved by choosing a high enough peripheral clock fr equency when compared to the oscillator clock frequency, or by adjusting one or more of the bit ti ming parameters (pr esdiv, propseg, pseg1, pseg2). as an example, taking the case of 64 mbs, if the oscillato r and peripheral clock frequencies are equal and the can bit timing is programmed to have 8 time quanta per bit, then the prescaler factor (presdiv + 1) should be at least 2. for prescaler factor equal to one and can bit timing with 8 ti me quanta per bit, the ratio be tween peripheral and oscillator clock frequencies should be at least 2. 22.4.10 modes of operation details freeze mode this mode is entered by asserting the halt bit in the mcr or when the mcu is put into debug mode. in both cases it is also necessary that the frz bit is asserted in the mcr and the module is not in low power mode (disable mode). when freeze mode is requested during transmission or reception, flexcan does the following: waits to be in either intermission, passive error, bus off or idle state waits for all internal activities like arbitration, matching, move-in and move-out to finish ignores the rx input pin and drives the tx pin as recessive stops the prescaler, thus halting all can protocol activities grants write access to the error counters register, which is read-only in other modes sets the not_rdy and frz_ack bits in mcr after requesting freeze mode, the user must wait for the frz_ack bit to be asserted in mcr before executing any other action, otherwise flexcan may operate in an unpredictable way. in freeze mode, all memory mapped registers are accessible. exiting freeze mode is done in one of the following ways: cpu negates the frz bit in the mcr the mcu is removed from debug mode and/or the halt bit is negated table 221. minimum ratio between periphe ral clock frequency and can bit rate number of message buffers minimum ratio 16 8 32 8 64 16 RM0017 flexcan doc id 14629 rev 8 458/904 once out of freeze mode, flexcan tries to resynchronize to the can bus by waiting for 11 consecutive recessive bits. module disable mode this low power mode is entered when the mdis bit in the mcr is asserted. if the module is disabled during freeze mode, it shuts down the clocks to the cpi and mbm submodules, sets the lpm_ack bit and negates the frz_ack bit. if the module is disabled during transmission or reception, flexcan does the following: waits to be in either idle or bus off state, or else waits for the third bit of intermission and then checks it to be recessive waits for all internal activities like arbitration, matching, move-in and move-out to finish ignores its rx input pin and drives its tx pin as recessive shuts down the clocks to the cpi and mbm submodules sets the not_rdy and lpm_ack bits in mcr the bus interface unit continues to operate, enabling the cpu to access memory mapped registers, except the free running timer, the error counter register and the message buffers, which cannot be accessed when the module is in disable mode. exiting from this mode is done by nega ting the mdis bit, which will resume the clocks and negate the lpm_ack bit. 22.4.11 interrupts the module can generate up to 69 interrupt sources (64 interrupts due to message buffers and 5 interrupts due to ored interrupts from mbs, bus off, error, tx warning and rx warning). the number of actual sources depends on the configured number of message buffers. each one of the message buffer s can be an interrupt source, if its corresponding imask bit is set. there is no distinction between tx and rx interrupts for a particular buffer, under the assumption that the buffer is initialized for either transmission or reception. each of the buffers has assigned a flag bit in the iflag registers. the bit is set when the corresponding buffer completes a successful transmission/reception and is cleared when the cpu writes it to ?1? (unless another interrupt is generated at the same time). note: it must be guaranteed that the cpu only clears the bit causing the current interrupt. for this reason, bit manipulation instructions (bset) must not be used to clear interrupt flags. these instructions may cause accidental clearing of interrupt flags which are set after entering the current interrupt service routine. if the rx fifo is enabled (bit fen on mcr set), the interrupts corresponding to mbs 0 to 7 have a different behavior. bit 7 of the iflag1 becomes the ?fifo overflow? flag; bit 6 becomes the fifo warning flag, bit 5 becomes the ?frames available in fifo flag? and bits 4?0 are unused. see section interrupt flags 1 register (iflag1) for more information. a combined interrupt for all mbs is also generated by an or of all the interrupt sources from mbs. this interrupt gets generated when any of the mbs generates an interrupt. in this case the cpu must read the iflag registers to determine which mb caused the interrupt. the other 4 interrupt sources (bus off, error, tx warning and rx warning) generate interrupts like the mb ones, and can be read from the error and status register. the bus off, error, tx warning and rx warning interrupt mask bits are located in the control register, and the wake-up interrupt mask bit is located in the mcr. flexcan RM0017 459/904 doc id 14629 rev 8 22.4.12 bus interface the cpu access to flexcan registers are subject to the following rules: read and write access to supervisor registers in user mode results in access error. read and write access to unimplemented or reserved address space also results in access error. any access to unimplemented mb or rx individual mask register locations results in access er ror. any access to the rx individual mask register space when the bcc bit in mcr is n egated results in access error. if maxmb is programmed with a value smaller than the available number of mbs, then the unused memory space can be used as general purpose sram space. note that the rx individual mask registers can only be accessed in freeze mode, and this is still true for unused space within this memory. note also that reserved words within sram cannot be used. as an example, suppose flexcan is configured with 64 mbs and maxmb is programmed with zero. the maximum number of mbs in this case becomes one. the mb memory starts at 0x0060, but the space from 0x0060 to 0x007f is reserved (for smb usage), and the space from 0x0080 to 0x008f is used by the one mb. this leaves us with the available space from 0x0090 to 0x047f. the available memory in the mask registers space would be from 0x0884 to 0x097f. note: unused mb space must not be used as general purpose sram while flexcan is transmitting and receiving can frames. 22.5 initialization/app lication information this section provide instructions for initializing the flexcan module. 22.5.1 flexcan initialization sequence the flexcan module may be reset in three ways: mcu level hard reset, which resets all memory mapped registers asynchronously mcu level soft reset, which resets some of the memory mapped registers synchronously (refer to ta b l e 2 0 2 to see what registers are affected by soft reset) soft_rst bit in mcr, which has the same effect as the m cu level soft reset soft reset is synchronous and has to follow an internal request/acknowledge procedure across clock domains. therefore, it may take some time to fully propagate its effects. the soft_rst bit remains asserted while soft reset is pending, so software can poll this bit to know when the reset has completed. also, soft reset cannot be applied while clocks are shut down in the low power mode. the low power mode should be exited and the clocks resumed before applying soft reset. the clock source (clk_src bit) should be selected while the module is in disable mode. after the clock source is selected and the module is enabled (mdis bit negated), flexcan automatically goes to freeze mode. in free ze mode, flexcan is unsynchronized to the can bus, the halt and frz bits in mcr are set, the internal state machines are disabled and the frz_ack and not_rdy bits in the mcr are set. the tx pin is in recessive state and flexcan does not initiate any transmission or reception of can frames. note that the message buffers and the rx individual mask registers are not affected by reset, so they are not automatically initialized. RM0017 flexcan doc id 14629 rev 8 460/904 for any configuration change/initialization it is required that flexcan is put into freeze mode (see section freeze mode ). the following is a gener ic initialization sequence applicable to the flexcan module: initialize the module configuration register ? enable the individual filtering per mb and reception queue features by setting the bcc bit ? enable the warning interrupts by setting the wrn_en bit ? if required, disable frame self reception by setting the srx_dis bit ? enable the fifo by setting the fen bit ? enable the abort mechanism by setting the aen bit ? enable the local priority feature by setting the lprio_en bit initialize the control register ? determine the bit timing parame ters: propseg, pseg1, pseg2, rjw ? determine the bit rate by programming the presdiv field ? determine the internal arbitration mode (lbuf bit) initialize the message buffers ? the control and status word of all message buffers must be initialized ? if fifo was enabled, the 8-entry id table must be initialized ? other entries in each message buffer should be initialized as required initialize the rx individual mask registers set required interrupt mask bits in the imask registers (for all mb interrupts) and in ctrl register (for bus off and error interrupts) negate the halt bit in mcr starting with the last event, flexcan attempts to synchronize to the can bus. 22.5.2 flexcan addressing an d sram size configurations there are three sram configurations that can be implemented within the flexcan module. the possible configurations are: for 16 mbs: 288 bytes for mb memory and 64 bytes for individual mask registers for 32 mbs: 544 bytes for mb memory and 128 bytes for individual mask registers for 64 mbs: 1056 bytes for mb memory and 256 bytes for individual mask registers in each configuration the user can program th e maximum number of mbs that will take part in the matching and arbitration processes using the maxmb field in the mcr. for 16 mb configuration, maxmb can be any number between 0?15. for 32 mb configuration, maxmb can be any number between 0?31. for 64 mb configuration, maxmb can be any number between 0 ? 63. deserial serial periphe ral interface (dspi) RM0017 461/904 doc id 14629 rev 8 23 deserial serial peripheral interface (dspi) 23.1 introduction this chapter describes the deserial serial pe ripheral interface (dspi), which provides a synchronous serial bus for communication between the mcu and an external peripheral device. the spc560bx and spc560cx has three identical dspi modules (dspi_0, dspi_1 and dspi_2). the ?x? appended to signal names signifies the module to which the signal applies. thus cs0_x specifies that the cs0 signal applies to dspi module 0, 1, etc. a block diagram of the dspi is shown in figure 220 . figure 220. dspi block diagram the register content is transmitted using an spi protocol. cmd interrupt control tx fifo rx fifo tx data rx data 16 16 shift register sout _x spi spi baud rate, delay and transfer control sin _x sck _x cs0_ x cs1:4 _x cs5 _x intc 4 RM0017 deserial serial peripheral interface (dspi) doc id 14629 rev 8 462/904 for queued operations the spi queues reside in internal sram which is external to the dspi. data transfers between the queues and the dspi fifos are accomplished through host software. figure 221 shows a dspi with external queues in internal sram. figure 221. dspi with queues 23.2 features the dspi supports these spi features: full-duplex, three-wire synchronous transfers master and slave mode buffered transmit and receive operation using the tx and rx fifos, with depths of four entries visibility into tx and rx fifos for ease of debugging fifo bypass mode for low-latency updates to spi queues programmable transfer attributes on a per-frame basis ? 6 clock and transfer attribute registers ? serial clock with programmable polarity and phase ? programmable delays cs to sck delay sck to cs delay delay between frames ? programmable serial frame size of 4 to 16 bits, expandable with software control ? continuously held ch ip select capability internal sram tx queue rx queue address/control tx fifo dspi rx fifo rx data tx data tx data rx data shift register address/control host cpu deserial serial periphe ral interface (dspi) RM0017 463/904 doc id 14629 rev 8 up to 6 peripheral chip selects, expandable to 64 with external demultiplexer deglitching support for up to 32 peripheral chip selects with ex ternal demultiplexer 6 interrupt conditions: end of queue reached (eoqf) tx fifo is not full (tfff) transfer of current frame complete (tcf) rx fifo is not empty (rfdf) fifo overrun (attempt to transmit with an empty tx fifo or serial frame received while rx fifo is full) (rfof) or (tfuf) modified spi transfer formats for communication with slower peripheral devices continuous serial communications clock (sck) 23.3 modes of operation the dspi has four modes of operation. these modes can be divided into two categories: module-specific: master, slave, and module disable modes mcu-specific: debug mode the module-specific modes are entered by host software writing to a register. the mcu- specific mode is controlled by signals exter nal to the dspi. an mcu-specific mode is a mode that the entire device may enter, in parallel to the dspi being in one of its module- specific modes. 23.3.1 master mode master mode allows the dspi to initiate and control serial communication. in this mode the sck, cs n and sout signals are controlled by the dspi and configured as outputs. for more information, see section , master mode . 23.3.2 slave mode slave mode allows the dspi to communicate wit h spi bus masters. in this mode the dspi responds to externally controlled serial transfers. the dspi cannot initiate serial transfers in slave mode. in slave mode, the sck signal and the cs0_ x signal are configured as inputs and provided by a bus master. cs0_ x must be configured as input and pulled high. if the internal pullup is being used then the appropriate bits in the relevant siu_pcr must be set (siu_pcr [wpe = 1], [wps = 1]). for more information, see section , slave mode . 23.3.3 module disable mode the module disable mode is used for mcu power management. the clock to the non- memory mapped logic in the dspi is stopped while in module disable mode. the dspi enters the module disable mode when the mdis bit in dspi x _mcr is set. for more information, see section , module disable mode . RM0017 deserial serial peripheral interface (dspi) doc id 14629 rev 8 464/904 23.3.4 debug mode debug mode is used for system development and debugging. if the device enters debug mode while the frz bit in the dspi x _mcr is set, the dspi halts operation on the next frame boundary. if the device enters debug mode while the frz bit is cleared, the dspi behavior is unaffected and remains dictated by the module-specific mode and configuration of the dspi. for more information, see section , debug mode . 23.4 external signal description 23.4.1 signal overview table 222 lists off-chip dspi signals. 23.4.2 signal names and descriptions peripheral chip select / slave select (cs0_x ) in master mode, the cs0_x signal is a peripheral chip select output that selects the slave device to which the current transmission is intended. in slave mode, the cs0_x signal is a slave select input signal that allows an spi master to select the dspi as the target for transmissi on. cs0_x must be configured as input and pulled high. if the internal pullup is being used then the appropriate bits in the relevant siu_pcr must be set (siu_pcr [wpe = 1], [wps = 1]). set the ibe and obe bits in the siu_pcr for all cs0_x pins when the dspi chip select or slave select primary function is selected for that pin. when the pin is used for dspi master mode as a chip select output, set the obe bit. when the pin is used in dspi slave mode as a slave select input, set the ibe bit. table 222. signal properties name i/o type function master mode slave mode cs0_ x output / input peripheral chip select 0 slave select cs1:3_x output peripheral chip select 1?3 unused (1) 1. the siul allows you to select al ternate pin functions for the device. cs4_x output peripheral chip select 4 master trigger cs5_x output peripheral chip select 5 / peripheral chip select strobe unused (1) sin_x input serial data in serial data in sout_x output serial data out serial data out sck_x output / input serial clock (output) serial clock (input) deserial serial periphe ral interface (dspi) RM0017 465/904 doc id 14629 rev 8 peripheral chip selects 1?3 (cs1:3_x) cs1:3_x are peripheral chip select output signals in master mode. in slave mode these signals are not used. peripheral chip select 4 (cs4_x) cs4_x is a peripheral chip select output signal in master mode. peripheral chip select 5 / peripheral chip select strobe (cs5_x) cs5_x is a peripheral chip select output signal. when the dspi is in master mode and pcsse bit in the dspi x _mcr is cleared, the cs5_x signal is used to select the slave device that receives the current transfer. cs5_x is a strobe signal used by external logi c for deglitching of the cs signals. when the dspi is in master mode and the pcsse bit in the dspi x _mcr is set, the cs5_x signal indicates the timing to decode cs0:4_x signals, which prevents glitches from occurring. cs5_x is not used in slave mode. serial input (sin_ x ) sin_ x is a serial data input signal. serial output (sout_ x ) sout_ x is a serial data output signal. serial clock (sck_ x ) sck_ x is a serial communication clock signal. in master mode, the dspi generates the sck. in slave mode, sck_ x is an input from an external bus master. 23.5 memory map and register description 23.5.1 memory map table 223 shows the dspi memory map. table 223. dspi memory map base addresses: 0xfff9_0000 (dspi_0) 0xfff9_4000 (dspi_1) 0xfff9_8000 (dspi_2) address offset register location 0x00 dspi module configuration register (dspi x _mcr) on page 23-466 0x04 reserved 0x08 dspi transfer count register (dspi x _tcr) on page 23-469 RM0017 deserial serial peripheral interface (dspi) doc id 14629 rev 8 466/904 23.5.2 dspi module confi guration register (dspi x _mcr) the dspi x _mcr contains bits which configure attribut es of the dspi operation. the values of the halt and mdis bits can be changed at any time, but their effect begins on the next frame boundary. the halt and mdis bits in the dspi x _mcr are the only bit values software can change while the dspi is running. 0x0c dspi clock and transfer attributes register 0 (dspi x _ctar0) on page 23-470 0x10 dspi clock and transfer attributes register 1 (dspi x _ctar1) on page 23-470 0x14 dspi clock and transfer attributes register 2 (dspi x _ctar2) on page 23-470 0x18 dspi clock and transfer attributes register 3 (dspi x _ctar3) on page 23-470 0x1c dspi clock and transfer attributes register 4 (dspi x _ctar4) on page 23-470 0x20 dspi clock and transfer attributes register 5 (dspi x _ctar5) on page 23-470 0x24?0x28 reserved 0x2c dspi status register (dspi x _sr) on page 23-478 0x30 dspi interrupt request enable register (dspix_rser) on page 23-480 0x34 dspi push tx fifo register (dspi x _pushr) on page 23-482 0x38 dspi pop rx fifo register (dspi x _popr) on page 23-484 0x3c dspi transmit fifo register 0 (dspi x _txfr0) on page 23-485 0x40 dspi transmit fifo register 1 (dspi x _txfr1) on page 23-485 0x44 dspi transmit fifo register 2 (dspi x _txfr2) on page 23-485 0x48 dspi transmit fifo register 3 (dspi x _txfr3) on page 23-485 0x4c?0x78 reserved 0x7c dspi receive fifo register 0 (dspi x _rxfr0) on page 23-485 0x80 dspi receive fifo register 1 (dspi x _rxfr1) on page 23-485 0x84 dspi receive fifo register 2 (dspi x _rxfr2) on page 23-485 0x88 dspi receive fifo register 3 (dspi x _rxfr3) on page 23-485 table 223. dspi memory map (continued) base addresses: 0xfff9_0000 (dspi_0) 0xfff9_4000 (dspi_1) 0xfff9_8000 (dspi_2) address offset register location deserial serial periphe ral interface (dspi) RM0017 467/904 doc id 14629 rev 8 figure 222. dspi module c onfiguration register (dspi x _mcr) offset: 0x00 access: read/write 0123456789101112131415 r mstr cont_scke dconf frz mtfe pcsse rooe 00 pcsis5 pcsis4 pcsis3 pcsis2 pcsis1 pcsis0 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 mdis dis_txf dis_rxf clr_txf clr_rxf smpl_pt 0000000 halt w reset0100000000000001 table 224. dspi x _mcr field descriptions field description mstr master/slave mode select configures the dspi for master mode or slave mode. 0 dspi is in slave mode 1 dspi is in master mode cont_scke continuous sck enable enables the serial communication clock (sck) to run continuously. see section 23.6.6, continuous serial communications clock , for details. 0 continuous sck disabled 1 continuous sck enabled note: if the fifo is enabled with continuous sc k mode, the tx-fifo should be cleared before setting the cont_scke bit, and only the ctar0 register should be used to transfer attributes; otherwise, a change in sck frequency occurs. dconf dspi configuration the following table lists the dconf val ues for the various configurations. dconf configuration 00 spi 01 invalid value 10 invalid value 11 invalid value RM0017 deserial serial peripheral interface (dspi) doc id 14629 rev 8 468/904 frz freeze enables the dspi transfers to be stopped on the ne xt frame boundary when the device enters debug mode. 0 do not halt serial transfers 1 halt serial transfers mtfe modified timing format enable enables a modified transfer format to be used. see section , modified spi transfer format (mtfe = 1, cpha = 1) , for more information. 0 modified spi transfer format disabled 1 modified spi transfer format enabled pcsse peripheral chip select strobe enable enables the cs5_ x to operate as a cs strobe output signal. see section , peripheral chip select strobe enable (cs5_x) , for more information. 0cs5_ x is used as the peripheral chip select 5 signal 1cs5_ x as an active-low cs strobe signal rooe receive fifo overflow overwrite enable enables an rx fifo overflow condition to ignore the incoming serial data or to overwrite existing data. if the rx fifo is full and new data is receiv ed, the data from the tr ansfer that generated the overflow is ignored or put in the shift register. if the rooe bit is set, the incoming data is put in the shift register. if the rooe bit is cleared, the incoming data is ignored. see section , receive fifo overflow interrupt request (rfof) , for more information. 0 incoming data is ignored 1 incoming data is put in the shift register pcsis n peripheral chip select inactive state determines the inactive state of the cs0_ x signal. cs0_ x must be configured as inactive high for slave mode operation. 0 the inactive state of cs0_ x is low 1 the inactive state of cs0_ x is high mdis module disable allows the clock to stop to the non-memory mapped logic in the dspi, effectively putting the dspi in a software controlled power-saving state. see section 23.6.8, power saving features for more information. 0 enable dspi clocks 1 allow external logic to disable dspi clocks table 224. dspi x _mcr field descriptions (continued) field description deserial serial periphe ral interface (dspi) RM0017 469/904 doc id 14629 rev 8 23.5.3 dspi transfer count register (dspi x _tcr) the dspi x _tcr contains a counter that indicates the number of spi transfers made. the transfer counter is intended to assist in queue management. the user must not write to the dspi x _tcr while the dspi is running. dis_txf disable transmit fifo enables and disables the tx fifo. when the tx fifo is disabled, the transmit part of the dspi operates as a simplified double-buffered spi. see section , fifo disable operation for details. 0 tx fifo is enabled 1 tx fifo is disabled dis_rxf disable receive fifo enables and disables the rx fifo. when the rx fi fo is disabled, the receive part of the dspi operates as a simplified double-buffered spi. see section , fifo disable operation for details. 0 rx fifo is enabled 1rx fifo is disabled clr_txf clear tx fifo. clr_txf is used to flush the tx fi fo. writing a ?1? to clr_txf clears the tx fifo counter. the clr_txf bit is always read as zero. 0 do not clear the tx fifo counter 1 clear the tx fifo counter clr_rxf clear rx fifo. clr_rxf is used to flush the rx fifo. writing a ?1? to clr_rxf clears the rx counter. the clr_rxf bit is always read as zero. 0 do not clear the rx fifo counter 1 clear the rx fifo counter smpl_pt sample point allows the host software to select when the dspi master samples si n in modified transfer format. figure 237 shows where the master can sample the sin pin. the following table lists the delayed sample points. halt halt provides a mechanism for software to start and stop dspi transfers. see section 23.6.2, start and stop of dspi transfers , for details on the operation of this bit. 0 start transfers 1 stop transfers table 224. dspi x _mcr field descriptions (continued) field description smpl_pt number of system clock cycles between odd-numbered edge of sck_ x and sampling of sin_ x 00 0 01 1 10 2 11 reserved RM0017 deserial serial peripheral interface (dspi) doc id 14629 rev 8 470/904 23.5.4 dspi clock and transfer attributes registers 0?5 (dspi x _ctar n ) the dspi modules each contain six clock and transfer attribute registers (dspi x _ctar n ) which are used to define different transfer attribute configurations. each dspi x _ctar controls: frame size baud rate and transfer delay values clock phase clock polarity msb or lsb first dspi x _ctars support compatib ility with the qspi module in the spc560bx and spc560cx family of mcus. at the initiation of an spi transfer, control logic selects the dspi x _ctar that contains the transfer?s attributes. do not write to the dspi x _ctars while the dspi is running. in master mode, the dspi x _ctar n registers define combinations of transfer attributes such as frame size, clock phase and polarity, data bit ordering, baud rate, and various delays. in slave mode, a subset of the bit fields in the dspi x _ctar0 and dspi x _ctar1 registers are used to set the slave transfer attributes. see the individual bit descriptions for details on which bits are used in slave modes. when the dspi is configured as an spi master, the ctas field in the command portion of the tx fifo entry selects which of the dspi x _ctar registers is used on a per-frame basis. when the dspi is configured as an spi bus slave, the dspi x _ctar0 register is used. figure 223. dspi transfer count register (dspix_tcr) offset: 0x08 access: read/write 0123456789101112131415 r spi_tcnt w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 table 225. dspi x _tcr field descriptions field description spi_tcnt spi transfer counter counts the number of spi transfers the dspi makes. the spi_tcnt field is in cremented every time the last bit of an spi frame is transmitted. a value wri tten to spi_tcnt presets the counter to that value. spi_tcnt is reset to zero at the beginning of the frame when the ctcnt field is set in the executing spi command. the transfer count er ?wraps around,? incrementing the counter past 65535 resets the counter to zero. deserial serial periphe ral interface (dspi) RM0017 471/904 doc id 14629 rev 8 . figure 224. dspi clock and transf er attributes registers 0?5 (dspi x _ctarn) offsets: 0x0c?0x20 (6 re gisters) access: read/write 0123456789101112131415 r dbr fmsz cpol cpha lsbfe pcssck pasc pdt pbr w reset0111100000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cssck asc dt br w reset0000000000000000 table 226. dspi x _ctar n field descriptions field descriptions dbr double baud rate the dbr bit doubles the effective ba ud rate of the serial communications clock (sck). this field is only used in master mode. it effectively halves the baud rate division ratio supporting faster frequencies and odd division ratios for the serial communications clock (sck). when the dbr bit is set, the duty cycle of the serial communications clock (sck) depends on the value in the baud rate prescaler and the clock phase bit as listed in table 233 . see the br[0:3] field description for details on how to compute the baud rate. if the overall baud rate is divide by two or divide by three of the system clock then neither the continuous sck enable or th e modified timing format enable bits should be set. 0 the baud rate is computed normally with a 50/50 duty cycle 1 the baud rate is doub led with the duty cycl e depending on the baud rate prescaler fmsz frame size the fmsz field selects the number of bits transfe rred per frame. the fmsz field is used in master mode and slave mode. table 234 lists the frame size encodings. cpol clock polarity the cpol bit selects the inactive state of the serial communications clock (sck). this bit is used in both master and slave mode. for successful communication between serial devices, the devices must have identical clock polarities. when the continuous selection format is selected, switching between clock polarities without stopping the dspi can cause e rrors in the transfer due to the peripheral device interpreting the switch of clock polarity as a valid clock edge. 0 the inactive state value of sck is low 1 the inactive state value of sck is high cpha clock phase the cpha bit selects which edge of sck causes da ta to change and which edge causes data to be captured. this bit is used in both master an d slave mode. for successful communication between serial devices, the devices must have identical clock phase settings. continuous sck is only supported for cpha = 1. 0 data is captured on the leading edge of sck and changed on the following edge 1 data is changed on the leading edge of sck and captured on the following edge RM0017 deserial serial peripheral interface (dspi) doc id 14629 rev 8 472/904 lsbfe lsb first the lsbfe bit selects if the lsb or msb of the frame is transferred first. this bit is only used in master mode. 0 data is transferred msb first 1 data is transferred lsb first pcssck pcs to sck delay prescaler the pcssck field selects the prescaler value for the delay between assertion of pcs and the first edge of the sck. this field is only used in master mode. the table below lists the prescaler values. see the cssck field description for details on how to compute the pcs to sck delay. pasc after sck delay prescaler the pasc field selects the prescaler value for the delay between the last edge of sck and the negation of pcs. this field is only used in master mode. the table below lists the prescaler values. see the asc[0:3] field description for details on how to compute the after sck delay. pdt delay after transfer prescaler the pdt field selects the prescaler value for the del ay between the negation of the pcs signal at the end of a frame and the assertion of pcs at the begi nning of the next frame. the pdt field is only used in master mode. the table below lists the prescaler values. see the dt[0:3] field description for details on how to compute the delay after transfer. table 226. dspi x _ctar n field descriptions (continued) field descriptions pcssck pcs to sck delay prescaler value 00 1 01 3 10 5 11 7 pasc after sck delay prescaler value 00 1 01 3 10 5 11 7 pdt delay after transfer prescaler value 00 1 01 3 10 5 11 7 deserial serial periphe ral interface (dspi) RM0017 473/904 doc id 14629 rev 8 pbr baud rate prescaler the pbr field selects the prescaler value for the baud rate. this field is only used in master mode. the baud rate is the frequency of the serial communications clock (sck). the system clock is divided by the prescaler value before the baud rate selection takes place. the baud rate prescaler values are listed in the table below. see the br[0:3] field description for details on how to compute the baud rate. cssck pcs to sck delay scaler the cssck field selects the scaler value for the pcs to sck delay. this field is only used in master mode. the pcs to sck delay is the delay between t he assertion of pcs and the first edge of the sck. table 235 list the scaler values.the pcs to sck delay is a multiple of the system clock period and it is computed according to the following equation: equation 8 see section , cs to sck delay (tcsc) for more details. asc after sck delay scaler the asc field selects the scaler value for the after sc k delay. this field is only used in master mode. the after sck delay is the delay between the last edge of sck and the negation of pcs. ta bl e 2 3 6 lists the scaler values.the after sck delay is a multiple of the syst em clock period, an d it is computed according to the following equation: equation 9 see section , after sck delay (tasc) for more details. dt delay after transfer scaler the dt field selects the delay after transfer scaler. th is field is only used in master mode. the delay after transfer is the time between the negation of the pcs signal at the end of a frame and the assertion of pcs at the beginning of the next frame. table 237 lists the scaler values. in the continuous serial communications clock operation the dt value is fixed to one tsck. the delay after transfer is a multiple of the system clock period and it is computed according to the following equation: equation 10 see section , delay after transfer (tdt) for more details. table 226. dspi x _ctar n field descriptions (continued) field descriptions pbr baud rate prescaler value 00 2 01 3 10 5 11 7 t csc 1 f sys ----------- pcssck cssck = t asc 1 f sys ----------- pasc asc = t dt 1 f sys ----------- pdt dt = RM0017 deserial serial peripheral interface (dspi) doc id 14629 rev 8 474/904 br baud rate scaler the br field selects the scaler value for the baud ra te. this field is only used in master mode. the prescaled system clock is divided by the baud ra te scaler to generate the frequency of the sck. table 238 lists the baud rate scaler values.the baud rate is computed according to the following equation: equation 11 see section , cs to sck delay (tcsc) for more details. table 227. dspi sck duty cycle dbr cpha pbr sck duty cycle 0 any any 50/50 1 0 00 50/50 1 0 01 33/66 1 0 10 40/60 1 0 11 43/57 1 1 00 50/50 1 1 01 66/33 1 1 10 60/40 1 1 11 57/43 table 228. dspi transfer frame size fmsz frame size fmsz frame size 0000 reserved 1000 9 0001 reserved 1001 10 0010 reserved 1010 11 0011 4 1011 12 0100 5 1100 13 0101 6 1101 14 0110 7 1110 15 0111 8 1111 16 table 229. dspi pcs to sck delay scaler cssck pcs to sck delay scaler value cssck pcs to sck delay scaler value 0000 2 1000 512 0001 4 1001 1024 table 226. dspi x _ctar n field descriptions (continued) field descriptions sck baud rate f sys pbr ------------ - 1dbr + br ---------------------- - = deserial serial periphe ral interface (dspi) RM0017 475/904 doc id 14629 rev 8 0010 8 1010 2048 0011 16 1011 4096 0100 32 1100 8192 0101 64 1101 16384 0110 128 1110 32768 0111 256 1111 65536 table 230. dspi after sck delay scaler asc after sck delay scaler value asc after sck delay scaler value 0000 2 1000 512 0001 4 1001 1024 0010 8 1010 2048 0011 16 1011 4096 0100 32 1100 8192 0101 64 1101 16384 0110 128 1110 32768 0111 256 1111 65536 table 231. dspi delay after transfer scaler dt delay after transfer scaler valu e dt delay after transfer scaler value 0000 2 1000 512 0001 4 1001 1024 0010 8 1010 2048 0011 16 1011 4096 0100 32 1100 8192 0101 64 1101 16384 0110 128 1110 32768 0111 256 1111 65536 table 232. dspi baud rate scaler br baud rate scaler value br baud rate scaler value 0000 2 1000 256 0001 4 1001 512 0010 6 1010 1024 table 229. dspi pcs to sck delay scaler (continued) cssck pcs to sck delay scaler value cssck pcs to sck delay scaler value RM0017 deserial serial peripheral interface (dspi) doc id 14629 rev 8 476/904 0011 8 1011 2048 0100 16 1100 4096 0101 32 1101 8192 0110 64 1110 16384 0111 128 1111 32768 table 233. dspi sck duty cycle dbr cpha pbr sck duty cycle 0 any any 50/50 1 0 00 50/50 1 0 01 33/66 1 0 10 40/60 1 0 11 43/57 1 1 00 50/50 1 1 01 66/33 1 1 10 60/40 1 1 11 57/43 table 234. dspi transfer frame size fmsz frame size fmsz frame size 0000 reserved 1000 9 0001 reserved 1001 10 0010 reserved 1010 11 0011 4 1011 12 0100 5 1100 13 0101 6 1101 14 0110 7 1110 15 0111 8 1111 16 table 235. dspi pcs to sck delay scaler cssck pcs to sck delay scaler value cssck pcs to sck delay scaler value 0000 2 1000 512 0001 4 1001 1024 0010 8 1010 2048 table 232. dspi baud rate scaler (continued) br baud rate scaler value br baud rate scaler value deserial serial periphe ral interface (dspi) RM0017 477/904 doc id 14629 rev 8 0011 16 1011 4096 0100 32 1100 8192 0101 64 1101 16384 0110 128 1110 32768 0111 256 1111 65536 table 236. dspi after sck delay scaler asc after sck delay scaler value asc after sck delay scaler value 0000 2 1000 512 0001 4 1001 1024 0010 8 1010 2048 0011 16 1011 4096 0100 32 1100 8192 0101 64 1101 16384 0110 128 1110 32768 0111 256 1111 65536 table 237. dspi delay after transfer scaler dt delay after transfer scaler valu e dt delay after transfer scaler value 0000 2 1000 512 0001 4 1001 1024 0010 8 1010 2048 0011 16 1011 4096 0100 32 1100 8192 0101 64 1101 16384 0110 128 1110 32768 0111 256 1111 65536 table 238. dspi baud rate scaler br baud rate scaler value br baud rate scaler value 0000 2 1000 256 0001 4 1001 512 0010 6 1010 1024 0011 8 1011 2048 table 235. dspi pcs to sck delay scaler (continued) cssck pcs to sck delay scaler value cssck pcs to sck delay scaler value RM0017 deserial serial peripheral interface (dspi) doc id 14629 rev 8 478/904 23.5.5 dspi status register (dspi x _sr) the dspi x _sr contains status and flag bits. the bits are set by the hardware and reflect the status of the dspi and indicate the occurrence of events that can generate interrupt requests. software can clear flag bits in the dspi x _sr by writing a ?1? to clear it (w1c). writing a ?0? to a flag bit has no effect. this register may not be writ able in module disable mode due to the use of power saving mechanisms. 0100 16 1100 4096 0101 32 1101 8192 0110 64 1110 16384 0111 128 1111 32768 table 238. dspi baud rate scaler (continued) br baud rate scaler value br baud rate scaler value figure 225. dspi status register (dspi x _sr) offset: 0x2c access: r/w 0123456789101112131415 rtcf txrxs 0 eoqf tfuf0tfff00000 rfof 0 rfdf 0 w w1c w1c w1c w1c w1c w1c reset0000001000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r txctr txnxtptr rxctr popnxtptr w reset0000000000000000 table 239. dspi x _sr field descriptions field description tcf transfer complete flag indicates that all bits in a frame have been shifte d out. the tcf bit is set after the last incoming databit is sampled, but before the t asc delay starts. see section , classic spi tr ansfer format (cpha = 0) for details. 0 transfer not complete 1 transfer complete txrxs tx and rx status reflects the status of the dspi. see section 23.6.2, start and stop of dspi transfers for information on what clears and sets this bit. 0 tx and rx operations are disabled (dspi is in stopped state) 1 tx and rx operations are enabled (dspi is in running state) deserial serial periphe ral interface (dspi) RM0017 479/904 doc id 14629 rev 8 eoqf end of queue flag indicates that transmission in progress is the last entry in a queue. the eoqf bit is set when tx fifo entry has the eoq bit set in the command halfwo rd and the end of the transfer is reached. see section , classic spi transfer format (cpha = 0) for details. when the eoqf bit is set, the txrxs bit is automatically cleared. 0 eoq is not set in the executing command 1 eoq bit is set in the executing spi command note: eoqf does not function in slave mode. tfuf transmit fifo underflow flag indicates that an underflow condit ion in the tx fifo has occurred . the transmit underflow condition is detected only for dspi modules operating in sl ave mode and spi configurat ion. the tfuf bit is set when the tx fifo of a dspi oper ating in spi slave mode is empty, and a transfer is initiated by an external spi master. 0 tx fifo underflow has not occurred 1 tx fifo underflow has occurred tfff transmit fifo fill flag indicates that the tx fifo can be filled. provides a method for the dspi to request more entries to be added to the tx fifo. the tfff bit is set whil e the tx fifo is not full. the tfff bit can be cleared by writing ?1? to it, or an by acknowledgeme nt from the edam controller when the tx fifo is full. 0 tx fifo is full 1 tx fifo is not full rfof receive fifo overflow flag indicates that an overflow conditi on in the rx fifo has occurred. th e bit is set when the rx fifo and shift register are full and a transfer is initiated. 0 rx fifo overflow has not occurred 1 rx fifo overflow has occurred rfdf receive fifo drain flag indicates that the rx fifo can be drained. provides a method for the dspi to request that entries be removed from the rx fifo. the bit is set while the rx fifo is not empty. the rfdf bit can be cleared by writing ?1? to it, or by acknowledgem ent from the edam contro ller when the rx fifo is empty. 0 rx fifo is empty 1 rx fifo is not empty note: in the interrupt service routine, rfdf must be cleared only after the dspix_popr register is read. txctr tx fifo counter indicates the number of valid entries in the tx fifo. the txctr is incremented every time the dspi _pushr is written. the txctr is decrement ed every time an spi command is executed and the spi data is transferred to the shift register. table 239. dspi x _sr field descriptions (continued) field description RM0017 deserial serial peripheral interface (dspi) doc id 14629 rev 8 480/904 23.5.6 dspi interrupt requ est enable register (dspi x _rser) the dspi x _rser enables flag bits in the dspi x _sr to generate interrupt requests. do not write to the dspi x _rser while the dspi is running. txnxtptr transmit next pointer indicates which tx fifo entry is transmitted du ring the next transfer. the txnxtptr field is updated every time spi data is transferred from the tx fifo to the shift register. see section , transmit first in first out (t x fifo) buffering mechanism for more details. rxctr rx fifo counter indicates the number of entries in the rx fifo . the rxctr is decremented every time the dspi _popr is read. the rxctr is incr emented after the last incoming databit is sampled, but before the t asc delay starts. see section , classic spi transfer format (cpha = 0) for details. popnxtptr pop next pointer contains a pointer to the rx fifo entry that is returned when the dspi x _popr is read. the popnxtptr is updated when the dspi x _popr is read. see section , receive first in first out (rx fifo) buffering mechanism for more details. table 239. dspi x _sr field descriptions (continued) field description figure 226. dspi interrupt reque st enable register (dspix_rser) offset:0x30 access: read/write 0123456789101112131415 r tcf_re 00 eoqf_re tfuf_re 0 tfff_re tfff_dirs 0000 rfof_re 0 rfdf_re rfdf_dirs w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 deserial serial periphe ral interface (dspi) RM0017 481/904 doc id 14629 rev 8 table 240. dspix_rser field descriptions field description tcf_re transmission complete request enable enables tcf flag in the dspi x _sr to generate an interrupt request. 0 tcf interrupt requests are disabled 1 tcf interrupt requests are enabled eoqf_re dspi finished request enable enables the eoqf flag in the dspi x _sr to generate an interrupt request. 0 eoqf interrupt requests are disabled 1 eoqf interrupt requests are enabled tfuf_re transmit fifo underflow request enable the tfuf_re bit enables the tfuf flag in the dspi x _sr to generate an interrupt request. 0 tfuf interrupt requests are disabled 1 tfuf interrupt requests are enabled tfff_re transmit fifo fill request enable enables the tfff flag in the dspi x _sr to generate a request. the tfff_dirs bit selects an interrupt request. 0 tfff interrupt requests are disabled 1 tfff interrupt requests are enabled tfff_dirs transmit fifo fill interrupt request select selects an interrupt request. when the tfff flag bit in the dspi x _sr is set, and the tfff_re bit in the dspi x _rser is set, this bit selects an interrupt request. 0 interrupt request is selected 1reserved rfof_re receive fifo overflow request enable enables the rfof flag in the dspi x _sr to generate an interrupt requests. 0 rfof interrupt requests are disabled 1 rfof interrupt requests are enabled rfdf_re receive fifo drain request enable enables the rfdf flag in the dspi x _sr to generate a request. the rfdf_dirs bit selects an interrupt request. 0 rfdf interrupt requests are disabled 1 rfdf interrupt requests are enabled rfdf_dirs receive fifo drain interrupt request select selects an interrupt request. when the rfdf flag bit in the dspi x _sr is set, and the rfdf_re bit in the dspi x _rser is set, the rfdf_dirs bit selects an interrupt request. 0 interrupt request is selected 1reserved RM0017 deserial serial peripheral interface (dspi) doc id 14629 rev 8 482/904 23.5.7 dspi push tx fifo register (dspi x _pushr) the dspi x _pushr provides a means to write to the tx fifo. data written to this register is transferred to the tx fifo. see section , transmit first in first out (tx fifo) buffering mechanism , for more information. write accesses of 8 or 16 bits to the dspi x _pushr transfers 32 bits to the tx fifo. note: txdata is used in master and slave modes. figure 227. dspi push tx fifo register (dspi x _pushr) offset:0x34 access: read/write 0123456789101112131415 r cont ctas eoq ctcnt 00 00 pcs5 pcs4 pcs3 pcs2 pcs1 pcs0 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r txdata w reset0000000000000000 deserial serial periphe ral interface (dspi) RM0017 483/904 doc id 14629 rev 8 table 241. dspi x _pushr field descriptions field description cont continuous peripheral chip select enable selects a continuous selection format. the bit is used in spi master mode. the bit enables the selected cs signals to remain asserted between transfers. see section , continuous selection format , for more information. 0 return peripheral chip select signals to their inactive state between transfers 1 keep peripheral chip select signals asserted between transfers ctas clock and transfer attributes select selects which of the dspi x _ctars is used to set the transfer attributes for the spi frame. in spi slave mode, dspi x _ctar0 is used. the following table shows how the ctas values map to the dspi x _ctars. there are eight dspi x _ctars in the device dspi implementation. note: use in spi master mode only. eoq end of queue provides a means for host software to signal to the d spi that the current spi transfer is the last in a queue. at the end of the transfer the eoqf bit in the dspi x _sr is set. 0 the spi data is not the last data to transfer 1 the spi data is the last data to transfer note: use in spi master mode only. ctcnt clear spi_tcnt provides a means for host software to clear the spi transfer counter. the ctcnt bit clears the spi_tcnt field in the dspi x _tcr. the spi_tcnt field is cleared before transmission of the current spi frame begins. 0 do not clear spi_tcnt field in the dspi x _tcr 1 clear spi_tcnt field in the dspi x _tcr note: use in spi master mode only. ctas use clock and transfer attributes from 000 dspi x _ctar0 001 dspi x _ctar1 010 dspi x _ctar2 011 dspi x _ctar3 100 dspi x _ctar4 101 dspi x _ctar5 110 reserved 111 reserved RM0017 deserial serial peripheral interface (dspi) doc id 14629 rev 8 484/904 23.5.8 dspi pop rx fifo register (dspi x _popr) the dspi x _popr allows you to read the rx fifo. see section , receive first in first out (rx fifo) buffering mechanism for a description of the rx fifo operations. eight or 16-bit read accesses to the dspi x _popr fetch the rx fifo data, and update the counter and pointer. note: reading the rx fifo field fetches data from the rx fifo. once the rx fifo is read, the read data pointer is moved to the next entry in the rx fifo. therefore, read dspix_popr only when you need the data. for compatibility, configure the tlb entry for dspix_popr as guarded. pcs x peripheral chip select x selects which cs x signals are asserted for the transfer. 0 negate the cs x signal 1 assert the cs x signal note: use in spi master mode only. txdata tr a n s m i t d a t a holds spi data for transfer according to the associated spi command. note: use txdata in master and slave modes. table 241. dspi x _pushr field descriptions (continued) field description figure 228. dspi pop rx fifo register (dspi x _popr) offset:0x38 access: read 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rrxdata w reset0000000000000000 table 242. dspi x _popr field descriptions field description rxdata received data the rxdata field contains the spi da ta from the rx fifo entry pointed to by the pop next data pointer (popnxtptr). deserial serial periphe ral interface (dspi) RM0017 485/904 doc id 14629 rev 8 23.5.9 dspi transmit fi fo registers 0?3 (dspi x _txfr n ) the dspi x _txfr n registers provide visibility into th e tx fifo for debugging purposes. each register is an entry in the tx fifo. the registers are read-only and cannot be modified. reading the dspi x _txfr n registers does not alter the state of the tx fifo. the mcu uses four registers to implement the tx fifo, that is dspi x _txfr0?dspi x _txfr3 are used. dspi receive fifo registers 0?3 (dspi x _rxfr n ) the dspi x _rxfr n registers provide visibility into t he rx fifo for debugging purposes. each register is an entry in the rx fifo. the dspi x _rxfr registers are read-only. reading the dspi x _rxfr n registers does not alter the state of the rx fifo. the device uses four registers to implement the rx fifo, that is dspi x _rxfr0?dspi x _rxfr3 are used. figure 229. dspi transmit fifo register 0?3 (dspi x _txfr n ) offsets: 0x3c?0x48 (4 registers) access: read 0123456789101112131415 rtxcmd w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rtxdata w reset0000000000000000 table 243. dspi x _txfr n field descriptions field description txcmd transmit command contains the command that sets the tran sfer attributes for the spi data. see section 23.5.7, dspi push tx fifo register (dspix_pushr) , for details on the command field. txdata tr a n s m i t d a t a contains the spi data to be shifted out. RM0017 deserial serial peripheral interface (dspi) doc id 14629 rev 8 486/904 23.6 functional description the dspi supports full-duplex, synchronous serial communications between the mcu and peripheral devices. all communications are through an spi-like protocol. the dspi has one configuration, namely serial peripheral interface (spi), in which the dspi operates as a basic spi or a queued spi. the dconf field in the dspi x _mcr register determines the dspi configuration. see table 224 for the dspi configuration values. the dspi x _ctar0?dspi x _ctar5 registers hold clock and transfer attributes.the spi configuration can select which ctar to use on a frame by frame basis by setting the ctas field in the dspi x _pushr. the 16-bit shift register in the master and the 16-bit shift register in the slave are linked by the sout_ x and sin_ x signals to form a distributed 32-bit register. when a data transfer operation is performed, data is serially shifted a pre-determined number of bit positions. because the registers are linked, data is exchanged between the master and the slave; the data that was in the master?s shift register is now in the shift register of the slave, and vice versa. at the end of a transfer, the tcf bit in the dspi x _sr is set to indi cate a completed transfer. figure 231 illustrates how master and slave data is exchanged. figure 230. dspi receive fifo registers 0?3 (dspi x _rxfr n ) offsets: 0x7c?0x88 (4 registers) access: read 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rrxdata w reset0000000000000000 table 244. dspi x _rxfr n field description field description rxdata receive data contains the received spi data. deserial serial periphe ral interface (dspi) RM0017 487/904 doc id 14629 rev 8 figure 231. spi serial protocol overview the dspi has six peripheral chip select (cs x ) signals that are be used to select which of the slaves to communicate with. transfer protocols and timing properties are shar ed by the three dspi configurations; these properties are described independently of the configuration in section 23.6.5, transfer formats . the transfer rate and delay settings are described in section 23.6.4, dspi baud rate and clock delay generation . see section 23.6.8, power saving features , for information on the power-saving features of the dspi. 23.6.1 modes of operation the dspi modules have the follo wing available distinct modes: master mode slave mode module disable mode debug mode master, slave, and module disable modes are module-specific modes whereas debug mode is device-specific. the module-specific modes are determined by bits in the dspi x _mcr. debug mode is a mode that the entire device can enter in parallel with the dspi being configured in one of its module-specific modes. master mode in master mode the dspi can initiate comm unications with peripheral devices. the dspi operates as bus master when the mstr bit in the dspi x _mcr is set. the serial communications clock (sck) is controlled by the master dspi. all three dspi configurations are valid in master mode. in spi configuration, master mode transfer attributes are controlled by the spi command in the current tx fifo entry. the ctas field in the spi command selects which of the eight dspi x _ctars are used to set the transfer attributes. transfer attribute control is on a frame by frame basis. see section 23.6.3, serial peripheral interface (spi) configuration for more details. dspi master shift register baud rate generator dspi slave shift register sout_ x sin_ x sout_ x sin_ x sck_ x sck_ x cs_ x cs0_ x RM0017 deserial serial peripheral interface (dspi) doc id 14629 rev 8 488/904 slave mode in slave mode the dspi responds to transfers initiated by an spi master. the dspi operates as bus slave when the mstr bit in the dspi x _mcr is negated. the dspi slave is selected by a bus master by having the slave?s cs0_ x asserted. in slave mode the sck is provided by the bus master. all transfer attributes are controlled by the bus master, except the clock polarity, clock phase and the number of bits to transfer which must be configured in the dspi slave to communicate correctly. module disable mode the module disable mode is used for mcu power management. the clock to the non- memory mapped logic in the dspi is stopped while in module disable mode. the dspi enters the module disable mode when the mdis bit in dspi x _mcr is set. see section 23.6.8, power saving features , for more details on the module disable mode. debug mode the debug mode is used for system development and debugging. if the mcu enters debug mode while the frz bit in the dspi x _mcr is set, the dspi stops all serial transfers and enters a stopped state. if the mcu enters debug mode while the frz bit is cleared, the dspi behavior is unaffected and remains dictated by the module-specific mode and configuration of the dspi. the dspi enters debug mode when a debug request is asserted by an external controller. see figure 232 for a state diagram. 23.6.2 start and stop of dspi transfers the dspi has two operating states: stopped and running. the stat es are independent of dspi configuration. the de fault state of the dspi is st opped. in the stopped state no serial transfers are initiated in master mode and no transfers are responded to in slave mode. the stopped state is also a safe state for writing the various configuration registers of the dspi without causing undetermined results. the txrxs bit in the dspi x _sr is cleared in this state. in the running state, serial transfers take place. the txrxs bit in the dspix_sr is set in the running state. figure 232 shows a state diagram of the start and stop mechanism. deserial serial periphe ral interface (dspi) RM0017 489/904 doc id 14629 rev 8 figure 232. dspi start and stop state diagram the transitions are described in table 245 . state transitions from running to stopped occur on the next frame boundary if a transfer is in progress, or on the next system clock cycle if no transfers are in progress. 23.6.3 serial peripheral interface (spi) configuration the spi configuration transfers data serially using a shift register and a selection of programmable transfer attributes. the dspi is in spi configuration when the dconf field in the dspi x _mcr is 0b00. the spi frames can be from 4 to 16 bits long. the data to be transmitted can come from queues stored in sram external to the dspi. host software can transfer the spi data from the queues to a first-in first-out (fifo) buffer. the received data is stored in entries in the receive fifo (rx fifo) buffer. host software transfers the received data from the rx fifo to memory external to the dspi. running txrxs = 1 stopped txrxs = 0 reset power-on-reset 0 1 2 table 245. state transitions for start and stop of dspi transfers transition no. current state next state description 0 reset stopped generic power-on-reset transition 1 stopped running the dspi starts (transitions from stopped to running) when all of the following conditions are true: ? eoqf bit is clear ? debug mode is unselected or the frz bit is clear ? halt bit is clear 2 running stopped the dspi stops (transitions fr om running to stopped) after the current frame for any one of the following conditions: ? eoqf bit is set ? debug mode is selected and the frz bit is set ? halt bit is set RM0017 deserial serial peripheral interface (dspi) doc id 14629 rev 8 490/904 the fifo buffer operations are described in section , transmit first in first out (tx fifo) buffering mechanism , and section , receive first in first out (rx fifo) buffering mechanism . the interrupt request conditions are described in section 23.6.7, interrupt requests . the spi configuration supports two module-specific modes; master mode and slave mode. the fifo operations are similar for the master mode and slave mode. the main difference is that in master mode the dspi initiates and controls the transfer according to the fields in the spi command field of the tx fifo entry. in slave mode the dspi only responds to transfers initiated by a bus master external to the dspi and the spi command field of the tx fifo entry is ignored. spi master mode in spi master mode the dspi initiates the serial transf ers by controlling the serial communications clock (sck_ x ) and the peripheral chip select (cs x ) signals. the spi command field in the executing tx fifo entry determines which ctars are used to set the transfer attributes and which cs x signal to assert. the command field also contains various bits that help with queue management and transfer protocol. the data field in the executing tx fifo entry is loaded into the shift register and shifted out on the serial out (sout _x ) pin. in spi master mode, each spi frame to be transmitted has a command associated with it allowing for transfer attribute control on a frame by frame basis. see section 23.5.7, dspi push tx fifo register (dspix_pushr) , for details on the spi command fields. spi slave mode in spi slave mode the dspi responds to transfers initiated by an spi bus master. the dspi does not initiate transfers. certain transfer attr ibutes such as clock polarity, clock phase and frame size must be set for successful communi cation with an spi master. the spi slave mode transfer attributes are set in the dspi x _ctar0. fifo disable operation the fifo disable mechanisms allow spi transf ers without using the tx fifo or rx fifo. the dspi operates as a double-buffered simplified spi when the fifos are disabled. the tx and rx fifos are disabled separately. the tx fifo is disabled by writing a ?1? to the dis_txf bit in the dspi x _mcr. the rx fifo is disabled by writing a ?1? to the dis_rxf bit in the dspi x _mcr. the fifo disable mechanisms are transparent to the user and to host software; transmit data and commands are written to the dspi x _pushr and received data is read from the dspi x _popr. when the tx fifo is disabled, the tfff, tfuf, and txctr fields in dspi x _sr behave as if there is a one-entry fifo but the contents of the dspi x _txfrs and txnxtptr are undefined. when the rx fifo is disabled, the rfdf, rfof, and rxctr fields in the dspi x _sr behave as if there is a one-entry fifo but the contents of the dspi x _rxfrs and popnxtptr are undefined. disable the tx and rx fifos only if the fifo must be disabled as a requirement of the application's operating mode. a fifo must be disabled before it is accessed. failure to disable a fifo prior to a first fifo access is not supported, and can result in incorrect results. deserial serial periphe ral interface (dspi) RM0017 491/904 doc id 14629 rev 8 transmit first in first out (tx fifo) buffering mechanism the tx fifo functions as a buffer of spi data and spi commands for transmission. the tx fifo holds four entries, each consisting of a command field and a data field. spi commands and data are added to the tx fifo by writing to the dspi push tx fifo register (dspi x _pushr). tx fifo entries can only be removed from the tx fifo by being shifted out or by flushing the tx fifo. for more information on dspix_pushr, see section 23.5.7, dspi push tx fifo register (dspix_pushr) . the tx fifo counter field (txctr) in the dspi status register (dspi x _sr) indicates the number of valid entries in the tx fifo. the txctr is updated every time the dspi _pushr is written or spi data is transferred into the shift register from the tx fifo. see section 23.5.5, dspi status register (dspix_sr) for more information on dspi x _sr. the txnxtptr field indicates which tx fifo en try is transmitted during the next transfer. the txnxtptr contains the positive offset from dspi x _txfr0 in number of 32-bit registers. for example, txnxtptr equal to two means that the dspi x _txfr2 contains the spi data and command for the next transfer. the txnxtptr field is incremented every time spi data is transferred from the tx fifo to the shift register. filling the tx fifo host software can add (push) entries to the tx fifo by writing to the dspi x _pushr. when the tx fifo is no t full, the tx fifo f ill flag (tfff) in the dspi x _sr is set. the tfff bit is cleared when the tx fifo is full or alternatively by host software writing a ?1? to the tfff in the dspi x _sr. the tfff then generates an interrupt request. see section , transmit fifo f ill interrupt request (tfff) , for details. the dspi ignores attempts to push data to a full tx fifo; that is, the state of the tx fifo is unchanged. no error condition is indicated. draining the tx fifo the tx fifo entries are removed (drained) by shifting spi data out through the shift register. entries are transferred from the tx fifo to the shift register and shifted out as long as there are valid entries in the tx fifo. every time an entry is transferred from the tx fifo to the shift register, the tx fifo counter is decremented by one. at the end of a transfer, the tcf bit in the dspi x _sr is set to indicate the completion of a transfer. the tx fifo is flushed by writing a ?1? to the clr_txf bit in dspi x _mcr. if an external spi bus master initiates a transfer with a dspi slave while the slave?s dspi tx fifo is empty, the transmit fifo underflow flag (tfuf) in the slave?s dspi x _sr is set. see section , transmit fifo underflow interrupt request (tfuf) , for details. receive first in first out (rx fifo) buffering mechanism the rx fifo functions as a buffer for data received on the sin pin. the rx fifo holds four received spi data frames. spi data is added to the rx fifo at the completion of a transfer when the received data in the shift register is transferred into the rx fifo. spi data is removed (popped) from the rx fifo by reading the dspi x _popr register. rx fifo entries can only be removed from the rx fifo by reading the dspi x _popr or by flushing the rx fifo. see section 23.5.8, dspi pop rx fifo register (dspix_popr) for more information on the dspi x _popr. RM0017 deserial serial peripheral interface (dspi) doc id 14629 rev 8 492/904 the rx fifo counter field (rxctr) in the dspi status register (dspi x _sr) indicates the number of valid entries in the rx fifo. the rxctr is updated every time the dspi _popr is read or spi data is copied from the shift register to the rx fifo. the popnxtptr field in the dspi x _sr points to the rx fifo entry that is returned when the dspi x _popr is read. the popnxtptr contains the positive, 32-bit word offset from dspi x _rxfr0. for example, popnxtptr equ al to two means that the dspi x _rxfr2 contains the received spi data that is returned when dspi x _popr is read. the popnxtptr field is incremented every time the dspi x _popr is read. popnxtptr rolls over every four frames on the mcu. filling the rx fifo the rx fifo is filled with the received spi data from the shift register. while the rx fifo is not full, spi frames from the shift register are transferred to the rx fifo. every time an spi frame is transferred to the rx fifo the rx fifo counter is incremented by one. if the rx fifo and shift register are full and a transfer is initiated, the rfof bit in the dspi x _sr is set indicating an overflow condition. depending on the state of the rooe bit in the dspi x _mcr, the data from the transfer that generated the overflow is ignored or put in the shift register. if the rooe bit is set, the incoming data is put in the shift register. if the rooe bit is cleared, the incoming data is ignored. draining the rx fifo host software can remove (pop) entries from the rx fifo by reading the dspi x _popr. a read of the dspi x _popr decrements the rx fifo counter by one. attempts to pop data from an empty rx fifo are ignored, the rx fifo counter remains unchanged. the data returned from reading an empty rx fifo is undetermined. see section 23.5.8, dspi pop rx fifo register (dspix_popr) for more information on dspi x _popr. when the rx fifo is not empty, the rx fifo drain flag (rfdf) in the dspi x _sr is set. the rfdf bit is cleared when the rx_fifo is empty; alternatively the rfdf bit can be cleared by the host writing a ?1? to it. 23.6.4 dspi baud rate and clock delay generation the sck_ x frequency and the delay values for serial transfer are generated by dividing the system clock frequency by a prescaler and a scaler with the option of doubling the baud rate. figure 233 shows conceptually how the sck signal is generated. figure 233. communications clock prescalers and scalers prescaler 1 scaler 1 + dbr system clock sck_x deserial serial periphe ral interface (dspi) RM0017 493/904 doc id 14629 rev 8 baud rate generator the baud rate is the frequency of the serial communication clock (sck_ x ). the system clock is divided by a baud rate prescaler (defined by dspi x _ctar[pbr]) and baud rate scaler (defined by dspi x _ctar[br]) to produce sck_ x with the possibility of doubling the baud rate. the dbr, pbr, and br fields in the dspi x _ctars select the frequency of sck_ x using the following formula: table 246 shows an example of a computed baud rate. cs to sck delay (t csc ) the cs _x to sck _x delay is the length of time from assertion of the cs _x signal to the first sck _x edge. see figure 235 for an illustration of the cs _x to sck _x delay. the pcssck and cssck fields in the dspi x _ctar n registers select the cs _x to sck _x delay, and the relationship is expressed by the following formula: table 247 shows an example of the computed cs to sck _x delay. after sck delay (t asc ) the after sck _x delay is the length of time between the last edge of sck _x and the negation of cs _x . see figure 235 and figure 236 for illustrations of the after sck _x delay. the pasc and asc fields in the dspi x _ctar n registers select the after sck delay. the relationship between these variables is given in the following formula: sck baud rate f sys pbrprescalervalue ---------------------------------------------------------- 1dbr + brscalervalue -------------------------------------------- = table 246. baud rate computation example f sys pbr prescaler value br scaler value dbr value baud rate 64 mhz 0b00 2 0b0000 2 0 16 mbit/s 20 mhz 0b00 2 0b0000 2 1 10 mbit/s t csc = f sys cssck pcssck 1 table 247. cs to sck delay computation example pcssck prescaler value cssck scaler value f sys cs to sck delay 0b01 3 0b0100 32 64 mhz 1.5 s t asc = f sys asc pasc 1 RM0017 deserial serial peripheral interface (dspi) doc id 14629 rev 8 494/904 table 248 shows an example of the computed after sck delay. delay after transfer (t dt ) the delay after transfer is the length of time between negation of the cs x signal for a frame and the assertion of the cs x signal for the next frame. the pdt and dt fields in the dspi x _ctar n registers select the delay after transfer. see figure 235 for an illustration of the delay after transfer. the following formula expresses the pdt/dt/delay after transfer relationship: table 249 shows an example of the computed delay after transfer. peripheral chip select strobe enable (cs5_ x ) the cs5 _x signal provides a delay to allow the cs x signals to settle after transitioning thereby avoiding glitches. when the dspi is in master mode and pc sse bit is set in the dspi x _mcr, cs5 _x provides a signal for an external demultiplexer to decode the cs4_ x signals into as many as 32 glitch-free cs x signals. figure 234 shows the timing of the cs5 _x signal relative to cs signals. figure 234. peripheral chip select strobe timing table 248. after sck delay computation example pasc prescaler value asc scaler value f sys after sck delay 0b01 3 0b0100 32 64 mhz 1.5 s t dt = f sys dt pdt 1 table 249. delay after transfer computation example pdt prescaler value dt scaler value f sys delay after transfer 0b01 3 0b1110 32768 64 mhz 1.54 ms cs5_ x csx t pcssck t pasc deserial serial periphe ral interface (dspi) RM0017 495/904 doc id 14629 rev 8 the delay between the assertion of the cs x signals and the assertion of cs5 _x is selected by the pcssck field in the dspi x _ctar based on the following formula: at the end of the transfer the delay between cs5 _x negation and cs x negation is selected by the pasc field in the dspi x _ctar based on the following formula: table 250 shows an example of the computed t pcssck delay. table 251 shows an example of the computed the t pasc delay. 23.6.5 transfer formats the spi serial communication is controlled by the serial communications clock (sck_ x ) signal and the cs x signals. the sck_ x signal provided by the master device synchronizes shifting and sampling of the data by the sin_ x and sout_ x pins. the cs x signals serve as enable signals for the slave devices. when the dspi is the bus master, the cpol and cpha bits in the dspi clock and transfer attributes registers (dspi x _ctar n ) select the polarity and phase of the serial clock, sck_ x . the polarity bit selects the idle state of the sck_ x . the clock phase bit selects if the data on sout_ x is valid before or on the first sck_ x edge. when the dspi is the bus slave, cpol and cpha bits in the dspi x _ctar0 (spi slave mode) select the polarity and phase of the serial clock. even though the bus slave does not control the sck signal, clock polarity, clock phase and number of bits to transfer must be identical for the master device and the slave device to ensure proper transmission. the dspi supports four different transfer formats: classic spi with cpha = 0 classic spi with cpha = 1 modified transfer format with cpha = 0 modified transfer format with cpha = 1 t pcssck = pcssck f sys 1 t pa s c = pasc f sys 1 table 250. peripheral chip select strobe assert computation example pcssck prescaler f sys delay before transfer 0b11 7 64 mhz 109.4 ns table 251. peripheral chip select strobe negate computation example pasc prescaler f sys delay after transfer 0b11 7 64 mhz 109.4 ns RM0017 deserial serial peripheral interface (dspi) doc id 14629 rev 8 496/904 a modified transfer format is supported to allow for high-speed communication with peripherals that require longer setup times. the dspi can sample the incoming data later than halfway through the cycle to give the peripheral more setup time. the mtfe bit in the dspi x _mcr selects between classic spi format and modified transfer format. the classic spi formats are described in section , classic spi transfer format (cpha = 0) and section , classic spi transfer format (cpha = 1) . the modified transfer formats are described in section , modified spi transfer format (mtfe = 1, cpha = 0) and section , modified spi transfer format (mtfe = 1, cpha = 1) . in the spi configuration, the dspi provides the option of keeping the cs signals asserted between frames. see section , continuous selection format for details. deserial serial periphe ral interface (dspi) RM0017 497/904 doc id 14629 rev 8 classic spi transfer format (cpha = 0) the transfer format shown in figure 235 is used to communicate with peripheral spi slave devices where the first data bit is available on the first clock edge. in this format, the master and slave sample their sin_ x pins on the odd-numbered sck_ x edges and change the data on their sout_ x pins on the even-numbered sck_ x edges. figure 235. dspi transfer timing diagram (mtfe = 0, cpha = 0, fmsz = 8) the master initiates the transfer by placing its first data bit on the sout_ x pin and asserting the appropriate peripheral chip select signals to the slave device. the slave responds by placing its first data bit on its sout_ x pin. after the t csc delay has elapsed, the master outputs the first edge of sck_ x . this is the edge used by the master and slave devices to sample the first input data bit on their serial data input signals. at the second edge of the sck_ x the master and slave devices place their second data bit on their serial data output signals. for the rest of the frame the master and the slave sample their sin_ x pins on the odd-numbered clock edges and changes the data on their sout_ x pins on the even- numbered clock edges. after the last clock edge occurs a delay of t asc is inserted before the master negates the cs signals. a delay of t dt is inserted before a new frame transfer can be initiated by the master. for the cpha = 0 condition of the master, tcf and eoqf are set and the rxctr counter is updated at the next to last serial clock edge of the frame (edge 15) of figure 235 . for the cpha = 0 condition of the slave, tcf is set and the rxctr counter is updated at the last serial clock edge of the frame (edge 16) of figure 235 . sck (cpol = 0) pcs x / ss t asc sck (cpol = 1) master and slave sample master sout / slave sin master sin / slave sout bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 lsb msb msb lsb t dt t csc t csc msb first (lsbfe = 0): lsb first (lsbfe = 1): t csc = cscs to sck delay. t asc = after sck delay. t dt = delay after transfer (minimum cs idle time). master (cpha = 0): tcf and eoqf are set and rxctr counter is updated at next to last sck edge of frame (edge 15) slave (cpha = 0): tcf is set and rxctr counter is updated at last sck edge of frame (edge 16) 1234567891011121314 16 15 RM0017 deserial serial peripheral interface (dspi) doc id 14629 rev 8 498/904 classic spi transfer format (cpha = 1) this transfer format shown in figure 236 is used to communicate with peripheral spi slave devices that require the first sck_ x edge before the first data bit becomes available on the slave sout_ x pin. in this format the master and slave devices change the data on their sout_ x pins on the odd-numbered sck_ x edges and sample the data on their sin_ x pins on the even-numbered sck_ x edges. figure 236. dspi transfer timing diagram (mtfe = 0, cpha = 1, fmsz = 8) the master initiates the transfer by asserting the cs x signal to the slave. after the t csc delay has elapsed, the master generates the first sck_ x edge and at the same time places valid data on the master sout_ x pin. the slave responds to the first sck_ x edge by placing its first data bit on its slave sout_ x pin. at the second edge of the sck_ x the master and slave sample their sin_ x pins. for the rest of the frame the master and the slave change the data on their sout_ x pins on the odd- numbered clock edges and sample their sin_ x pins on the even-numbered clock edges. after the last clock edge occurs a delay of t asc is inserted before the master negates the cs x signal. a delay of t dt is inserted before a new frame transfer can be initiated by the master. for cpha = 1 the master eoqf and tcf and slave tcf are set at the last serial clock edge (edge 16) of figure 236 . for cpha = 1 the master and slave rxctr counters are updated on the same clock edge. slave (cpha = 1): tcf is set and rxctr counter is updated at last sck edge of frame (edge 16) sck 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (cpol = 0) pcsx / ss t asc sck (cpol = 1) master and slave sample master sout/ slave sin master sin/ slave sout bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 lsb msb msb lsb t dt t csc msb first (lsbfe = 0): lsb first (lsbfe = 1): t csc = cs to sck delay. t asc = after sck delay. t dt = delay after transfer (minimum cs negation time). master (cpha = 1): tcf and eoqf are set and rxctr counter is updated at last sck edge of frame (edge 16) 16 deserial serial periphe ral interface (dspi) RM0017 499/904 doc id 14629 rev 8 modified spi transfer format (mtfe = 1, cpha = 0) in this modified transfer format both the master and the slave sample later in the sck period than in classic spi mode to allow for delays in device pads and board traces. these delays become a more significant fraction of the sck period as the sck period decreases with increasing baud rates. note: for the modified transfer format to operate correctly, you must thoroughly analyze the spi link timing budget. the master and the slave place data on the sout_ x pins at the assertion of the cs x signal. after the cs x to sck_ x delay has elapsed the first sck_ x edge is generated. the slave samples the master sout_ x signal on every odd numbered sck_ x edge. the slave also places new data on the slave sout_ x on every odd numbered clock edge. the master places its second data bit on the sout_ x line one system clock after odd numbered sck_ x edge. the point where the master samples the slave sout_ x is selected by writing to the smpl_pt field in the dspi x _mcr. ta bl e 2 5 2 lists the number of system clock cycles between the active edge of sck_ x and the master sample point for different values of the smpl_pt bit field. the master sample point can be delayed by one or two system clock cycles. table 252. delayed master sample point smpl_pt number of system clock cycles between odd-numbered edge of sck and sampling of sin 00 0 01 1 10 2 11 invalid value RM0017 deserial serial peripheral interface (dspi) doc id 14629 rev 8 500/904 figure 237 shows the modified transfer format for cpha = 0. only the condition where cpol = 0 is illustrated. the de layed master sample points are indicated with a lighter shaded arrow. figure 237. dspi modified transfer format (mtfe = 1, cpha = 0, f sck = f sys / 4) modified spi transfer format (mtfe = 1, cpha = 1) at the start of a transfer the dspi asserts the cs signal to the slave device. after the cs to sck delay has elapsed the master and the slave put data on their sout pins at the first edge of sck. the slave samples the master sout signal on the even numbered edges of sck. the master samples the slave sout signal on the odd numbered sck edges starting with the third sck edge. the slave samples the last bit on the last edge of the sck. the master samples the last slave sout bit one half sck cycle after the la st edge of sck. no clock edge is visible on the master sck pin during the sampling of the last bit. the sck to cs delay must be greater or equal to half of the sck period. note: for the modified transfer format to operate correctly, you must thoroughly analyze the spi link timing budget. t csc = cs to sck delay. t asc = after sck delay. system clock 123456 cs x t asc sck master sample slave sout master sout system clock system clock slave sample t csc deserial serial periphe ral interface (dspi) RM0017 501/904 doc id 14629 rev 8 figure 238 shows the modified transfer format for cpha = 1. only the condition where cpol = 0 is described. figure 238. dspi modified transfer format (mtfe = 1, cpha = 1, f sck = f sys / 4) continuous selection format some peripherals must be deselected between every transfer. other peripherals must remain selected between several sequential serial transfers. the continuous selection format provides the flexibility to handle both cases. the continuous selection format is enabled for the spi configuration by setting the cont bit in the spi command. when the cont bit = 0, the dspi drives the asserted chip select signals to their idle states in between frames. the idle states of the chip select signals are selected by the pcsis field in the dspi x _mcr. t csc = cs to sck delay. t asc = after sck delay. system clock 123456 cs t asc sck master sample master sout slave sout slave sample t csc RM0017 deserial serial peripheral interface (dspi) doc id 14629 rev 8 502/904 figure 239 shows the timing diagram for two four-bit transfers with cpha = 1 and cont = 0. figure 239. example of non-continuous format (cpha = 1, cont = 0) when the cont = 1 and the cs signal for the next transfer is the same as for the current transfer, the cs signal remains asserted for the duration of the two transfers. the delay between transfers (t dt ) is not inserted between the transfers. figure 240 shows the timing diagram for two 4-bit transfers with cpha = 1 and cont = 1. figure 240. example of continuous transfer (cpha = 1, cont = 1) in figure 240 , the period length at the start of the next transfer is the sum of t asc and t csc ; that is, it does not include a half-clock period. the default settings for these provide a total of four system clocks. in many situations, t asc and t csc must be increased if a full half-clock period is required. sck (cpol = 0) csx t asc sck (cpol = 1) master sout t dt t csc t csc = cs to sck delay. t asc = after sck delay. t dt = delay after transfer (minimum cs negation time). master sin t csc sck (cpol = 0) cs t asc sck (cpol = 1) master sout t csc t csc t csc = cs to sck delay. t asc = after sck delay. master sin deserial serial periphe ral interface (dspi) RM0017 503/904 doc id 14629 rev 8 switching ctars between frames while using continuous selection can cause errors in the transfer. the cs signal must be negated before ctar is switched. when the cont bit = 1 and the cs signals for the next transfer are different from the present transfer, the cs signals behave as if the cont bit was not set. note: you must fill the txfifo wit h the number of entries that will be concatenated together under one pcs assertion for both master and slave before the txfifo becomes empty. for example; while transmitting in master mode, ensure that the last entry in the txfifo, after which txfifo becomes empty, has cont = 0 in the command frame. when operating in slave mode, ensure that when the last-entry in the txfifo is completely transmitted (i.e. the corresponding tcf flag is asserted and txfifo is empty) the slave is deselected for any further serial communication; otherwise, an underflow error occurs. clock polarity switching between dspi transfers if it is desired to switch polarity between non-continuous dspi frames, the edge generated by the change in the idle state of the clock occurs one system clock before the assertion of the chip select for the next frame. see section 23.5.4, dspi clock and transfer attributes registers 0?5 (dspix_ctarn) . in figure 241 , time ?a? shows the one clock interval. time ?b? is user programmable from a minimum of two system clocks. figure 241. polarity switching between frames 23.6.6 continuous serial communications clock the dspi provides the option of generating a continuous sck signal for slave peripherals that require a continuous clock. continuous sck is enabled by sett ing the cont_scke bit in the dspi x _mcr. continuous sck is valid in a ll configurations. continuous sck is only supported for cpha = 1. setting cpha = 0 is ignored if the cont_scke bit is set. continuous sck is supported for modified transfer format. cs system clock sck frame 1 frame 0 cpol = 0 cpol = 1 ab RM0017 deserial serial peripheral interface (dspi) doc id 14629 rev 8 504/904 clock and transfer attributes for the continuous sck mode are set according to the following rules: the tx fifo must be cleared before initiating any spi configuration transfer. when the dspi is in spi configuration, ctar0 is used initially. at the start of each spi frame transfer, the ctar specified by the ctas for the frame should be ctar0. in all configurations, the cu rrently selected ctar remains in use until the start of a frame with a different ctar specified, or the continuous sck mode is terminated. the device is designed to use the same baud rate for all transfers made while using the continuous sck. switching cl ock polarity between frames while using continuous sck can cause errors in the transfer. continuous sck operation is not guaranteed if the dspi is put into module disable mode. enabling continuous sck disables the cs to sck delay and the after sck delay. the delay after transfer is fixed at one sck cycle. figure 242 shows timing diagram for continuous sck format with continuous selection disabled. note: when in continuous sck mode, always use ctar0 for the spi transfer, and clear the txfifo using the mcr[clr_txf] field before initiating transfer. figure 242. continuous sck timing diagram (cont= 0) if the cont bit in the tx fifo entry is set, cs remains asserted between the transfers when the cs signal for the next transfer is the same as for the current transfer. figure 243 shows timing diagram for continuous sck format with continuous selection enabled. sck (cpol = 0) cs sck (cpol = 1) master sout t dt t dt = 1 sck master sin deserial serial periphe ral interface (dspi) RM0017 505/904 doc id 14629 rev 8 figure 243. continuous s ck timing diagram (cont=1) sck (cpol = 0) cs sck (cpol = 1) master sout master sin transfer 1 transfer 2 RM0017 deserial serial peripheral interface (dspi) doc id 14629 rev 8 506/904 23.6.7 interrupt requests the dspi has five conditions that can generate interrupt requests. table 253 lists the five conditions. each condition has a flag bit and a request enable bit. the flag bits are described in the section 23.5.5, dspi status register (dspix_sr) and the request enable bits are described in the section 23.5.6, dspi interrupt request enable register (dspix_rser) . the tx fifo fill flag (tfff) and rx fifo drain flag (rfdf) generate inte rrupt requests depending on the tfff_dirs and rfdf_dirs bits in the dspi x _rser. end of queue interrupt request (eoqf) the end of queue request indicates that the end of a transmit queue is reached. the end of queue request is generated when the eoq bit in the executing spi command is asserted and the eoqf_re bit in the dspi x _rser is set. see the eoq bit description in section 23.5.5, dspi status register (dspix_sr) . see figure 235 and figure 236 that illustrate when eoqf is set. transmit fifo fill interrupt request (tfff) the transmit fifo fill request indicates that t he tx fifo is not full. the transmit fifo fill request is generated when the number of entries in the tx fifo is less than the maximum number of possible entries, and the tfff_re bit in the dspi x _rser is set. the tfff_dirs bit in the dspi x _rser is used to generate an interrupt request. transfer complete interrupt request (tcf) the transfer complete request indicates the end of the transfer of a serial frame. the transfer complete request is generated at the end of each frame transfer when the tcf_re bit is set in the dspi x _rser. see the tcf bit description in section 23.5.5, dspi status register (dspix_sr) . see figure 235 and figure 236 that illustrate when tcf is set. transmit fifo underflow interrupt request (tfuf) the transmit fifo underflow request indicates that an underflow condition in the tx fifo has occurred. the transmit underflow condition is detected only for dspi modules operating in slave mode and spi configuration. the tfuf bit is set when the tx fifo of a dspi operating in slave mode and spi configuration is empty, and a transfer is initiated from an external spi master. if the tfuf bit is set while the tfuf_re bit in the dspi x _rser is set, an interrupt request is generated. table 253. interrupt request conditions condition flag end of transfer queue has been reached (eoq) eoqf current frame transfer is complete tcf tx fifo underflow has occurred tfuf rx fifo overflow occurred rfof a fifo overrun occurred (1) 1. the fifo overrun condition is created by oring the tfuf and rfof flags together. tfuf ored with rfof deserial serial periphe ral interface (dspi) RM0017 507/904 doc id 14629 rev 8 receive fifo drain interrupt request (rfdf) the receive fifo drain request indicates that the rx fifo is not empty. the receive fifo drain request is generated when the number of entries in the rx fifo is not zero, and the rfdf_re bit in the dspi x _rser is set. the rfdf_dirs bit in the dspi x _rser is used to generate an interrupt request. receive fifo overflow interrupt request (rfof) the receive fifo overflow request indicates that an overflow condition in the rx fifo has occurred. a receive fifo overflow request is generated when rx fifo and shift register are full and a transfer is initiated. the rfof_re bit in the dspi x _rser must be set for the interrupt request to be generated. depending on the state of the rooe bit in the dspi x _mcr, the data from the transfer that generated the overflow is either ignored or shifted in to the shift register. if the rooe bit is set, the incoming data is shifted in to the shift register. if the rooe bit is negated, the incoming data is ignored. fifo overrun request (tfuf) or (rfof) the fifo overrun request indicates that at least one of the fifos in the dspi has exceeded its capacity. the fifo overrun request is ge nerated by logically or?ing together the rx fifo overflow and tx fifo underflow signals. 23.6.8 power saving features the dspi supports the following power-saving strategies: module disable mode?clock gating of non-memory mapped logic clock gating of slave interface signals and clock to memory-mapped logic module disable mode module disable mode is a module-specific mode that the dspi can enter to save power. host software can initiate the module disable mode by writing a ?1? to the mdis bit in the dspi x _mcr. in module disable mode, the dspi is in a dormant state, but the memory mapped registers are still accessible . certain read or write operat ions have a different affect when the dspi is in the module disable mode. reading the rx fifo pop register does not change the state of the rx fifo. likewise, writing to the tx fifo push register does not change the state of the tx fifo. clearing either of the fifos does not have any effect in the module disable mode. changes to the dis_txf and dis_rxf fields of the dspi x _mcr does not have any affect in the module disable mode. in the module disable mode, all status bits and register flags in the dspi return the correct values when read, but writing to them has no affect. writing to the dspi x _tcr during module disable mode does not have an effect. interrupt request signals cannot be cleared while in the module disable mode. slave interface signal gating the dspi module enable signal is used to gate slave interface signals such as address, byte enable, read/write and data. this prevents toggling slave interface signals from consuming power unless the dspi is accessed. RM0017 deserial serial peripheral interface (dspi) doc id 14629 rev 8 508/904 23.7 initialization and application information 23.7.1 how to change queues dspi queues are not part of the dspi module, but the dspi includes features in support of queue management. queues are primarily supported in spi configuration. this section presents an example of how to change queues for the dspi. 1. the last command word from a queue is executed. the eoq bit in the command word is set to indicate to the dspi that this is the last entry in the queue. 2. at the end of the transfer, corresponding to the command word with eoq set is sampled, the eoq flag (eoqf) in the dspi x _sr is set. 3. the setting of the eoqf flag disables both serial transmission, and serial reception of data, putting the dspi in the stopped state. the txrxs bit is negated to indicate the stopped state. 4. ensure all received data in rx fifo has been transferred to memory receive queue by reading the rxcnt in dspi x _sr or by checking rfdf in the dspi x _sr after each read operation of the dspi x _popr. 5. flush tx fifo by writing a ?1 ? to the clr_txf bit in the dspi x _mcr register and flush the rx fifo by writing a ?1? to the clr_rxf bit in the dspi x _mcr register. 6. clear transfer count either by setting ctcnt bit in the command word of the first entry in the new queue or via cpu writing directly to spi_tcnt field in the dspi x _tcr. 7. enable serial transmission and serial reception of data by clearing the eoqf bit. 23.7.2 baud rate settings table 254 shows the baud rate that is generated based on the combination of the baud rate prescaler pbr and the baud rate scaler br in the dspi x _ctars. the values are calculated at a 64 mhz system frequency. deserial serial periphe ral interface (dspi) RM0017 509/904 doc id 14629 rev 8 table 254. baud rate values baud rate divider prescaler values (dspi_ctar[pbr]) 2357 baud rate scaler values (dspi_ctar[br]) 2 16.0 mhz 10.7 mhz 6.4 mhz 4.57 mhz 4 8 mhz 5.33 mhz 3.2 mhz 2.28 mhz 6 5.33 mhz 3.56 mhz 2.13 mhz 1.52 mhz 8 4 mhz 2.67 mhz 1.60 mhz 1.15 mhz 16 2 mhz 1.33 mhz 800 khz 571 khz 32 1 mhz 670 khz 400 khz 285 khz 64 500 khz 333 khz 200 khz 142 khz 128 250 khz 166 khz 100 khz 71.7 khz 256 125 khz 83.2 khz 50 khz 35.71 khz 512 62.5 khz 41.6 khz 25 khz 17.86 khz 1024 31.2 khz 20.8 khz 12.5 khz 8.96 khz 2048 15.6 khz 10.4 khz 6.25 khz 4.47 khz 4096 7.81 khz 5.21 khz 3.12 khz 2.23 khz 8192 3.90 khz 2.60 khz 1.56 khz 1.11 khz 16384 1.95 khz 1.31 khz 781 hz 558 hz 32768 979 hz 653 hz 390 hz 279 hz RM0017 deserial serial peripheral interface (dspi) doc id 14629 rev 8 510/904 23.7.3 delay settings table 255 shows the values for the delay after transfer (t dt ) that can be generated based on the prescaler values and the scaler values set in the dspi x _ctars. the values calculated assume a 64 mhz system frequency. 23.7.4 calculation of fifo pointer addresses the user has complete vi sibility of the tx and rx fifo cont ents through the fifo registers, and valid entries can be identified through a memory mapped pointer and a memory mapped counter for each fifo. the pointer to the first-in entry in each fifo is memory mapped. for the tx fifo the first-in pointer is the transmit next pointer (txnxtptr). for the rx fifo the first-in pointer is the pop next pointer (popnxtptr). see section , transmit first in first out (tx fifo) buffering mechanism , and section , receive first in first out (rx fifo) buffering mechanism , for details on the fifo operation. the tx fifo is chosen for the illustration, bu t the concepts carry over to the rx fifo. table 255. delay values delay prescaler values (dspi_ctar[pdt]) 1357 delay scaler values (dspi_ctar[dt]) 2 31.25 ns 93.75 ns 156.25 ns 218.75 ns 4 62.5 ns 187.5 ns 312.5 ns 437.5 ns 8 125 ns 375 ns 625 ns 875 ns 16 250 ns 750 ns 1.25 s 1.75 s 32 0.5 s 1.5 s 2.5 s 3.5 s 64 1 s 3 s 5 s 7 s 128 2 s 6 s 10 s 14 s 256 4 s 12 s 20 s 28 s 512 8 s 24 s 40 s 56 s 1024 16 s 48 s 80 s 112 s 2048 32 s 96 s 160 s 224 s 4096 64 s 192 s 320 s 448 s 8192 128 s 384 s 640 s 896 s 16384 256 s 768 s 1.28 ms 1.79 ms 32768 512 s 1.54 ms 2.56 ms 3.58 ms 65536 1.02 ms 3.07 ms 5.12 ms 7.17 ms deserial serial periphe ral interface (dspi) RM0017 511/904 doc id 14629 rev 8 figure 244 illustrates the concept of first-in and last-in fifo entries along with the fifo counter. figure 244. tx fifo pointers and counter address calculation for the first-in entry and last-in entry in the tx fifo the memory address of the first-in entry in the tx fifo is computed by the following equation: first-in entry address = txfifo base + 4 (txnxtptr) the memory address of the last-in entry in the tx fifo is computed by the following equation: last-in entry address = txfifo base + 4 x [(txctr + txnxtptr - 1) modulo txfifo depth] where: txfifo base = base add ress of transmit fifo txctr = transmit fifo counter txnxtptr = transmit next pointer tx fifo depth = transmit fifo depth, implementation specific address calculation for the first-in entry and last-in entry in the rx fifo the memory address of the first-in entry in the rx fifo is computed by the following equation: first-in entry address = rxfifo base + 4 x (popnxtptr) the memory address of the last-in entry in the rx fifo is computed by the following equation: last-in entry address = rxfifo base + 4 x [(rxctr + popnxtptr - 1) modulo rxfifo depth] entry c entry a (first in) ? 1 entry b entry d (last in) tx fifo base push tx fifo tx fifo counter shift register sout register transmit next data pointer ? ? ? ? + 1 (txnxtptr) RM0017 deserial serial peripheral interface (dspi) doc id 14629 rev 8 512/904 where: rxfifo base = base address of receive fifo rxctr = receive fifo counter popnxtptr = pop next pointer rx fifo depth = receive fifo depth, implementation specific timers RM0017 513/904 doc id 14629 rev 8 24 timers 24.1 introduction this chapter describes the timer modules implemented on the microcontroller: system timer module (stm) enhanced modular io subsystem (emios) periodic interrupt timer (pit) the microcontroller also has a real time clock / autonomous periodic interrupt (rtc/api) module. the main purpose of this is to provide a periodic device wakeup source. 24.2 technical overview this section gives a technical overview of each of the timers as well as detailing the pins that can be used to access the timer peripherals if applicable. figure 245 details the interaction between the timers and the edma, intc, ctu, and adc. RM0017 timers doc id 14629 rev 8 514/904 figure 245. interaction between timers and relevant peripherals intc emios 0 ctu emios0 ch[0..22, 24] emios 1 trigger [0..22, 24] trigger [32..54, 56] pit trigger [23] pit_ch[3] emios1 ch[0..22, 24] ch[0..27] ch[0..27] irq[141..154] emios0 ch[0..27]* irq[157..170] emios1 ch[0..27]* irq[59..61, 127..129] pit[0..2, 3..5] pit[0..5] adc 0 (10-bit) 24 24 1 14 14 6 pit_ch[2] pit trigger for injected adc conversions 1 ctu triggers for all adc channels single adc conversion per ctu channel note* there are 14 interrupt requests from the emios to the intc. emios channels are routed to the interru pt controller in pairs for example ch[0,1] ch[2,3] stm ch[0..3] irq[30..33] stm_ch[0..3] 4 timers RM0017 515/904 doc id 14629 rev 8 24.2.1 overview of the stm the stm is a 32-bit free running up-counter clocked by the system clock with a configurable 8-bit clock pre-scaler (divide by 1 to 256). the counter is disabled out of reset and must therefore be enabled by software prior to use. the counter value can be read at any time. the stm has four 32-bit compare channels. each channel can generate a unique interrupt on an exact match event with the free running counter. the stm is often used to analyse code execution times. by starting the stm and reading the timer before and after a task or function, you can make an accurate measurement of the time taken in clock cycles to perform the task. the stm can be configured to stop (freeze) or continue to run in debug mode and is available for use in all operating mode where the system clock is present (not standby or certain stop mode configurations) there are no external pins associated with the stm. 24.2.2 overview of the emios each emios offers a combination of pwm, output capture and input compare functions. there are different types of channel implemented and not every channel supports every emios function. the channel functionality also differs between each emios module. see section 24.4, enhanced modular io subsystem (emios) , for more details. each channel has its own independent 16-bit counter. to allow synchronization between channels, there are a number of shared counter busses that can be used as a common timing reference. these counter buses can be used in combination with the individual channel counters to provide advanced features such as centre aligned pwm with dead time insertion. once configured, the emios needs very little cpu intervention. interrupts, edma requests and ctu trigger requests can be raised based on emios flag and timeout events. the emios is clocked from the system clock via peripheral clock group 3 (with a maximum permitted clock frequency of 64 mhz). the emios can be used in all modes where the system clock is available (which excludes standby mode and stop mode when the system clock is turned off). the emios has an option to allow the emios counters to freeze or to continue running in debug mode. the ctu allows an emios event to trigger a single adc conversion via the ctu without any cpu intervention. without the ctu, the emios would have to trigger an interrupt request. the respective isr would then perform a software triggered adc conversion. this not only uses cpu resource, but also increases the latency between the emios event and the adc trigger. the emios "output pulse width modulation with trigger" mode (see section , output pulse width modulation with trigger (opwmt) mode ) allows a customisable trigger point to be defined at any point in the waveform period. this is extremely useful for led lighting applications where the trigger can be set to a point where the pwm output is high but after the initial inrush current to the led has occurred. the pwm trigger can then cause the ctu to perform a single adc conversion which in tu rn measures the operating conditions of the led to ensure it is working within specification. a watchdog feature on the adc allows channels to be monitored and if the results fall outwith a specific range an interrupt is triggered. this means that all of the measurement is without cpu intervention if the results are within range. RM0017 timers doc id 14629 rev 8 516/904 to make it easier to plan which pins to use for the emios, ta b l e 2 5 6 and ta bl e 2 5 7 show the emios channel numbers that are available on each pin. the color shading matches the channel configuration diagram in the emios section. table 256. emios_0 channel to pin mapping channel pin function channel pin function alt1 alt2 alt3 alt1 alt2 alt3 uc[0] pa[0] uc[16] pe[0] uc[1] pa [ 1 ] uc[17] pe[1] uc[2] pa [ 2 ] uc[18] pe[2] uc[3] pa[3], pb[11] uc[19] pe[3] uc[4] pa[4], pb[12] uc[20] pe[4] uc[5] pa[5], pb[13] uc[21] pe[5] uc[6] pa[6], pb[14] uc[22] pe[6], pf[5] pe[8] uc[7] pa[7], pb[15] uc[23] pe[7], pf[6] pe[9] uc[8] pa [ 8 ] uc[24] pg[10] pd[12] uc[9] pa [ 9 ] uc[25] pg[11] pd[13] uc[10] pa[10], pf[0] uc[26] pg[12] pd[14] uc[11] pa[11], pf[1] uc[27] pg[13] pd[15] uc[12] pc[12], pf[2] uc[13] pc[13], pf[3] uc[14] pc[14], pf[4] uc[15] pc[15] table 257. emios_1 channel to pin mapping channel pin function channel pin function alt1 alt2 alt3 alt1 alt2 alt3 uc[0] pg[14] uc[16] pg[7] uc[1] pg[15] uc[17] pg[8] uc[2] ph[0] uc[18] pg[9] uc[3] ph[1] uc[19] pe[12] uc[4] ph[2] uc[20] pe[13] uc[5] ph[3] ph[11] uc[21] pe[14] uc[6] ph[4] uc[22] pe[15] uc[7] ph[5] uc[23] pg[0] uc[8] ph[6] uc[24] pg[1] uc[9] ph[7] uc[25] pf[12] uc[10] ph[8] uc[26] pf[13] uc[11] pg[2] uc[27] pf[14] uc[12] pg[3] uc[13] pg[4] uc[14] pg[5] uc[15] pg[6] timers RM0017 517/904 doc id 14629 rev 8 24.2.3 overview of the pit the pit module consists of 6 periodic interrupt timers (pits) clocked from the system clock. out of reset, the pitis disabled. there is a global disable control bit for all of the pit timers. before using the timers, software must clear the appropriate disabled bit. each of the pit timers are effectively standalone entities and each have their own timer and control registers. the pit timers are 32-bit count down timers. to use them, you must first program an initial value into the ldval register. the timer will then start to count down and can be read at any time. once the timer reaches 0x0000_0000, a flag is set and the previous value is automatically re-loaded into the ldval register and the countdown starts again. the flag event can be routed to a dedicated intc interrupt if desired. the pit is also used to trigger other events: 1 pit channels can be used to trigger a ctu adc conversion (single) 1 pit channel can be used to directly trigger injected conversions on the adc the timers can be configured to stop (freeze) or to continue to run in debug mode. the pitis available in all modes where a system clock is generated. there are no external pins associated with the pit. 24.3 system timer module (stm) 24.3.1 introduction overview the system timer module (stm) is a 32-bit timer designed to support commonly required system and application software timing functions. the stm includes a 32-bit up counter and four 32-bit compare channels with a separate interrupt source for each channel. the counter is driven by the system clock divided by an 8-bit prescale value (1 to 256). features the stm has the following features: one 32-bit up counter with 8-bit prescaler four 32-bit compare channels independent interrupt source for each channel counter can be stopped in debug mode modes of operation the stm supports two device modes of operation: normal and debug. when the stm is enabled in normal mode, its counter runs continuously. in debug mode, operation of the counter is controlled by the frz bit in the stm_cr register. if the frz bit is set, the counter is stopped in debug mode, otherwise it continues to run. RM0017 timers doc id 14629 rev 8 518/904 24.3.2 external signal description the stm does not have any external interface signals. 24.3.3 memory map and register definition the stm programming model has fourteen 32-bit registers. the stm registers can only be accessed using 32-bit (word) accesses. attempted references using a different size or to a reserved address generates a bus error termination. memory map the stm memory map is shown in ta b l e 2 5 8 . register descriptions the following sections detail the individual registers within the stm programming model. table 258. stm memory map base address: 0xfff3_c000 address offset register location 0x0000 stm control register (stm_cr) on page 24-519 0x0004 stm counter value (stm_cnt) on page 24-519 0x0008?0x000c reserved 0x0010 stm channel 0 control register (stm_ccr0) on page 24-520 0x0014 stm channel 0 interrupt register (stm_cir0) on page 24-520 0x0018 stm channel 0 compare register (stm_cmp0) on page 24-521 0x001c reserved 0x0020 stm channel 1 control register (stm_ccr1) on page 24-520 0x0024 stm channel 1 interrupt register (stm_cir1) on page 24-520 0x0028 stm channel 1 compare register (stm_cmp1) on page 24-521 0x002c reserved 0x0030 stm channel 2 control register (stm_ccr2) on page 24-520 0x0034 stm channel 2 interrupt register (stm_cir2) on page 24-520 0x0038 stm channel 2 compare register (stm_cmp2) on page 24-521 0x003c reserved 0x0040 stm channel 3 control register (stm_ccr3) on page 24-520 0x0044 stm channel 3 interrupt register (stm_cir3) on page 24-520 0x0048 stm channel 3 compare register (stm_cmp3) on page 24-521 0x004c?0x3fff reserved timers RM0017 519/904 doc id 14629 rev 8 stm control register (stm_cr) the stm control register (stm_cr) includes the prescale value, freeze control and timer enable bits. stm count register (stm_cnt) the stm count register (stm_cnt) holds the timer count value. figure 246. stm control register (stm_cr) offset: 0x000 access: read/write 0123456789101112131415 r 0 0 0 0 0 00000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cps 0 0 00 00 frz ten w reset0000000000000000 table 259. stm_cr field descriptions field description cps counter prescaler. selects the clock divide value for the prescaler (1 - 256). 0x00 = divide system clock by 1 0x01 = divide system clock by 2 ... 0xff = divide system clock by 256 frz freeze. allows the timer counter to be stopped when the device enters debug mode. 0 = stm counter continues to run in debug mode. 1 = stm counter is stopped in debug mode. ten timer counter enabled. 0 = counter is disabled. 1 = counter is enabled. figure 247. stm count register (stm_cnt) offset: 0x004 access: read/write 0 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425262728293031 r cnt w reset00000000000000000000000000000000 RM0017 timers doc id 14629 rev 8 520/904 stm channel control register (stm_ccrn) the stm channel control register (stm_ccrn) has the enable bit for channel n of the timer. stm channel interrupt register (stm_cirn) the stm channel interrupt register (stm_cirn) has the interrupt flag for channel n of the timer. table 260. stm_cnt field descriptions field description cnt timer count value used as the time base for all cha nnels. when enabled, the counter increments at the rate of the system clock divided by the prescale value. figure 248. stm channel control register (stm_ccrn) offset: 0x10+0x10*n access: read/write 0123456789101112131415 r 0 0 0 0 0 00000000 0 00 w reset0000000000000 0 00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 00000000 0 0 0 000 cen w reset0000000000000 0 00 table 261. stm_ccrn field descriptions field description cen channel enable. 0 = the channel is disabled. 1 = the channel is enabled. timers RM0017 521/904 doc id 14629 rev 8 stm channel compare register (stm_cmpn) the stm channel compare register (stm_cmpn) holds the compare value for channel n. 24.3.4 functional description the system timer module (stm) is a 32-bit timer designed to support commonly required system and application software timing functions. the stm includes a 32-bit up counter and four 32-bit compare channels with a separate interrupt source for each channel. the stm has one 32-bit up counter (stm_cnt) that is used as the time base for all channels. when enabled, the counter increments at the system clock frequency divided by a prescale value. the stm_cr[cps] field sets the divider to any value in the range from 1 to figure 249. stm channel interrupt register (stm_cirn) offset: 0x14+0x10*n access: read/write 0123456789101112131415 r 0 0 0 0 0 00000000 0 00 w reset0000000000000 0 00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 00000000 0 0 0 000cif w w1c reset0000000000000 0 00 table 262. stm_cirn field descriptions field description cif channel interrupt flag 0 = no interrupt request. 1 = interrupt request due to a match on the channel. figure 250. stm channel compare register (stm_cmpn) offset: 0x18+0x10*n access: read/write 012345678910111213141516171819202122232425262728293031 r cmp w reset00000000000000000000000000000000 table 263. stm_cmpn field descriptions field description cmp compare value for channel n. if the stm_ccrn[cen] bit is set and the stm_cmpn register matches the stm_cnt register, a channel interrupt request is generated and the stm_cirn[cif] bit is set. RM0017 timers doc id 14629 rev 8 522/904 256. the counter is enabled with the stm_cr[ten] bit. when enabled in normal mode the counter continuously increments. when enabled in debug mode the counter operation is controlled by the stm_cr[frz] bit. when the stm_cr[frz] bit is set, the counter is stopped in debug mode, otherwise it continues to run in debug mode. the counter rolls over at 0xffff_ffff to 0x0000_0000 with no restrictions at this boundary. the stm has four identical compare channels. each channel includes a channel control register (stm_ccrn), a channel interrupt register (stm_cirn) and a channel compare register (stm_cmpn). the channel is enabled by setting the stm_ccrn[cen] bit. when enabled, the channel will set th e stm_cir[cif] bit and generat e an interrupt request when the channel compare register matches the timer counter. the interrupt request is cleared by writing a 1 to the stm_cirn[cif] bit. a write of 0 to the stm_cirn[cif] bit has no effect. note: stm counter does not advance when the system clock is stopped. 24.4 enhanced modular io subsystem (emios) 24.4.1 introduction overview of the emios module the emios provides functionality to generate or measure time events. each channel provides a subset of the functionality available in the unified channel, at a resolution of 16 bits, and provides a user interface that is consistent with previous emios implementations. features of the emios module 2 emios blocks with 28 channels each ? 50 channels with opwmt, which can be connected to the ctu ? 6 channels with single action ic/oc ? both emios blocks can be synchronized 1 global prescaler 16-bit data registers 10 x 16-bit wide counter buses ? counter buses b, c, d, and e can be driven by unified channel 0, 8, 16, and 24, respectively ? counter bus a is driven by the unified channel #23 ? several channels have their own time base, alternative to the counter buses ? shared timebases through the counter buses ? synchronization among timebases control and status bits grouped in a single register shadow flag register state of the uc can be frozen for debug purposes motor contro l capability timers RM0017 523/904 doc id 14629 rev 8 modes of operation the unified channels can be configur ed to operate in the following modes: general purpose input/output single action input capture single action output compare input pulse width measurement input period measurement double action output compare modulus counter modulus counter buffered output pulse width and frequency modulation buffered output pulse width modulation buffered output pulse width modulation with trigger center aligned output pulse width modulation buffered these modes are described in section , uc modes of operation . each channel can have a specific set of modes implemented, according to device requirements. if an unimplemented mode (reserved) is selected, the results are unpredictable such as writing a reserved value to mode[0:6] in section , emios uc control register (emiosc[n]) . channel implementation figure 251 shows the channel configuration of the emios blocks. RM0017 timers doc id 14629 rev 8 524/904 figure 251. channel configuration key daoc dual action output compare gpio general purpose input output ipm input period measurement ipwm input pulse width measurement mc modulus counter mcb buffered modulus counter opwmb buffered output pulse width modulation opwmt buffered output pulse width modulation with trigger opwfmb buffered output pulse width and frequency modulation opwmcb center aligned output pwm buffered with dead-time saic single action input capture saoc single action output compare ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch8 ch9 ch10 ch11 ch12 ch13 ch14 ch15 ch16 ch17 ch18 ch19 ch24 ch25 ch26 ch27 ch20 ch21 ch22 ch23 global prescaler 8-bit counter counter bus_b counter bus_a counter bus_c counter bus_d counter bus_e bus clk channel functionality type x type y ?mc, mcb ?opwmt ?opwmb ?opwfmb ? saic, saoc ?gpio type h ?opwmt ?opwmb ?ipwm, ipm ?daoc ? saic, saoc ?gpio ?opwmt ?opwmb ? saic, saoc ?gpio emios_0 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch8 ch9 ch10 ch11 ch12 ch13 ch14 ch15 ch16 ch17 ch18 ch19 ch24 ch25 ch26 ch27 ch20 ch21 ch22 ch23 global prescaler 8-bit counter counter bus_b counter bus_a counter bus_c counter bus_d counter bus_e bus clk emios_1 type g ?mcb ?opwmt ?opwmb ?opwfmb ?opwmcb ?ipwm, ipm ?daoc ? saic, saoc ?gpio typef ? saic, saoc ?gpio timers RM0017 525/904 doc id 14629 rev 8 channel mode selection channel modes are selected using the mode selection bits mode[0:6] in the emios uc control register (emiosc[n]). ta bl e 2 7 6 provides the specific mode selection settings for the emios implementation on this device. 24.4.2 external signal description for information on emios external signals on this device, please refer to the signal description chapter of the reference manual. 24.4.3 memory map and register description memory maps the overall address map organization is shown in ta bl e 2 6 4 . unified channel memory map table 264. emios memory map base addresses: 0xc3fa_0000 (emios_0) 0xc3fa_4000 (emios_1) address offset description location 0x000?0x003 emios module config uration register (emiosmcr) on page 24- 526 0x004?0x007 emios global flag (emiosgflag) register on page 24- 527 0x008?0x00b emios output update disable (emiosoudis) register on page 24- 528 0x00c?0x00f emios disable channel (emiosucdis) register on page 24- 529 0x010?0x01f reserved ? 0x020?0x11f channel [0] to channel [7] ? 0x120?0x21f channel [8] to channel [15] ? 0x220?0x31f channel [16] to channel [23] ? 0x320?0x39f channel [24] to channel [27] ? 0x3a0?0xfff reserved ? RM0017 timers doc id 14629 rev 8 526/904 addresses of unified channel registers are specified as offsets from the channel?s base address; otherwise the emios base address is used as reference. table 265 describes the unified channel memory map. register description all control registers are 32 bits wide. data regi sters and counter registers are 16 bits wide. emios module configuration register (emiosmcr) the emiosmcr contains global control bits for the emios block. table 265. unified channel memory map uc[n] base address description location 0x00 emios uc a register (emiosa[n]) on page 24-529 0x04 emios uc b register (emiosb[n]) on page 24-530 0x08 emios uc counter register (emioscnt[n]) on page 24-531 0x0c emios uc control register (emiosc[n]) on page 24-531 0x10 emios uc status register (emioss[n]) on page 24-536 0x14 emios uc alternate a register (emiosalta[n]) on page 24-537 0x18?0x1f reserved ? figure 252. emios module configuration register (emiosmcr) address: emios base address +0x00 0123456789101112131415 r0 mdis frz gtbe 0 gpren 0000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r gpre 00000000 w reset0000000000000000 table 266. emiosmcr field descriptions field description mdis module disable puts the emios in low power mode. the mdis bit is used to stop the clock of the block, except the access to register s emiosmcr, emiosoudis and emiosucdis. 1 = enter low power mode 0 = clock is running timers RM0017 527/904 doc id 14629 rev 8 emios global flag (emiosgflag) register the emiosgflag is a read-only register that groups the flag bits (f[27:0]) from all channels. this organization improves interrupt handling on simpler devices. each bit relates to one channel. for unified channels these bits are mirrors of the flag bits in the emioss[n] register. frz freeze enables the emios to freeze the registers of the unified channels when debug mode is requested at mcu level. each unified channel should have fren bit set in order to enter freeze state. while in freeze state, the emios cont inues to operate to allow the mcu access to the unified channels registers. the unified channel will remain frozen un til the frz bit is written to ?0? or the mcu exits debug mode or the unified channel fren bit is cleared. 1 = stops unified channels operation when in debug mode and the fren bit is set in the emiosc[n] register 0 = exit freeze state gtbe global time base enable the gtbe bit is used to export a global time ba se enable from the module and provide a method to start time bases of several blocks simultaneously. 1 = global time base enable out signal asserted 0 = global time base enable out signal negated note: the global time base enable input pin controls the internal counters. when asserted, internal counters are enabled. when ne gated, internal counters disabled. gpren global prescaler enable the gpren bit enables the prescaler counter. 1 = prescaler enabled 0 = prescaler disabled (no clock) and prescaler counter is cleared gpre global prescaler the gpre bits select the clock divider value for the global prescaler, as shown in table 267 . table 267. global pres caler clock divider gpre divide ratio 00000000 1 00000001 2 00000010 3 00000011 4 . . . . . . . . 11111110 255 11111111 256 table 266. emiosmcr field descriptions (continued) field description RM0017 timers doc id 14629 rev 8 528/904 emios output update disable (emiosoudis) register figure 253. emios global fl ag (emiosgflag) register address: emios base address +0x04 0123456789101112131415 r 0 0 0 0 f27 f26 f25 f24 f23 f 22 f21 f20 f19 f18 f17 f16 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r f15 f14 f13 f12 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 f0 w reset0000000000000000 table 268. emiosgfla g field descriptions field description fn channel [n] flag bit figure 254. emios output update disable (emiosoudis) register address: emios base address +0x08 0123456789101112131415 r0000 ou27 ou26 ou25 ou24 ou23 ou22 ou21 ou20 ou19 ou18 ou17 ou16 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ou15 ou14 ou13 ou12 ou11 ou10 ou9 ou8 ou7 ou6 ou5 ou4 ou3 ou2 ou1 ou0 w reset0000000000000000 table 269. emiosoudi s field descriptions field description oun channel [n] output update disable bit when running mc, mcb or an output mode, values are written to registers a2 and b2. ou[n] bits are used to disable transfers from registers a2 to a1 and b2 to b1. each bit controls one channel. 1 = transfers disabled 0 = transfer enabled. depending on the operation mode, transfer may occur immediately or in the next period. unless stated otherwise, transfer occurs immediately. timers RM0017 529/904 doc id 14629 rev 8 emios disable channel (emiosucdis) register emios uc a register (emiosa[n]) depending on the mode of operation, internal registers a1 or a2, used for matches and captures, can be assigned to address emiosa[n]. both a1 and a2 are cleared by reset. figure 255. emios enable channel (emiosucdis) register address: emios base address +0x0c 0123456789101112131415 r0000 chdis27 chdis26 chdis25 chdis24 chdis23 chdis22 chdis21 chdis20 chdis19 chdis18 chdis17 chdis16 w reset 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r chdis15 chdis14 chdis13 chdis12 chdis11 chdis10 chdis9 chdis8 chdis7 chdis6 chdis5 chdis4 chdis3 chdis2 chdis1 chdis0 w reset 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 table 270. emiosucdis field descriptions field description chdisn enable channel [n] bit the chdis[n] bit is used to disable each of the channels by stopping its respective clock. 1 = channel [n] disabled 0 = channel [n] enabled figure 256. emios uc a register (emiosa[n]) address: uc[n] base address + 0x00 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r a w reset0000000000000000 RM0017 timers doc id 14629 rev 8 530/904 figure 271 summarizes the emiosa[n] writing and reading accesses for all operation modes. for more information see section , uc modes of operation . emios uc b register (emiosb[n]) depending on the mode of operation, internal registers b1 or b2 can be assigned to address emiosb[n]. both b1 and b2 are cleared by reset. ta b l e 2 7 1 summarizes the emiosb[n] writing and reading accesses for all operation modes. for more information see section , uc modes of operation . depending on the channel configuration, it may have emiosb register or not. this means that, if at least one mode that requires the register is implemented, then the register is present; otherwise it is absent. figure 257. emios uc b register (emiosb[n]) address: uc[n] base address + 0x04 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r b w reset0000000000000000 table 271. emiosa[n], emiosb[n] and emiosalta[n] values assignment operation mode register access write read write read alt write alt read gpio a1, a2 a1 b1,b2 b1 a2 a2 saic (1) 1. in these modes, the register emiosb[n] is not used, but b2 can be accessed. ?a2b2b2? ? saoc (1) a2 a1 b2 b2 ? ? ipwm ? a2 ? b1 ? ? ipm ? a2 ? b1 ? ? daoc a2 a1 b2 b1 ? ? mc (1) a2 a1 b2 b2 ? ? opwmt a1a1b2b1a2a2 mcb (1) a2 a1 b2 b2 ? ? opwfmb a2 a1 b2 b1 ? ? opwmcb a2 a1 b2 b1 ? ? opwmb a2a1b2b1 ? ? timers RM0017 531/904 doc id 14629 rev 8 emios uc counter register (emioscnt[n]) the emioscnt[n] register contains the value of the internal counter. when gpio mode is selected or the channel is frozen, the emioscnt[n] register is read/write. for all others modes, the emioscnt[n] is a read-only register. when entering some operation modes, this register is automatically cleared (refer to section , uc modes of operation for details). depending on the channel configuration it may have an internal counter or not. it means that if at least one mode that requires the counter is implemented, then the counter is present; otherwise it is absent. channels of type x and g have the internal counter enabled, so their timebase can be selected by channel's bsl[1:0]=11:emios_a - channels 0 to 8, 16, 23 and 24, emios_b = channels 0, 8, 16, 23 and 24. other channels from the above list don't have internal counters. emios uc control register (emiosc[n]) the control register gathers bits reflecting the status of the uc input/output signals and the overflow condition of the internal counter, as well as several read/write control bits. figure 258. emios uc counter register (emioscnt[n]) address: uc[n] base address + 0x08 0123456789101112131415 r0000000000000000 w (1) 1. in gpio mode or freeze acti on, this regist er is writable. reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rc w (1) reset0000000000000000 RM0017 timers doc id 14629 rev 8 532/904 figure 259. emios uc control register (emiosc[n]) address: uc[n] base address + 0x0c 0123456789101112131415 r fren 000 ucpre ucpren dma 0 if fck fen 0 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000 bsl edsel edpol mode w forcma forcmb reset0000000000000000 table 272. emiosc[n] field descriptions field description fren freeze enable bit the fren bit, if set and validated by frz bit in emiosmcr register allows the channel to enter freeze state, freezing all registers values when in debug mode and allowing the mcu to perform debug functions. 1 = freeze uc registers values 0 = normal operation ucpre prescaler bits the ucpre bits select the clock divider value fo r the internal prescaler of unified channel, as shown in ta b l e 2 7 3 . ucpren prescaler enable bit the ucpren bit enables the prescaler counter. 1 = prescaler enabled 0 = prescaler disabled (no clock) dma direct memory access bit the dma bit selects if the flag generation will be used as an interrupt or as a ctu trigger. 1 = flag/overrun assigned to ctu trigger 0 = flag/overrun assigned to interrupt request if input filter the if field controls the programmable input filter , selecting the minimum input pulse width that can pass through the filter, as shown in ta b l e 2 7 4 . for output modes, these bits have no meaning. fck filter clock select bit the fck bit selects the clock source for the programmable input filter. 1 = main clock 0 = prescaled clock timers RM0017 533/904 doc id 14629 rev 8 fen flag enable bit the fen bit allows the unified channel flag bit to generate an interrupt signal or a ctu trigger signal (the type of signal to be generated is defined by the dma bit). 1 = enable (flag will generate an interrupt request or a ctu trigger) 0 = disable (flag does not generate an interrupt request or a ctu trigger) forcma force match a bit for output modes, the forcma bit is equivalent to a successful comparison on comparator a (except that the flag bit is not set). this bit is cl eared by reset and is always read as zero. this bit is valid for every output operation mode which us es comparator a, othe rwise it has no effect. 1 = force a match at comparator a 0 = has no effect note: for input modes, the forcma bit is not used and writing to it has no effect. forcmb force match b bit for output modes, the forcmb bit is equivalent to a successful comparison on comparator b (except that the flag bit is not set). this bit is cl eared by reset and is always read as zero. this bit is valid for every output operation mode which us es comparator b, otherwise it has no effect. 1 = force a match at comparator b 0 = has not effect note: for input modes, the forcmb bit is not used and writing to it has no effect. bsl bus select the bsl field is used to select either one of the co unter buses or the internal counter to be used by the unified channel. refer to ta bl e 2 7 5 for details. edsel edge selection bit for input modes, the edsel bit selects whether the internal counter is triggered by both edges of a pulse or just by a single edge as defined by the edpol bit. when not shown in the mode of operation description, this bit has no effect. 1 = both edges triggering 0 = single edge triggering defined by the edpol bit for gpio in mode, the edsel bit selects if a flag can be generated. 1 = no flag is generated 0 = a flag is generated as defined by the edpol bit for saoc mode, the edsel bit selects the behavior of the output flip-flop at each match. 1 = the output flip-flop is toggled 0 = the edpol value is transferred to the output flip-flop edpol edge polarity bit for input modes, the edpol bit asserts which edge trig gers either the internal counter or an input capture or a flag. when not shown in the mode of operation description, this bit has no effect. 1 = trigger on a rising edge 0 = trigger on a falling edge for output modes, the edpol bit is used to select the logic level on the output pin. 1 = a match on comparator a sets the output flip-flop, while a match on comparator b clears it 0 = a match on comparator a clea rs the output flip-flop, while a match on comparator b sets it table 272. emiosc[n] field descriptions (continued) field description RM0017 timers doc id 14629 rev 8 534/904 mode mode selection the mode field selects the mode of operat ion of the unified channel, as shown in table 276 . note: if a reserved value is written to mode the results are unpredictable. table 273. uc internalprescaler clock divider ucpre divide ratio 00 1 01 2 10 3 11 4 table 274. uc input filter bits if (1) 1. filter latency is 3 clock edges. minimum input pulse width [flt_clk periods] 0000 bypassed (2) 2. the input signal is synchronized bef ore arriving to the digital filter. 0001 02 0010 04 0100 08 1000 16 all others reserved table 275. uc bsl bits bsl selected bus 00 all channels: counter bus[a] 01 channels 0 to 7: counter bus[b] channels 8 to 15: counter bus[c] channels 16 to 23: counter bus[d] channels 24 to 27: counter bus[e] 10 reserved 11 all channels: internal counter table 272. emiosc[n] field descriptions (continued) field description timers RM0017 535/904 doc id 14629 rev 8 table 276. channel mode selection mode (1) 1. b = adjust parameters for the mode of operation. refer to section , uc modes of operation for details. mode of operation 0000000 general purpose in put/output mode (input) 0000001 general purpose input/output mode (output) 0000010 single action input capture 0000011 single action output compare 0000100 input pulse width measurement 0000101 input period measurement 0000110 double action output compare (with flag set on b match) 0000111 double action output compare (with flag set on both match) 0001000 ? 0001111 reserved 001000b modulus counter (up counter with clear on match start) 001001b modulus counter (up counter with clear on match end) 00101bb modulus counter (up/down counter) 0011000 ? 0100101 reserved 0100110 output pulse width modulation with trigger 0100111 ? 1001111 reserved 101000b modulus counter buffered (up counter) 101001b reserved 10101bb modulus counter buffered (up/down counter) 10110b0 output pulse width and frequency modulation buffered 10110b1 reserved 10111b0 center aligned output pulse width modulation buffered (with trail edge dead-time) 10111b1 center aligned output pulse width modul ation buffered (with lead edge dead-time) 11000b0 output pulse width modulation buffered 1100001 ? 1111111 reserved RM0017 timers doc id 14629 rev 8 536/904 emios uc status register (emioss[n]) figure 260. emios uc status register (emioss[n]) address: uc[n] base address + 0x10 0123456789101112131415 rovr000000000000000 ww1c reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ovfl 000000000000ucin ucout flag ww1c w1c reset0000000000000000 table 277. emioss[n] field descriptions field description ovr overrun bit the ovr bit indicates that flag generation occurred when the flag bit was already set. 1 = overrun has occurred 0 = overrun has not occurred ovfl overflow bit the ovfl bit indicates that an overflow has occurred in the internal counter. ovfl must be cleared by software writing a 1 to the ovflc bit. 1 = an overflow had occurred 0 = no overflow ucin unified channel input pin bit the ucin bit reflects the input pin state after being filtered and synchronized. ucout ucout ? unified channel output pin bit the ucout bit reflects the output pin state. flag flag bit the flag bit is set when an input capture or a match event in the comparators occurred. 1 = flag set event has occurred 0 = flag cleared note: when dma bit is set, the flag bit can be cleared by the ctu. timers RM0017 537/904 doc id 14629 rev 8 emios uc alternate a register (emiosalta[n]) the emiosalta[n] register provides an alternate address to access a2 channel registers in restricted modes (gpio, opwmt) only. if emiosa[n] register is used along with emiosalta[n], both a1 and a2 registers can be accessed in these modes. figure 271 summarizes the emiosalta[n] writing and reading accesses for all operation modes. please, see section , general purpose input/output (gpio) mode , section , output pulse width modulation with trigger (opwmt) mode for a more detailed description of the use of emiosalta[n] register. 24.4.4 functional description the five types of channels of the emios can operate in the modes as listed in figure 251 . the emios provides independently operating unified channels (uc) that can be configured and accessed by a host mcu. up to four time bases can be shared by the channels through four counter buses and each unified channel can generate its own time base. the emios block is reset at positive edge of the clock (synchronous reset). all registers are cleared on reset. figure 261. emios uc alternate a register (emiosalta[n]) address: uc[n] base address + 0x14 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r alta w reset0000000000000000 RM0017 timers doc id 14629 rev 8 538/904 unified channel (uc) each unified channel consists of: counter bus selector, which selects the time base to be used by the channel for all timing functions a programmable clock prescaler two double buffered data registers a and b that allow up to two input capture and/or output compare events to occur before software intervention is needed. two comparators (equal only) a and b, which compares the selected counter bus with the value in the data registers internal counter, which can be used as a local time base or to count input events programmable input filter, which ensures that only valid pin transitions are received by channel programmable input edge detector, which de tects the rising, falling or either edges an output flip-flop, which holds the logic level to be applied to the output pin emios status and control register uc modes of operation the mode of operation of the unified channel is determined by the mode select bits mode[0:6] in the emios uc control register (emiosc[n]) (see figure 259 for details). as the internal counter emioscnt[n] continues to run in all modes (except for gpio mode), it is possible to use this as a time bas e if the resource is not used in the current mode. in order to provide smooth waveform generation even if a and b registers are changed on the fly, it is available the mcb, opwfmb, opwmb and opwmcb modes. in these modes a and b registers are double buffered. general purpose input/output (gpio) mode in gpio mode, all input capture and output compare functions of the uc are disabled, the internal counter (emioscnt[n] register) is cleared and disabled. all control bits remain accessible. in order to prepare the uc for a new operation mode, writing to registers emiosa[n] or emiosb[n] stores the same value in registers a1/a2 or b1/b2, respectively. writing to register emiosalta[n] stores a value only in register a2. mode[6] bit selects between input (mode[6] = 0) and output (mode[6] = 1) modes. it is required that when changing mode[0:6], the application software goes to gpio mode first in order to reset the uc?s internal functions properly. failure to do this could lead to invalid and unexpected output compare or input capture results or the flags being set incorrectly. in gpio input mode (mode[0:6] = 0000000), the flag generation is determined according to edpol and edsel bits and the input pin status can be determined by reading the ucin bit. in gpio output mode (mode[0:6] = 0000001), the unified channel is used as a single output port pin and the value of the edpol bit is permanently transferred to the output flip- flop. timers RM0017 539/904 doc id 14629 rev 8 single action input capture (saic) mode in saic mode (mode[0:6] = 0000010), when a triggering event occurs on the input pin, the value on the selected time base is captured into register a2. the flag bit is set along with the capture event to indicate that an input capture has occurred. register emiosa[n] returns the value of register a2. as soon as the saic mode is entered coming out from gpio mode the channel is ready to capture events. the events are captured as soon as they occur thus reading register a always returns the value of the latest captured event. subsequent captures are enabled with no need of further reads from emiosa[n] register. the flag is set at any time a new event is captured. the input capture is triggered by a rising, falling or either edges in the input pin, as configured by edpol and edsel bits in emiosc[n] register. figure 262 and figure 263 show how the unified channel can be used for input capture. figure 262. single action input capture wi th rising edge triggering example figure 263. single action input capture with both edges triggering example single action output compare (saoc) mode in saoc mode (mode[0:6] = 0000011) a match value is loaded in register a2 and then immediately transferred to register a1 to be compared with the selected time base. when a match occurs, the edsel bit selects whether the output flip-flop is toggled or the value in edpol is transferred to it. along with the match the flag bit is set to indicate that the output compare match has occurred. writing to register emiosa[n] stores the value in register a2 and reading to register emiosa[n] returns the value of register a1. selected counter bus 0x000500 0x001000 0x001100 0x001250 0x001525 0x0016a0 flag pin/register a2 (captured) value 2 0xxxxxxx 0x001000 0x001250 0x0016a0 input signal 1 edge detect edge detect edge detect notes: 1. after input filter 2. emiosa[n] <= a2 edsel = 0 edpol = 1 selected counter bus 0x001000 0x001102 flag set event a2 (captured) value 2 0xxxxxxx 0x001000 input signal 1 edge detect notes: 1. afte r input filter 2. emiosa[n] <= a2 0x001103 0x001108 0x001104 0x001105 0x001106 0x001107 0x001001 flag pin/register edge detect flag clear edge detect 0x001103 0x001108 edsel = 1 edpol = x RM0017 timers doc id 14629 rev 8 540/904 an output compare match can be simulated in software by setting the forcma bit in emiosc[n] register. in this case, the flag bit is not set. when saoc mode is entered coming out from gpio mode the output flip-flop is set to the complement of the edpol bit in the emiosc[n] register. counter bus can be either internal or external and is selected through bits bsl[0:1]. figure 264 and figure 265 show how the unified channel can be used to perform a single output compare with edpol value being transferred to the output flip-flop and toggling the output flip-flop at each match, respectively. note that once in saoc mode the matches are enabled thus the desired match value on register a1 must be written before the mode is entered. a1 register can be updated at any time thus modi fying the match value which will reflect in the output signal generated by the channel. subsequent matches are enabled with no need of further writes to emiosa[n] register. the flag is set at the same time a match occurs (see figure 266 ). note: the channel internal counter in saoc mode is free-running. it starts counting as soon as the saoc mode is entered. figure 264. saoc example with edpol value being transferred to the output flip-flop figure 265. saoc example toggling the output flip-flop selected counter bus 0x000500 0x001000 0x001100 0x001000 0x001100 0x001000 output flip-flop update to a1 a1 value 1 0xxxxxxx 0x001000 flag pin/register 0x001000 0x001000 0x001000 a1 match a1 match a1 match notes: 1. emiosa[n] = a2 edsel = 0 edpol = 1 a2 = a1 according to ou[n] bit selected counter bus 0x000500 0x001000 0x001100 0x001000 0x001100 0x001000 a1 value 1 0xxxxxxx 0x001000 output flip-flop update to a1 flag pin/register a1 match a1 match a1 match 0x001000 0x001000 0x001000 notes: 1. emiosa[n] = a2 edsel = 1 edpol = x a2 = a1 according to ou[n] bit timers RM0017 541/904 doc id 14629 rev 8 figure 266. saoc example with flag behavior input pulse width measurement (ipwm) mode the ipwm mode (mode[0:6] = 0000100) allows the measurement of the width of a positive or negative pulse by capturing the leading edge on register b1 and the trailing edge on register a2. successive captures are done on consecutive edges of opposite polarity. the leading edge sensitivity (that is, pulse polarity ) is selected by edpol bit in the emiosc[n] register. registers emiosa[n] and emiosb[n] return the values in register a2 and b1, respectively. the capture function of register a2 remains disabled until the first leading edge triggers the first input capture on register b2. when this leading edge is detected, the count value of the selected time base is latched into register b2; the flag bit is not set. when the trailing edge is detected, the count value of the selected time base is latched into register a2 and, at the same time, the flag bit is set and the content of register b2 is transferred to register b1 and to register a1. if subsequent input capture events occur while the corresponding flag bit is set, registers a2, b1 and a1 will be updated with the latest captur ed values and the fl ag will remain set. registers emiosa[n] and emiosb[n] return the value in registers a2 and b1, respectively. in order to guarantee coherent access, reading emiosa[n] forces b1 be updated with the content of register a1. at the same time transfers between b2 and b1 are disabled until the next read of emiosb[n] register. reading emiosb[n] register forces b1 be updated with a1 register content and re-enables transfers from b2 to b1, to take effect at the next trailing edge capture. transfers from b2 to a1 are not blocked at any time. the input pulse width is calculated by subtracting the value in b1 from a2. figure 267 shows how the unified channel can be used for input pulse width measurement. selected counter bus 0x0 0x2 flag set event a2 value 1 0x1 output flip-flop note: 1. emiosa[n] <= a2 0x0 0x2 0x1 0x2 0x0 0x1 0x1 flag pin/register flag clear edsel = 1 system clock a1 match edpol = x RM0017 timers doc id 14629 rev 8 542/904 figure 267. input pulse width measurement example figure 268 shows the a1 and b1 updates when emiosa[n] and emiosb[n] register reads occur. note that a1 register has always coherent data related to a2 register. note also that when emiosa[n] read is performed b1 register is loaded with a1 register content. this guarantee that the data in register b1 has always the coherent data related to the last emiosa[n] read. the b1 register updates remains locked until emiosb[n] read occurs. if emiosa[n] read is performed b1 is updated with a1 register content even if b1 update is locked by a previous emiosa[n] read operation. figure 268. b1 and a1 updates at emiosa[n] and emiosb[n] reads reading emiosa[n] followed by emiosb[n] always provides coherent data. if not coherent data is required for any reason, the sequence of reads should be inverted, therefore emiosb[n] should be read prior to emiosa[n] register. note that even in this case b1 register updates will be blocked after emiosa[n] read, thus a second emiosb[n] is required in order to release b1 register updates. selected counter bus 0x000500 0x001000 0x001100 0x001250 0x001525 0x0016a0 a2(captured) value 2 b2(captured) value b1 value 3 0xxxxxxx 0x001000 0x001250 0x0016a0 0xxxxxxx 0x001100 0x001525 0xxxxxxx 0x001000 0x001250 input signal 1 babab 1. after input filter notes: flag pin/register 2. emiosa[n] = a2 3. emiosb[n] = b1 edpol = 1 a1 value 3 0xxxxxxx 0x001000 0x001250 selected counter bus 0x000500 0x001000 0x001100 0x001250 0x001525 0x0016a0 a2(captured) value 2 b2(captured) value b1 value 3 0xxxxxxx 0x001000 0x001250 0x0016a0 0xxxxxxx 0x001100 0x001525 0xxxxxxx 0x001000 input signal 1 babab 1. after input filter notes: flag pin/register 2. emiosa[n] = a2 edpol = 1 a1 value 3 0xxxxxxx 0x001000 0x001250 0x001000 0x001250 read emiosa[n] read emiosb[n] 3. emiosb[n] = b1 timers RM0017 543/904 doc id 14629 rev 8 input period measurement (ipm) mode the ipm mode (mode[0:6] = 0000101) allows the measurement of the period of an input signal by capturing two consecutive rising edges or two consecutive falling edges. successive input captures are done on consecutive edges of the same polarity. the edge polarity is defined by the edpol bit in the emiosc[n] register. when the first edge of selected polarity is detected, the selected time base is latched into the registers a2 and b2, and the data previously held in register b2 is transferred to register b1. on this first capture the flag line is not set, and the values in registers b1 is meaningless. on the second and subsequent captures, the flag line is set and data in register b2 is transferred to register b1. when the second edge of the same polarity is detected, the counter bus value is latched into registers a2 and b2, the data previously held in register b2 is transferred to data register b1 and to register a1. the flag bit is set to indicate the start and end points of a complete period have been captured. this sequence of events is repeated for each subsequent capture. registers emiosa[n] and emiosb[n] return the values in register a2 and b1, respectively. in order to allow coherent data, reading emiosa[n] forces a1 content be transferred to b1 register and disables transfers between b2 and b1. these transfers are disabled until the next read of the emiosb[n] register. reading emiosb[n] register forces a1 content to be transferred to b1 and re-enables transfers from b2 to b1, to take effect at the next edge capture. the input pulse period is calculated by subtracting the value in b1 from a2. figure 269 shows how the unified channel can be used for input period measurement. figure 269. input period measurement example figure 270 describes the a1 and b1 register updates when emiosa[n] and emiosb[n] read operations are performed. when emiosa[n] read occurs the content of a1 is transferred to b1 thus providing coherent data in a2 and b1 registers. transfers from b2 to b1 are then blocked until emiosb[n] is read. after emiosb[n] is read, register a1 content is transferred to register b1 and the transfers from b2 to b1 are re-enabled to occur at the transfer edges, which is the leading edge in the figure 270 example. selected counter bus 0x000500 0x001000 0x001100 0x001250 0x001525 0x0016a0 a2(captured) value 2 a1 value b2 (captured) value 0xxxxxxx 0x001000 0x001250 0xxxxxxx 0x001000 0x001250 0x0016a0 0xxxxxxx 0x001000 0x001250 0x0016a0 input signal 1 edpol = 1 flag pin register notes: 1. after input filter 2. emiosa[n] = a2 3. emiosb[n] = b1 a a a b1 value 3 0xxxxxxx 0x001000 0x001250 RM0017 timers doc id 14629 rev 8 544/904 figure 270. a1 and b1 updates at emiosa[n] and emiosb[n] reads double action output compare (daoc) mode in the daoc mode the leading and trailing edges of the vari able pulse width output are generated by matches occurring on comparators a and b. there is no restriction concerning the order in which a and b matches occur. when the daoc mode is entered, coming out from gpio mode both comparators are disabled and the output flip-flop is set to the complement of the edpol bit in the emiosc[n] register. data written to a2 and b2 are transferred to a1 and b1, respectively, on the next system clock cycle if bit ou[n] of the emiosoudis register is cleared (see figure 273 ). the transfer is blocked if bit ou[n] is set. comparator a is enabled only after the transfer to a1 register occurs and is disabled on the next a match. comparator b is enabled only after the transfer to b1 register occurs and is disabled on the next b match. comparators a and b are enabled and disabled independently. the output flip-flop is set to the value of edpol when a match occurs on comparator a and to the complement of edpol when a match occurs on comparator b. mode[6] controls if the flag is set on both matches (mode[0:6] = 0000111) or just on the b match (mode[0:6] = 0000110). flag bit assertion depends on comparator enabling. if subsequent enabled output compares occur on registers a1 and b1, pulses will continue to be generated, regardless of the state of the flag bit. at any time, the forcma and forcmb bits allow the software to force the output flip-flop to the level corresponding to a comparison event in comparator a or b, respectively. note that the flag bit is not affected by these forced operations. note: if both registers (a1 and b1) are loaded with the same value, the b match prevails concerning the output pin state (output flip-flop is set to the complement of edpol), the flag bit is set and both comparators are disabled. figure 271 and figure 272 show how the unified channel can be used to generate a single output pulse with flag bit being set on the second match or on both matches, respectively. selected counter bus 0x000500 0x001000 0x001100 0x001250 0x001525 0x0016a0 a2(captured) value 2 b2(captured) value b1 value 3 0xxxxxxx 0x001000 0x001250 0x0016a0 0xxxxxxx 0x001000 0xxxxxxx 0x001000 input signal 1 a aa flag pin/register edpol = 1 a1 value 0xxxxxxx 0x001000 0x001000 0x001250 0x001250 read emiosa[n] read emiosb[n] 0x001250 notes: 1. after input filter 2. emiosa[n] = a2 3. emiosb[n] = b1 0x0016a0 timers RM0017 545/904 doc id 14629 rev 8 figure 271. double action output compare with flag set on the second match figure 272. double action output co mpare with flag set on both matches selected counter bus 0x000500 0x001000 0x001100 0x001000 0x001100 a1 value 1 b1 value 2 0xxxxxxx 0x001100 0x001100 0x001100 0xxxxxxx 0x001000 0x001000 0x001000 output flip-flop a1 match b1 match update to a1 and b1 flag pin/register a1 match b1 match notes: 1. emiosa[n] = a1 (when reading) 2. emiosb[n] = b1 (when reading) a2 = a1according to ou[n] bit b2 = b1according to ou[n] bit mode[6] = 0 selected counter bus 0x000500 0x001000 0x001100 0x001000 0x001100 a1 value 1 b1 value 2 0xxxxxxx 0x001100 0x001100 0x001100 0xxxxxxx 0x001000 0x001000 0x001000 output flip-flop a1 match b1 match update to a1 and b1 flag pin/register a1 match b1 match notes: 1. emiosa[n] = a1 (when reading) 2. emiosb[n] = b1 (when reading) a2 = a1according to ou[n] bit b2 = b1according to ou[n] bit mode[6] = 1 RM0017 timers doc id 14629 rev 8 546/904 figure 273. daoc with transfer disabling example modulus counter (mc) mode the mc mode can be used to provide a time base for a counter bus or as a general purpose timer. bit mode[6] selects internal or external clock source when cleared or set, respectively. when external clock is selected, the input signal pin is used as the source and the triggering polarity edge is selected by the edpol and edsel in the emiosc[n] register. the internal counter counts up from the current value until it matches the value in register a1. register b1 is cleared and is not accessib le to the mcu. bit mode[4] selects up mode or up/down mode, when cleared or set, respectively. when in up count mode, a match between the internal counter and register a1 sets the flag and clears the internal counter. the timing of those events varies according to the mc mode setup as follows: internal counter clearing on match start (mode[0:6] = 001000b) ? external clock is selected if mode[6] is set. in this case the internal counter clears as soon as the match signal occurs. the channel flag is set at the same time the match occurs. note that by having the internal counter cleared as soon as the match occurs and incremented at the next input event a shorter zero count is generated. see figure 296 and figure 297 . ? internal clock source is selected if mode[6] is cleared. in this case the counter clears as soon as the match signal occurs. the channel flag is set at the same time the match occurs. at the next prescaler tick after the match the internal selected counter bus 0x0 0x2 flag set event a1 value 2 0xx output flip-flop 2. emiosa[n] = a1 (when reading) 0x0 0x2 0x1 0x2 0x0 0x1 0x1 flag pin/register flag clear edsel = 1 system clock enabled a1 match edpol = x b2 value 5 0x2 b1 value 4 0xx a2 value 3 0x1 ou 1 enabled b1 match 0x1 0xx 0xx 0x2 0x1 write to a2 0x2 0x2 0x1 0x2 0x1 0x1 0x2 write to b2 write to a2 write to b2 write to a2 write to b2 mode[0]=1 3. emiosa[n] = a2 (when writing) 4. emiosb[n] = b1 (when reading) 5. emiosb[n] = b2 (when writing) note: 1. ou[n] bit of emiosoudis register timers RM0017 547/904 doc id 14629 rev 8 counter remains at zero and only resumes counting on the following tick. see figure 296 and figure 298 . internal counter clearing on match end (mode[0:6] = 001001b) ? external clock is selected if mode[6] is set. in this case the internal counter clears when the match signal is asserted and the input event occurs. the channel flag is set at the same time the counter is cleared. see figure 296 and figure 299 . ? internal clock source is selected if mode[6] is cleared. in this case the internal counter clears when the match signal is asserted and the prescaler tick occurs. the channel flag is set at the same time the counter is cleared. see figure 296 and figure 299 . note: if the internal clock source is selected and the prescaler of the internal counter is set to ?1?, the mc mode behaves the same way even in clear on match start or clear on match end submodes. when in up/down count mode (mode[0:6] = 00101bb), a match between the internal counter and register a1 sets the flag and changes the counter direction from increment to decrement. a match between register b1 and the internal counter changes the counter direction from decrement to increment and sets the flag only if mode[5] bit is set. only values different than 0x0 must be written at a register. loading 0x0 leads to unpredictable results. updates on a register or counter in mc mode may cause loss of match in the current cycle if the transfer occurs near the match. in this case, the counter may rollover and resume operation in the next cycle. register b2 has no effect in mc mode. nevertheless, register b2 can be accessed for reads and writes by addressing emiosb. figure 274 and figure 275 show how the unified channel can be used as modulus counter in up mode and up/down mode, respectively. figure 274. modulus counter up mode example 0xffffff 0x000303 0x000000 emioscnt[n] time match a1 a1 value 1 0x000303 0x000303 0x000200 write to a2 match a1 write to a2 0x000200 match a1 match a1 0xxxxxxx flag pin/register notes: 1. emiosa[n] = a1 0x000303 0x000200 a2 = a1according to ou[n] bit mode[4] = 0 RM0017 timers doc id 14629 rev 8 548/904 figure 275. modulus counter up/down mode example modulus counter buffered (mcb) mode the mcb mode provides a time base which can be shared with other channels through the internal counter buses. register a1 is double buffered thus allowing smooth transitions between cycles when changing a2 register value on the fly. a1 register is updated at the cycle boundary, which is defined as when the internal counter transitions to 0x1. the internal counter values operates within a range from 0x1 up to register a1 value. if when entering mcb mode coming out from gpio mode the internal counter value is not within that range then the a match will not oc cur causing the channel internal counter to wrap at the maximum counter value which is 0xffff for a 16-bit counter. after the counter wrap occurs it returns to 0x1 and resume normal mcb mode operation. thus in order to avoid the counter wrap condition make sure its value is within the 0x1 to a1 register value range when the mcb mode is entered. bit mode[6] selects internal clock source if cleare d or external if set. when external clock is selected the input channel pin is used as the c hannel clock source. the active edge of this clock is defined by edpol and edsel bits in the emiosc[n] channel register. when entering in mcb mode, if up counter is selected by mode[4] = 0 (mode[0:6] = 101000b), the internal counter starts counting from its current value to up direction until a1 match occurs. the internal counter is set to 0x1 when its value matches a1 value and a clock tick occurs (either prescaled clock or input pin event). if up/down counter is selected by setting mode[4] = 1, the counter changes direction at a1 match and counts down until it reaches the value 0x1. after it has reached 0x1 it is set to count in up direction again. b1 register is used to generate a match in order to set the internal counter in up-count direction if up/down mode is selected. register b1 cannot be changed while this mode is selected. note that differently from the mc mode, the mcb mode counts between 0x1 and a1 register value. only values greater than 0x1 must be written at a1 register. loading values other than those leads to unpredictable results. th e counter cycle period is equal to a1 value in up counter mode. if in up/down counter mode the period is defined by the expression: (2*a1)-2. figure 276 describes the counter cycle for several a1 values. register a1 is loaded with a2 register value at the cycle boundary. thus any value written to a2 register within cycle n will be updated to a1 at the next cycle boundary and therefore will be used on cycle n+1 . the 0xffffff 0x000303 0x000000 emioscnt[n] time match a1 a1 value 1 0x000303 0x000303 0x000200 write to a2 match b1(=0) write to a2 0x000200 match a1 match b1(=0) 0xxxxxxx notes: 1. emiosa[n] = a1 0x000200 0x000200 flag pin/register a2 = a1according to ou[n] bit mode[6] = 1 timers RM0017 549/904 doc id 14629 rev 8 cycle boundary between cycle n and cycle n+1 is defined as when the internal counter transitions from a1 value in cycle n to 0x1 in cycle n+1 . note that the flag is generated at the cycle boundary and has a sync hronous operation, meaning that it is asserted one system clock cycle after the flag set event. figure 276. modulus counter buffered (mcb) up count mode figure 277 describes the mcb in up/down counter mode (mode[0:6] = 10101bb). a1 register is updated at the cycle boundary. if a2 is written in cycle n , this new value will be used in cycle n+1 for a1 match. flags are generated only at a1 match start if mode[5] is 0. if mode[5] is set to 1 flags are also generated at the cycle boundary. figure 277. modulus counter buffered (mcb) up/down mode figure 278 describes in more detail the a1 register update process in up counter mode. the a1 load signal is generated at the last system clock period of a counter cycle. thus, a1 is updated with a2 value at the same time that the counter (emioscnt[n]) is loaded with 0x1. emioscnt[n] time write to a2 match a1 match a1 match a1 write to a2 0x000001 0x000005 0x000006 0x000007 flag set event a1 value 0x000006 0x000005 0x000007 0x000007 0x000005 0x000007 a2 value flag pin/register prescaler ratio = 1 cycle n cycle n+1 cycle n+2 flag clear emioscnt[n] time write to a2 match a1 match a1 write to a2 0x000001 0x000005 0x000006 0x000007 flag set event a1 value 0x000006 0x000005 0x000007 0x000005 0x000007 a2 value flag pin/register prescaler ratio = 1 cycle n+1 cycle n+2 cycle n flag clear RM0017 timers doc id 14629 rev 8 550/904 the load signal pulse has the duration of one system clock period. if a2 is written within cycle n its value is available at a1 at the first clock of cycle n+1 and the new value is used for match at cycle n+1 . the update disable bits ou[n] of emiosoudis register can be used to control the update of this register, thus allowing to delay the a1 register update for synchronization purposes. figure 278. mcb mode a1 register update in up counter mode figure 279 describes the a1 register update in up/down counter mode. note that a2 can be written at any time within cycle n in order to be used in cycle n+1 . thus a1 receives this new value at the next cycle boundary. note that the update disable bits ou[n] of emiosoudis register can be used to disable the update of a1 register. figure 279. mcb mode a1 register update in up/down counter mode output pulse width and frequency modulation buffered (opwfmb) mode this mode (mode[0:6] = 10110b0) provides waveforms with variable duty cycle and frequency. the internal channel counter is auto matically selected as t he time base when this a1 value 0x000008 0x000008 0x000001 internal counter 0x000004 0x000006 a2 value 0x000008 0x000004 0x000006 0x000002 0x000004 0x000006 write to a2 write to a2 match a1 match a1 a1 load signal 8 4 6 match a1 counter = a1 time cycle n cycle n+1 cycle n+2 prescaler ratio = 2 a1 value 0x000006 a2 value 0x000006 0x000005 0x000006 0x000005 a1 load signal counter = 2 emioscnt[n] time write to a2 match a1 match a1 write to a2 0x000001 0x000005 0x000006 0x000006 cycle n cycle n+1 cycle n+2 prescaler ratio = 2 timers RM0017 551/904 doc id 14629 rev 8 mode is selected. a1 register indicates the duty cycle and b1 register the frequency. both a1 and b1 registers are double buffered to allow smooth signal generation when changing the registers values on the fly. 0% and 100% duty cycles are supported. at opwfmb mode entry the output flip-flop is set to the value of the edpol bit in the emiosc[n] register. if when entering opwfmb mode coming out from gpio mode the internal counter value is not within that range then the b match will not oc cur causing the channel internal counter to wrap at the maximum counter value which is 0xffff for a 16-bit counter. after the counter wrap occurs it returns to 0x1 and resume normal opwfmb mode operation. thus in order to avoid the counter wrap condition make sure its value is within the 0x1 to b1 register value range when the opwfmb mode is entered. when a match on comparator a occurs the output register is set to the value of edpol. when a match on comparator b occurs the output register is set to the complement of edpol. b1 match also causes the internal counter to transition to 0x1, thus restarting the counter cycle. only values greater than 0x1 are allowed to be written to b1 register. loading values other than those leads to unpredictable results. if you want to configure the module for opwfmb mode, ensure that the b1 register is modified before the mode is set. figure 280 describes the operation of the opwfmb mode regarding output pin transitions and a1/b1 registers match events. note that the output pin transition occurs when the a1 or b1 match signal is deasserted which is indica ted by the a1 match negedge detection signal. if register a1 is set to 0x4 the output pin transitions 4 counter periods after the cycle had started, plus one system clock cycle. note that in the example shown in figure 280 the internal counter prescaler has a ratio of two. figure 280. opwfmb a1 and b1 match to output register delay figure 281 describes the generated output signal if a1 is set to 0x0. since the counter does not reach zero in this mode, the channel internal logic infers a match as if a1 = 0x1 with the difference that in this case, the posedge of the match signal is used to trigger the output pin 8 1 4 match a1 negedge detection 5 a1 value 0x000004 a1 match a1 match negedge detection output pin edpol = 0 emioscnt time match b1 negedge detection b1 match b1 match negedge detection b1 value 0x000008 system clock prescaler prescaler ratio = 2 RM0017 timers doc id 14629 rev 8 552/904 transition instead of the negedge used when a1 = 0x1. note that a1 posedge match signal from cycle n+1 occurs at the same time as b1 negedge match signal from cycle n . this allows to use the a1 posedge match to mask the b1 negedge match when they occur at the same time. the result is that no transition occurs on the output flip-flop and a 0% duty cycle is generated. figure 281. opwfmb mode with a1 = 0 (0% duty cycle) figure 282 describes the timing for the a1 and b1 registers load. the a1 and b1 load use the same signal which is generated at the last system clock period of a counter cycle. thus, a1 and b1 are updated respectively with a2 and b2 values at the same time that the counter (emioscnt[n]) is loaded with 0x1. this event is defined as the cycle boundary. the load signal pulse has the duration of one system clock period. if a2 and b2 are written within cycle n their values are available at a1 and b1, respectively, at the first clock of cycle n+1 and the new values are used for matches at cycle n+1 . the update disable bits ou[n] of emiosoudis register can be used to control the update of these registers, thus allowing to delay the a1 and b1 registers update for synchronization purposes. in figure 282 it is assumed that both the channel and global prescalers are set to 0x1 (each divide ratio is two), meaning that the channel internal counter transitions at every four system clock cycles. flags can be generated only on b1 matches when mode[5] is cleared, or on both a1 and b1 matches when mode[5] is set. since b1 flag occurs at the cycle boundary, this flag can be used to indicate that a2 or b2 data written on cycle n were loaded to a1 or b1, respectively, thus generating matches in cycle n+1 . note that the flag has a synchronous operation, meaning that it is asserted one system clock cycle after the flag set event. 1 4 match a1 negedge detection 5 a1 value 0x000004 a1 match a1 match negedge detection output pin edpol = 0 emioscnt time match b1 negedge detection b1 match b1 match negedge detection b1 value 0x000008 system clock prescaler a2 value 0x000000 write to a2 0x000000 a1 match posedge detection match a1 posedge detection no transition at this point 1 cycle n cycle n+1 prescaler ratio = 2 timers RM0017 553/904 doc id 14629 rev 8 figure 282. opwfmb a1 and b1 registers update and flags the forcma and forcmb bits allow the software to force the output flip-flop to the level corresponding to a match on comparators a or b respectively. similarly to a b1 match forcmb sets the internal counter to 0x1. the flag bit is not set by the forcma or forcmb bits being asserted. figure 283 describes the generation of 100% and 0% duty cycle signals. it is assumed edpol = 0 and the resultant prescaler value is 1. initially a1 = 0x8 and b1 = 0x8. in this case, b1 match has precedence over a1 match, thus the output flip-flop is set to the complement of edpol bit. this cycle corresponds to a 100% duty cycle signal. the same output signal can be generated for any a1 value greater or equal to b1. figure 283. opwfmb mode from 100% to 0% duty cycle a 0% duty cycle signal is generated if a1 = 0x0 as shown in figure 283 cycle 9. in this case b1 = 0x8 match from cycle 8 occurs at the same time as the a1 = 0x0 match from cycle 9. edpol = 0 cycle n cycle n+1 cycle n+2 a1 value 1 b1 value b2 value 0x8 0x2 0x6 0x8 0x1 internal counter 0x4 0x6 a2 value 1 0x2 0x4 0x6 0x2 0x4 0x6 0x8 0x6 output pin write to b2 write to a2 write to a2 match a1 match a1 match b1 match b1 match b1 a1/b1 load signal due to b1 match cycle n-1 flag set event flag pin/register prescaler ratio = 4 flag clear mode[6] = 1 0x000008 0x000007 0x000006 0x000005 0x000004 0x000003 0x000002 0x000001 0x000000 0% 100% emioscnt edpol = 0 a1 value b1 value output pin 0x000008 prescaler ratio = 1 cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 0x000007 0x000006 0x000005 0x000004 0x000003 0x000002 0x000001 0x000000 a2 value 0x000008 0x000001 RM0017 timers doc id 14629 rev 8 554/904 please, refer to figure 281 for a description of the a1 and b1 match generation. in this case a1 match has precedence over b1 match and the output signal transitions to edpol. center aligned output pwm buffered with dead-time (opwmcb) mode this operation mode generates a center aligned pwm with dead time insertion to the leading (mode[0:6] = 10111b1) or trailin g edge (mode[0:6] = 10 111b0). a1 and b1 registers are double buffered to allow smooth output signal generation when changing a2 or b2 registers values on the fly. bits bsl[0:1] select the time base. the time base selected for a channel configured to opwmcb mode should be a channel configured to mcb up/down mode, as shown in figure 277 . it is recommended to start the mcb channel time base after the opwmcb mode is entered in order to avoid miss ing a matches at the very first duty cycle. register a1 contains the ideal duty cycle for the pwm signal and is compared with the selected time base. register b1 contains the dead time value and is compared against the internal counter. for a leading edge dead time insertion, the output pwm duty cycle is equal to the difference between register a1 a nd register b1, an d for a trailing edge dead ti me insertion, the output pwm duty cycle is equal to the sum of register a1 and register b1. bit mode[6] selects between trailing and l eading dead time insertion, respectively. note: the internal counter runs in the internal pr escaler ratio, while the selected time base may be running in a different prescaler ratio. when opwmcb mode is entered, coming out from gpio mode, the output flip-flop is set to the complement of the edpol bit in the emiosc[n] register. the following basic steps summarize proper opwmcb startup, assuming the channels are initially in gpio mode: 1. [global] disable global prescaler; 2. [mcb channel] disable channel prescaler; 3. [mcb channel] write 0x1 at internal counter; 4. [mcb channel] set a register; 5. [mcb channel] set channel to mcb up mode; 6. [mcb channel] set prescaler ratio; 7. [mcb channel] enable channel prescaler; 8. [opwmcb channel] disable channel prescaler; 9. [opwmcb channel] set a register; 10. [opwmcb channel] set b register; 11. [opwmcb channel] select time base input through bsl[1:0] bits; 12. [opwmcb channel] enter opwmcb mode; 13. [opwmcb channel] set prescaler ratio; 14. [opwmcb channel] enable channel prescaler; 15. [global] enable global prescaler. figure 284 describes the load of a1 and b1 registers which occurs when the selected counter bus transitions from 0x2 to 0x1. this event defines the cycle boundary. note that values written to a2 or b2 within cycle n are loaded into a1 or b1 registers, respectively, and used to generate matches in cycle n+1 . timers RM0017 555/904 doc id 14629 rev 8 figure 284. opwmcb a1 and b1 registers load bit ou[n] of the emiosoudis register can be used to disable the a1 and b1 updates, thus allowing to synchronize the load on these registers with the load of a1 or b1 registers in others channels. note that using the update disable bit a1 and b1 registers can be updated at the same counter cycle thus allowing to change both registers at the same time. in this mode a1 matches always sets the internal counter to 0x1. when operating with leading edge dead time insertion the first a1 match sets the internal counter to 0x1. when a match occurs between register b1 and the internal time base, the output flip-flop is set to the value of the edpol bit. in the following match between register a1 and the selected time base, the output flip-flop is set to the complement of the edpol bit. this sequence repeats continuously. the internal counter should not reach 0x0 as consequence of a rollover. in order to avoid it the user should not write to the emiosb register a value greater than twice the difference between external count up limit and emiosa value. figure 285 shows two cycles of a center aligned pwm signal. note that both a1 and b1 register values are changing wit hin the same cycle which allows to vary at the same time the duty cycle and dead time values. a1 value 0x000020 a2 value 0x000020 0x000015 0x000016 0x000015 a1/b1 load signal selected counter == 2 selected time write to a2 write to b2 write to b2 write to a2 0x000001 0x000005 0x000006 0x000016 cycle n cycle n+1 cycle n+2 counter bus b1 value 0x000004 b2 value 0x000004 0x000005 0x000006 0x000005 0x000006 prescaler ratio = 2 system clock RM0017 timers doc id 14629 rev 8 556/904 figure 285. opwmcb with lead dead time insertion when operating with trailing edge dead time insertion, the first match between a1 and the selected time base sets the output flip-flop to the value of the edpol bit and sets the internal counter to 0x1. in the second match between register a1 and the selected time base, the internal counter is set to 0x1 and b1 matches are enabled. when the match between register b1 and the selected time base occurs the output flip-flop is set to the complement of the edpol bit. this sequence repeats continuously. edpol = 1 internal time base internal counter is set to 1 on a1 match dead-time a1 value a2 value b1 value b2 value write to b2 selected counter bus 0x000002 0x000004 0x000002 0x000004 0x000015 0x000015 write to a2 0x000013 0x000013 0x000001 0x000002 0x000004 0x000015 0x000013 0x000020 dead-time output flip-flop flag pin/register 0x000001 timers RM0017 557/904 doc id 14629 rev 8 figure 286. opwmcb with trail dead time insertion flag can be generated in th e trailing edge of th e output pwm signa l when mode[5] is cleared, or in both edges, when mode[5] is set. if subsequent matches occur on comparators a and b, the pwm pulses continue to be generated, regardless of the state of the flag bit. note: in opwmcb mode, forcma and forcmb do not have the same behavior as a regular match. instead, they force the output flip-flop to constant value which depends upon the selected dead time insertion mode, lead or trail, and the value of the edpol bit. forcma has different behaviors depending upon the selected dead time insertion mode, lead or trail. in lead dead time insertion forcma force a transition in the output flip-flop to the opposite of edpol. in trail dead time insertion the output flip-flop is forced to the value of edpol bit. if bit forcmb is set, the output flip-flop value depends upon the selected dead time insertion mode. in lead dead time insertion forcmb forces the output flip-flop to transition to edpol bit value. in trail dead time insertion the output flip-flop is forced to the opposite of edpol bit value. note: forcma bit set does not set the internal time-base to 0x1 as a regular a1 match. the flag bit is not set either in case of a forcma or forcmb or even if both forces are issued at the same time. note: forcma and forcmb have the same behavior even in freeze or normal mode regarding the output pin transition. when forcma is issued along with forcmb the output flip-flop is set to the opposite of edpol bit value. this is equivalent of saying that.forcma has precedence over forcmb edpol = 1 internal time base internal counter is set to 1 on a1 match dead-time a1 value a2 value b1 value b2 value write to b2 selected counter bus 0x000002 0x000004 0x000002 0x000004 0x000015 0x000015 write to a2 0x000013 0x000013 0x000001 0x000002 0x000004 0x000015 0x000013 0x000020 dead-time output flip-flop flag pin/register 0x000001 RM0017 timers doc id 14629 rev 8 558/904 when lead dead time insertion is selected and forcmb has precedence over forcma when trail dead time in sertion is selected. duty cycle from 0% to 100% can be generated by setting appropriate values to a1 and b1 registers relatively to the period of the external time base. setting a1 = 1 generates a 100% duty cycle waveform. assuming edpol is set to ?1? and opwmcb mode with trail dead time insertion, 100% duty cycle signals can be generated if b1 occurs at or after the cycle boundary (external counter = 1). if a1 is greater than the maximum value of the selected counter bus period, then a 0% duty cycle is produced, only if the pin starts the current cycle in the opposite of edpol value. in case of 100% duty cycle, the transition from edpol to the opposite of edpol may be obtained by forcing pin, using forcma or forcmb, or both. note: if a1 is set to 0x1 at opwmcb entry the 100% duty cycle may not be obtained in the very first pwm cycle due to the pin condition at mode entry. only values different than 0x0 are allowed to be written to a1 register. if 0x0 is loaded to a1 the results are unpredictable. note: a special case occurs when a1 is set to (external counter bus period)/2, which is the maximum value of the external counter. in this case the output flip-flop is constantly set to the edpol bit value. the internal channel logic prevents matches from one cycle to propagate to the next cycle. in trail dead time insertion b1 match from cycle n could eventually cross the cycle boundary and occur in cycle n+1 . in this case b1 match is masked out and does not cause the output flip-flop to transition. therefore matches in cycle n+1 are not affected by the late b1 matches from cycle n . figure 287 shows a 100% duty cycle output signal generated by setting a1 = 4 and b1 = 3. in this case the trailing edge is positioned at the boundary of cycle n+1 , which is actually considered to belong to cycle n+2 and therefore does not cause the output flip-flip to transition. timers RM0017 559/904 doc id 14629 rev 8 figure 287. opwmcb with 100% duty cycle (a1 = 4 and b1 = 3) it is important to notice that, such as in opwmb and opwfmb modes, the match signal used to set or clear the channel output flip-flop is generated on the deassertion of the channel combinational comparator output signal which compares the selected time base with a1 or b1 register values. please refer to figure 280 which describes the delay from matches to output flip-flop transition in opwfmb mode. the operation of opwmcb mode is similar to opwfmb regarding matches and output pin transition. output pulse width modulation buffered (opwmb) mode opwmb mode (mode[0:6] = 11000b0) is used to generate pulses with programmable leading and trailing edge placement. an extern al counter driven in mcb up mode must be selected from one of the counter buses. a1 register value defines the first edge and b1 the second edge. the output signal polarity is de fined by the edpol bit. if edpol is zero, a negative edge occurs when a1 matches the selected counter bus and a positive edge occurs when b1 matches the selected counter bus. the a1 and b1 registers are double buffered and updated from a2 and b2, respectively, at the cycle boundary. the load operation is sim ilar to the opwfmb mode. please refer to figure 282 for more information about a1 and b1 registers update. flag can be generated at b1 matches, when mode[5] is cleared, or in both a1 and b1 matches, when mode[5] is set. if subsequent matches occur on comparators a and b, the pwm pulses continue to be generated, regardless of the state of the flag bit. forcma and forcmb bits allow the software to force the output flip-flop to the level corresponding to a match on a1 or b1 respectively. flag bit is not set by the forcma and forcmb operations. at opwmb mode entry the output flip-flop is set to the value of the edpol bit in the emiosc[n] register. 0x000001 dead time 0x000020 dead time dead time write to a2 selected counter bus internal time base 0x000004 a1 value a2 value b1 value b2 value 0x000004 0x000001 output flip-flop 0x000003 0x000015 0x000003 0x000015 0x000003 cycle n cycle n+1 cycle n+2 RM0017 timers doc id 14629 rev 8 560/904 some rules applicable to the opwmb mode are: b1 matches have precedence over a1 matches if they occur at the same time within the same counter cycle a1 = 0 match from cycle n has precedence over b1 match from cycle n-1 a1 matches are masked out if they occur after b1 match within the same cycle any value written to a2 or b2 on cycle n is loaded to a1 and b1 registers at the following cycle boundary (assuming ou[n] bit of emiosoudis register is not asserted). thus the new values will be used for a1 and b1 matches in cycle n+1 figure 288 describes the operation of the opwmb mode regarding a1 and b1 matches and the transition of the channel output pin. in this example edpol is set to ?0?. figure 288. opwmb mode matches and flags note that the output pin transitions are based on the negedges of the a1 and b1 match signals. figure 288 shows in cycle n+1 the value of a1 register bein g set to ?0?. in this case the match posedge is used instead of the negedge to transition the output flip-flop. figure 289 describes the channel operation for 0% duty cycle. note that the a1 match posedge signal occurs at the same time as the b1 = 0x8 negedge signal. in this case a1 match has precedence over b1 match, causing the output pin to remain at edpol bit value, thus generating a 0% duty cycle signal. 1 4 match a1 negedge detection 6 a1 value 0x000004 a1 match a1 match negedge detection output pin edpol = 0 time match b1 negedge detection b1 match b1 match negedge detection b1 value 0x000006 clock prescaler a2 value 0x000000 write to a2 0x000000 a1 match posedge detection match a1 posedge detection 1 cycle n cycle n+1 8 6 flag set event selected counter bus flag pin/register timers RM0017 561/904 doc id 14629 rev 8 figure 289. opwmb mode with 0% duty cycle figure 290 shows a waveform changing from 100% to 0% duty cycle. edpol in this case is zero. in this example b1 is programmed to the same value as the period of the external selected time base. figure 290. opwmb mode from 100% to 0% duty cycle in figure 290 if b1 is set to a value lower than 0x8 it is not possible to achieve 0% duty cycle by only changing a1 register value. since b1 matches have precedence over a1 matches the output pin transitions to the opposite of edpol bit at b1 match. note also that if b1 is set to 0x9, for instance, b1 match does not occur, thus a 0% duty cycle signal is generated. 1 4 match a1 negedge detection 8 a1 value 0x000004 a1 match a1 match negedge detection output pin edpol = 0 selected time match b1 negedge detection b1 match b1 match negedge detection b1 value 0x000008 clock prescaler a2 value 0x000000 write to a2 0x000000 a1 match posedge detection match a1 posedge detection 1 cycle n cycle n+1 8 counter bus flag set event flag pin/register 0x000008 0x000007 0x000006 0x000005 0x000004 0x000003 0x000002 0x000001 0x000000 0% 100% selected edpol = 0 a1 value b1 value output pin 0x000008 prescaler = 1 cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 counter bus 0x000007 0x000006 0x000005 0x000004 0x000003 0x000002 0x000001 0x000000 a2 value RM0017 timers doc id 14629 rev 8 562/904 output pulse width modulation with trigger (opwmt) mode opwmt mode (mode[0:6] = 0100110) is intended to support the generation of pulse width modulation signals where the period is not modified while the signal is being output, but where the duty cycle will be varied and must not create glitches. the mo de is intended to be used in conjunction with other channels executing in the same mode and sharing a common timebase. it will support each channel with a fi xed pwm leading edge position with respect to the other channels and the ability to generate a trigger signa l at any point in the period that can be output from the module to initiate activity in other parts of the device such as starting adc conversions. an external counter driven in either mc up or mcb up mode must be selected from one of the counter buses. register a1 defines the leading edge of the pwm output pulse and as such the beginning of the pwm?s period. this makes it possible to insure that th e leading edge of multiple channels in opwmt mode can occur at a specific time with respect to the other channels when using a shared timebase. this can allow the introduction of a fixed offset for each channel which can be particularly useful in the generation of lighting pwm control signals where it is desirable that edges are not coincident with each other to help eliminate noise generation. the value of register a1 represents the shift of the pwm channel with respect to the selected timebase. a1 can be configured with any value within the range of the selected time base. note that register s loaded with 0x0 will not produce matches if the timebase is driven by a channel in mcb mode. a1 is not buffered as the shift of a pwm channel must not be modified while the pwm signal is being generated. in case a1 is modified it is immediately updated and one pwm pulse could be lost. emiosb[n] address gives access to b2 register for write and b1 register for read. register b1 defines the trailing ed ge of the pwm output pulse and as such the duty cycle of the pwm signal. to synchronize b1 update with the pwm signal and so ensure a correct output pulse generation the transfer from b2 to b1 is done at every match of register a1. emiosoudis register affects transfers between b2 and b1 only. in order to account for the shift in the leading edge of the waveform defined by register a1 it will be necessary that the trailing edge, held in register b1, can ro ll over into the next period. this means that a match against the b1 register should not have to be qualified by a match in the a1 register. the impact of this would mean that incorrectly setting register b1 to a value less that register a1 will result in the output being held over a cycle boundary until the b1 value is encountered. this mode provides a buffered update of t he trailing edge by updati ng register b1 with register b2 contents only at a match of register a1. the value loaded in register a1 is compared with the value on the selected time base. when a match on comparator a1 occurs, the output flip-flop is set to the value of the edpol bit. when a match occurs on comparator b, the output flip-flop is set to the complement of the edpol bit. note that the output pin and flag transitions are based on the posedges of the a1, b1 and a2 match signals. please, refer to figure 288 at section , output pulse width modulation buffered (opwmb) mode for details on match posedge. register a2 defines the generation of a trigger event within the pwm period and a2 should be configured with any value within the range of the selected time base, otherwise no trigger timers RM0017 563/904 doc id 14629 rev 8 will be generated. a match on th e comparator will gener ate the flag signal but it has no effect on the pwm output signal generation. the typical setup to obtain a trigger with flag is to enable dma and to drive the channel?s ipd_done input high. a2 is not buffered and therefore its update is immediate. if the channel is running when a change is made this could cause either the loss of one trigger event or the generation of two trigger events within the same period. register a2 can be accessed by reading or writing the emios uc alternate a register (emiosalta) at uc[n] base address +0x14. flag signal is set only at match on the comparator with a2. a match on the comparator with a1 or b1 or b2 has no effect on flag. at any time, the forcma and forcmb bits allow the software to force the output flip-flop to the level corresponding to a match on a or b respectively. any forcma and/or forcmb has priority over any simultaneous match regarding to output pin transitions. note that the load of b2 content on b1 register at an a match is not inhibited due to a simultaneous forcma/forcmb assertion. if both forcma and forcmb are asserted simultaneously the output pin goes to the opposite of edpol value such as if a1 and b1 registers had the same value. forcma assertion causes the transfer from register b2 to b1 such as a regular a match, regardle ss of forcmb assertion. if subsequent matches occur on comparators a1 and b, the pwm pulses continue to be generated, regardless of the state of the flag bit. at opwmt mode entry the output flip-flop is set to the complement of the edpol bit in the emiosc[n] register. in order to achieve 0% duty cycle both registers a1 and b must be set to the same value. when a simultaneous match on comparators a and b occur, the output flip-flop is set at every period to the complement value of edpol. in order to achieve 100% duty cycle the register b1 must be set to a value greater than maximum value of the selected time base. as a consequence, if 100% duty cycle must be implemented, the maximum counter value for the time base is 0xfffe for a 16-bit counter. when a match on comparator a1 occurs the output flip-flop is set at every period to the value of edpol bit. the transfer from register b2 to b1 is still triggered by the match at comparator a. figure 291 shows the unified channel running in opwmt mode with trigger event generation and duty cycle update on next period update. RM0017 timers doc id 14629 rev 8 564/904 figure 291. opwmt example figure 292 shows the unified channel running in opwmt mode with trigger event generation and 0% duty. figure 292. opwmt with 0% duty cycle figure 293 shows the unified channel running in opwmt mode with trigger event generation and 100% duty cycle. 0x0011ff 0x001000 0x000000 selected counter bus time output flip-flop a1 value 1 write to b2 0x000400 b1 value b2 value 2 0x000700 match b1 write to a1 0xxxxxxx 0x000400 0x001000 0x000700 and b2 0x001000 match a1 match b1 match a1 notes: 1. emiosa[n] = a1 2. emiosb[n] = b2 for write, b1 for read 0x000700 notes: a2 value 0x000500 0x000500 flag pin/register match a2 match a2 0x0011ff 0x001000 0x000000 selected counter bus time output flip-flop a1 value 1 write to b2 0x000400 b1 value b2 value 2 0x000400 match b1 write to a1 0xxxxxxx 0x000400 0x001000 and b2 0x001000 match a1 match b1 match a1 notes: 1. emiosa[n] = a1 2. emiosb[n] = b2 for write, b1 for read 0x000400 notes: a2 value 0x000500 0x000500 flag pin/register match a2 match a2 timers RM0017 565/904 doc id 14629 rev 8 figure 293. opwmt with 100% duty cycle input programmable filter (ipf) the ipf ensures that only valid input pin transitions are received by the unified channel edge detector. a block diagram of the ipf is shown in figure 294 . the ipf is a 5-bit programmable up counter that is incremented by the selected clock source, according to bits if[0:3] in emiosc[n] register. figure 294. lnput programmable filter submodule diagram the input signal is synchronized by system clock. when a state change occurs in this signal, the 5-bit counter starts counting up. as long as the new state is stable on the pin, the counter remains incrementing. if a counter overflows occurs, the new pin value is validated. in this case, it is transmitted as a pulse edge to the edge detector. if the opposite edge appears on the pin before validation (overflow), the counter is reset. at the next pin transition, the counter starts counting again. any pulse that is shorter than a full range of the masked counter is regarded as a glitch and it is not passed on to the edge detector. a timing diagram of the input filter is shown in figure 295 . 0x0011ff 0x001000 0x000000 selected counter bus time output flip-flop a1 value 1 write to b2 0x000400 b1 value b2 value 2 0x001200 match b1 does not occur write to a1 0xxxxxxx 0x000400 0x001000 and b2 0x001000 match a1 match b1 match a1 notes: 1. emiosa[n] = a1 2. emiosb[n] = b2 for write, b1 for read 0x001200 notes: a2 value 0x000500 0x000500 flag pin/register match a2 match a2 if3 filter out ipg_clk prescaled clock if2 if1 if0 clk fck emiosi 5-bit up counter synchronizer clock RM0017 timers doc id 14629 rev 8 566/904 figure 295. input programmable filter example the filter is not disabled during either freeze state or negated gtbe input. clock prescaler (cp) the cp divides the gcp output signal to generate a clock enable for the internal counter of the unified channels. the gcp output signal is prescaled by the value defined in figure 273 according to the ucpre[0:1] bits in emiosc[n] register. the prescaler is enabled by setting the ucpren bit in the emiosc[n] and can be stopped at any time by clearing this bit, thereby stopping the internal counter in the unified channel. in order to ensure safe working and avoid glitches the following steps must be performed whenever any update in the prescaling rate is desired: 1. write 0 at both gpren bit in emiosmcr register and ucpren bit in emiosc[n] register, thus disabling prescalers; 2. write the desired value for prescaling rate at ucpre[0:1] bits in emiosc[n] register; 3. enable channel prescaler by writing 1 at ucpren bit in emiosc[n] register; 4. enable global prescaler by writing 1 at gpren bit in emiosmcr register. the prescaler is not disabled during either freeze state or negated gtbe input. effect of freeze on the unified channel when in debug mode, bit frz in the emiosmcr and bit fren in the emiosc[n] register are both set, the internal counter and unified channel capture and compare functions are halted. the uc is frozen in its current state. during freeze, all registers are accessible. when the unified channel is operating in an output mode, the force match functions remain available, allowing the software to force the output to the desired level. note that for input modes, any input events that may occur while the channel is frozen are ignored. when exiting debug mode or freeze enable bit is cleared (frz in the emiosmcr or fren in the emiosc[n] register) the channel actions resume, but may be inconsistent until channel enters gpio mode again. time selected clock emiosi 5-bit counter filter out if[0:3] = 0010 timers RM0017 567/904 doc id 14629 rev 8 ip bus interface unit (biu) the biu provides the interface between the internal interface bus (iib) and the peripheral bus, allowing communication among all submodules and this ip interface. the biu allows 8, 16 and 32-bit access. they are performed over a 32-bit data bus in a single cycle clock. effect of freeze on the biu when the frz bit in the emiosmcr is set and the module is in debug mode, the operation of biu is not affected. global clock prescaler submodule (gcp) the gcp divides the system clock to generate a clock for the cps of the channels. the main clock signal is prescaled by the value defined in figure 267 according to bits gpre[0:7] in the emiosmcr. the global prescaler is enabled by setting the gpren bit in the emiosmcr and can be stopped at any time by clearing this bit, thereby stopping the internal counters in all the channels. in order to ensure safe working and avoid glitches the following steps must be performed whenever any update in the prescaling rate is desired: 1. write ?0? at gpren bit in emiosm cr, thus disabling global prescaler; 2. write the desired value for prescaling rate at gpre[0:7] bits in emiosmcr; 3. enable global prescaler by writ ing ?1? at gpren bit in emiosmcr. the prescaler is not disabled during either freeze state or negated gtbe input. effect of freeze on the gcp when the frz bit in the emiosmcr is set and the module is in debug mode, the operation of gcp submodule is not affected, that is, there is no freeze function in this submodule. 24.4.5 initialization/a pplication information on resetting the emios the unified channels enter gpio input mode. considerations before changing an operating mode, the uc must be programmed to gpio mode and emiosa[n] and emiosb[n] registers must be updated with the correct values for the next operating mode. then the emiosc[n] register can be written with the new operating mode. if a uc is changed from one mode to another without performing this procedure, the first operation cycle of the selected time base can be random, that is, matches can occur in random time if the contents of emiosa[n] or emiosb[n] were not updated with the correct value before the time base matches the previous contents of emiosa[n] or emiosb[n]. when interrupts are enabled, the software must clear the flag bits before exiting the interrupt service routine. application information correlated output signals can be generated by all output operation modes. bits ou[n] of the emiosoudis register can be used to control the update of these output signals. RM0017 timers doc id 14629 rev 8 568/904 in order to guarantee that the internal counters of correlated channels are incremented in the same clock cycle, the internal prescalers must be set up before enabling the global prescaler. if the internal prescalers are set after enabling the global prescaler, the internal counters may increment in the same ratio, but at a different clock cycle. time base generation for mc with internal clock source operation modes, the internal counter rate can be modified by configuring the clock prescaler ratio. figure 296 shows an example of a time base with prescaler ratio equal to one. note: mcb and opwfmb modes have a different behavior. figure 296. time base period when running in the fastest prescaler ratio if the prescaler ratio is greater than one or external clock is selected, the counter may behave in three different ways depending on the channel mode: if mc mode and clear on match start and external clock source are selected the internal counter behaves as described in figure 297. if mc mode and clear on match start and internal clock source are selected the internal counter behaves as described in figure 298. if mc mode and clear on match end are selected the internal counter behaves as described in figure 299. note: mcb and opwfmb modes have a different behavior. system clock input event/prescaler clock enable = 1 internal counter match value = 3 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 pre scaled clock ratio = 1 (bypassed) see note 1 flag set event note 1: when a match occurs, the first clock cycle is used to clear the internal counter, starting another period. flag pin/register flag clear timers RM0017 569/904 doc id 14629 rev 8 figure 297. time base generation with external clock and clear on match start figure 298. time base generation with in ternal clock and clear on match start system clock input event internal counter match value = 3 1 2 3 0 see note 1 note 1: when a match occurs, the first system clock cycle is used to clear the internal counter, and at the next edge of prescaler clock enable 1 2 the counter will start counting. 1 2 3 0 flag set event flag clear flag pin/register system clock prescaler clock enable internal counter match value = 3 0 1 3 0 2 0 3 0 prescaled clock ratio = 3 see note 1 note 1: when a match occurs, the first clock cycle is used to clear the internal counter, and only after a second edge of pre scaled clock 1 2 the counter will start counting. flag set event flag clear flag pin/register RM0017 timers doc id 14629 rev 8 570/904 figure 299. time base generation with clear on match end coherent accesses it is highly recommended that the software waits for a new flag set event before start reading emiosa[n] and emiosb[n] registers to get a new measurement. the flag indicates that new data has been captured and it is the only way to assure data coherency. the flag set event can be detected by polling the flag bit or by enabling the interrupt request or ctu trigger generation. reading the emiosa[n] register again in the same period of the last read of emiosb[n] register may lead to incoherent results. this will occur if the la st read of emio sb[n] register occurred after a disabled b2 to b1 transfer. channel/modes initialization the following basic steps summarize basic output mode startup, assuming the channels are initially in gpio mode: 1. [global] disable global prescaler. 2. [timebase channel] disable channel prescaler. 3. [timebase channel] write initial value at internal counter. 4. [timebase channel] set a/b register. 5. [timebase channel] set channel to mc(b) up mode. 6. [timebase channel] set prescaler ratio. 7. [timebase channel] enable channel prescaler. 8. [output channel] disable channel prescaler. 9. [output channel] set a/b register. 10. [output channel] select timebase input through bits bsl[1:0]. 11. [output channel] enter output mode. 12. [output channel] set prescaler ratio (same ratio as timebase channel). 13. [output channel] enable channel prescaler. 14. [global] enable global prescaler. 15. [global] enable global time base. system clock input event/prescaler clock enable internal counter match value = 3 0 1 3 2 0 prescaled clock ratio = 3 see note 1 note 1: the match occurs only when the input event/prescaler clock enable is active. then, the internal counter is immediately cleared. 1 2 3 flag set event flag clear flag pin/register timers RM0017 571/904 doc id 14629 rev 8 the timebase channel and the output channel may be the same for some applications such as in opwfm(b) mode or whenever the output channel is intended to run the timebase itself. the flags can be configured at any time. 24.5 periodic interrupt timer (pit) 24.5.1 introduction the pit is an array of timers that can be used to raise interrupts. figure 300 shows the pit block diagram. figure 300. pit block diagram 24.5.2 features the main features of this block are: timers can generate interrupts all interrupts are maskable independent timeout periods for each timer timer 5 timer 0 . . . pit registers peripheral interrupts pit . . . triggers bus system clock RM0017 timers doc id 14629 rev 8 572/904 24.5.3 signal description the pit module has no external pins. 24.5.4 memory map and register description this section provides a detailed description of all registers accessible in the pit module. memory map table 278 gives an overview of the pit registers. see the chip memory map for the pit base address. note: register address = base address + address offset, where the base address is defined at the mcu level and the address offset is defined at the module level. note: reserved registers will read as 0, writes will have no effect. pit module control register (pitmcr) this register controls whether the timer clocks should be enabled and whether the timers should run in debug mode. table 278. pit memory map base address: 0xc3ff_0000 address offset use location 0x000 pit module control register (pitmcr) on page 24-572 0x004?0x0fc reserved 0x100?0x10c timer channel 0 see ta b l e 2 7 9 0x110?0x11c timer channel 1 see ta b l e 2 7 9 0x120?0x12c timer channel 2 see ta b l e 2 7 9 0x130?0x13c timer channel 3 see ta b l e 2 7 9 0x140?0x14c timer channel 4 see ta b l e 2 7 9 0x150?0x15c timer channel 5 see ta b l e 2 7 9 table 279. timer channel n address offset use location channel + 0x00 timer load value register (ldval) on page 24-573 channel + 0x04 current timer value register (cval) on page 24-574 channel + 0x08 timer control register (tctrl) on page 24-574 channel + 0x0c timer flag register (tflg) on page 24-575 timers RM0017 573/904 doc id 14629 rev 8 timer load value register (ldval) this register selects the timeout period for the timer interrupts. figure 301. pit module control register (pitmcr) offset: 0x000 access: read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 00000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0000 0 00 0 0 mdis frz w reset0000000000000010 table 280. pitmcr field descriptions field description mdis module disable this is used to disable the module clock. this bit should be enabled before any other setup is done. 0 clock for pit timers is enabled 1 clock for pit timers is disabled (default) frz freeze allows the timers to be stopped when the device enters debug mode. 0 = timers continue to run in debug mode. 1 = timers are stopped in debug mode. figure 302. timer load value register (ldval) offset: channel_base + 0x00 access: read/write 0123456789101112131415 r tsv[31:16] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r tsv[15:0] w reset0000000000000000 RM0017 timers doc id 14629 rev 8 574/904 current timer value register (cval) this register indicates the current timer position. timer control register (tctrl) this register contains the control bits for each timer. table 281. ldval field descriptions field description tsv time start value this field sets the timer start value. the timer counts down until it reache s 0, then it generates an interrupt and loads this register value again. writi ng a new value to this register does not restart the timer, instead the value is loaded once the timer expires. to abort the current cycle and start a timer period with the new value, the timer must be disabled and enabled again (see figure 307 ). figure 303. current timer value register (cval) offset: channel_base + 0x04 access: read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r tvl[31:16] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r tvl[15:0] w reset0000000000000000 table 282. cval field descriptions field description tvl current timer value this field represents the curre nt timer value. note that the timer uses a downcounter. note: the timer values will be frozen in debug mode if the frz bit is set in the pit module control register (see figure 246 ). timers RM0017 575/904 doc id 14629 rev 8 timer flag register (tflg) this register holds the pit interrupt flags. figure 304. timer control register (tctrl) offset: channel_base + 0x08 access: read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000000000000 tie ten w reset0000000000000000 table 283. tctrl field descriptions field description tie timer interrupt enable bit 0 interrupt requests from timer x are disabled 1 interrupt will be requested whenever tif is set when an interrupt is pending (tif set), enabling the interrupt will immediately cause an interrupt event. to avoid this, the associated tif flag must be cleared first. ten timer enable bit 0 timer will be disabled 1 timer will be active figure 305. timer flag register (tflg) offset: channel_base + 0x0c access: read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000000000 tif w w1c reset0000000000000000 RM0017 timers doc id 14629 rev 8 576/904 24.5.5 functional description general this section gives detailed information on the internal operation of the module. each timer can be used to generate trigger pulses as we ll as to generate interrupts, each interrupt will be available on a se parate interrupt line. timers the timers generate triggers at periodic intervals, when enabled. they load their start values, as specified in their ldval registers, then count down until they reach 0. then they load their respective start value again. each time a timer reaches 0, it will generate a trigger pulse and set the interrupt flag. all interrupts can be enabled or masked (by setting the tie bits in the tctrl registers). a new interrupt can be generated only after the previous one is cleared. if desired, the current counter value of the timer can be read via the cval registers. the counter period can be restarted, by first disabling, then enabling the timer with the ten bit (see figure 306 ). the counter period of a running timer can be modified, by first disabling the timer, setting a new load value and then enabling the timer again (see figure 307 ). it is also possible to change the counter period without restarting the timer by writing the ldval register with the new load value. this value will then be loaded after th e next trigger event (see figure 308 ). figure 306. stopping and starting a timer table 284. tflg field descriptions field description tif time interrupt flag tif is set to 1 at the end of the timer period. this fl ag can be cleared only by writing it with a 1. writing a 0 has no effect. if enabled (tie = 1 ), tif causes an interrupt request. 0 time-out has not yet occurred 1 time-out has occurred p1 p1 timer enabled disable timer p1 start value = p1 trigger event p1 re-enable timer timers RM0017 577/904 doc id 14629 rev 8 figure 307. modifying running timer period figure 308. dynamically setting a new load value debug mode in debug mode the timers will be frozen. this is intended to aid software development, allowing the developer to halt the processor, investigate the current state of the system (for example, the timer values) and then continue the operation. interrupts all of the timers support interrupt generation. see the intc chapter of the reference manual for related vector addresses and priorities. timer interrupts can be disabled by setting the tie bits to zero. the timer interrupt flags (tif) are set to 1 when a timeout occurs on the associated timer, and are cleared to 0 by writing a 1 to that tif bit. 24.5.6 initialization and application information example configuration in the example configuration: the pit clock has a frequency of 50 mhz timer 1 creates an interrupt every 5.12 ms timer 3 creates a trigger event every 30 ms first the pit module needs to be activated by programming pit_mcr[mdis] = 0. the 50 mhz clock frequency equates to a clock period of 20 ns. timer 1 needs to trigger every 5.12 ms/20 ns = 256000 cycles and timer 3 every 30 ms/20 ns = 1500000 cycles. the value for the ldval register trigger would be calculated as (period / clock period) ? 1. the ldval registers must be set as follows: ldval for timer 1 is set to 0x0003e7ff ldval for timer 3 is set to 0x0016e35f p1 timer enabled disable timer, start value = p1 trigger event re-enable timer p1 set new load value p2 p2 p2 p1 p1 timer enabled new start value p2 set p1 p2 start value = p1 p2 trigger event RM0017 timers doc id 14629 rev 8 578/904 the interrupt for timer 1 is enabled by setting tie in the tctrl1 register. the timer is started by writing a 1 to bit ten in the tctrl1 register. timer 3 shall be used only for triggering. therefore timer 3 is started by writing a 1 to bit ten in the tctrl3 register; bit tie stays at 0. the following example code matches the described setup: // turn on pit pit_ctrl = 0x00; // timer 1 pit_ldval1 = 0x0003e7ff; // setup timer 1 for 256000 cycles pit_tctrl1 = tie; // enable timer 1 interrupts pit_tctrl1 |= ten; // start timer 1 // timer 3 pit_ldval3 = 0x0016e35f; // setup timer 3 for 1500000 cycles pit_tctrl3 = ten; // start timer 3 analog-to-digital c onverter (adc) RM0017 579/904 doc id 14629 rev 8 25 analog-to-digital converter (adc) 25.1 overview 25.1.1 device-specific features 10-bit resolution 36 channels (depending on package type), expandable to 64 channels via external multiplexing ? as many as 16 precision channels ? as many as 20 standard channels, 4 being expandable to as many as 32 external channels address decoder signal generation (alternate functions ma[2:0]) to control external multiplexers individual conversion registers for each channel (internal and external) 3 different sampling and conversion time registers ctr[0:2] (internal precision channels, standard channels, external channels) as many as 64 data registers for storing converted data. conversion information, such as mode of operation (normal, injected or ctu), is associated to data value. conversion triggering sources: ? software ?ctu ? pit channel 2 (for injected conversion) 4 analog watchdogs ? interrupt capability ? allow continuous hardware monitoring of 4 analog input channels presampling (v ss and v dd ) conversions on external channels managed in the same way as internal channels, making it transparent to the application one shot/scan modes chain injection mode power-down mode 2 different abort functions allow to abort either single-channel conversion or chain conversion auto-clock-off RM0017 analog-to-digital converter (adc) doc id 14629 rev 8 580/904 25.1.2 device-specific implementation figure 309. adc implementation 25.2 introduction the analog-to-digital converter (adc) block provides accurate and fast conversions for a wide range of applications. the adc contains advanced features for normal or injected conversion. a conversion can be triggered by software or hardware (cross triggering unit or pit). there are three types of input channels: internal precision, adc0_p[n] (inter nally multiplexed precision channels) internal standard, adc0_s[n] (internally multiplexed standard channels) external adc0_x[n] (externally multiplexed standard channels) the mask registers present within the adc can be programmed to configure which channel has to be converted. three external decode signals ma[2:0] (multiplexer address) are provided for external channel selection and are available as alternate functions on gpio. the ma[0:2] are controlled by the adc itself and are set automatically by the hardware. a conversion timing register for configuring different sampling and conversion times is associated to each channel type. analog watchdogs allow continuous hardware monitoring. pit2 ctu emios pit ch23 trig pit3 adc control adc trigger adc done 2 interrupts adc_eoc & adc_wd digital interface analog switch intc d a mux 20 mux 16 adc_0 (10 bit) emios0_0 emios0_22 emios0_24 ch0 trig ch22 trig ch24 trig emios1_0 emios1_22 emios1_24 ch32 trig ch54 trig ch56 trig . . . . . . . . . . . . up to 20 standard channels 16 precision adc0_x[3] adc0_x[0] adc0_s[15] (ch 47) adc0_s[0] (ch 32) adc0_p[15] (ch 15) adc0_p[0] (ch 0) ma[2:0] mux 8 mux 8 3 . . . . . . adc0_x[2] adc0_x[1] mux 8 mux 8 (ch 88?95) (ch 64?71) (ch 80?87) (ch 72?79) channels up to 32 extended channels through external mux analog-to-digital c onverter (adc) RM0017 581/904 doc id 14629 rev 8 25.3 functional description 25.3.1 analog channel conversion three conversion modes are available within the adc: normal conversion injected conversion ctu triggered conversion normal conversion this is the normal conversion that the user programs by configuring the normal conversion mask registers (ncmr). each channel can be individually enabled by setting ?1? in the corresponding field of ncmr registers. mask registers must be programmed before starting the conversion and cannot be changed until the conversion of all the selected channels ends (nstart bit in the main status register (msr) is reset). start of normal conversion by programming the configuration bits in the main configuration register (mcr), the normal conversion can be started in two ways: by software (trgen reset)?if the external trigger enable bit is reset, the conversion chain starts when the mcr[nstart] bit is set. by trigger (trgen set)?an on-chip internal signal triggers an adc conversion. the settings in the mcr select how conversions are triggered based on these internal signals: ? if the edglev (edge/level selection) bit in the mcr is cleared, then a rising/falling edge (depending on the mcr[edge] bit) detected in the signal sets the msr[nstart] bit and starts the programmed conversion. edge = 0 selects a falling edge. edge = 1 selects a rising edge. ? if the edglev bit in the mcr is set, the conversion is started if and only if the mcr[nstart] bit is set and the programmed level on the trigger signal is detected. the level is selected using the mcr[edge] bit. edge = 0 means that the start of conversion is enabled if the signal is low. if edge = 1, the start of conversion is enabled when the signal is high. the msr[nstart] status bit is automatically set when the normal conversion starts. at the table 285. configurations for starting normal conversion type of conversion start mcr msr result trgen nstart edglev edge nstart software 0 1 ? ? 1 conversion chain starts trigger 1 ? 0 0 1 a falling edge detected in a trigger signal sets the nstart bit in the msr and starts the programmed conversion. 1 a rising edge detected in a trigger signal sets the nstart bit in the msr and starts the programmed conversion. RM0017 analog-to-digital converter (adc) doc id 14629 rev 8 582/904 same time the mcr[nstart] bit is reset, allowing the software to program a new start of conversion. in that case the new requested conversion starts after the running conversion is completed. if the content of all the normal conversion mask registers is zero (that is, no channel is selected) the conversion operation is considered completed and the interrupt ech (see interrupt controller chapter for further details) is immediately issued after the start of conversion. normal conversion operating modes two operating modes are available for the normal conversion: one shot scan to enter one of these modes, it is necessary to program the mcr[mode] bit. the first phase of the conversion process involves sampling the analog channel and the next phase involves the conversion phase when the sampled analog value is converted to digital as shown in figure 310 . figure 310. normal conversion flow in one shot mode (mode = 0) a sequential conversion specified in the ncmr registers is performed only once. at the end of each conversion, the digital result of the conversion is stored in the corresponding data register. example 3 one shot mode (mode = 0) channels a-b-c-d-e-f-g-h are present in the device where channels b-d-e are to be converted in the one shot mode. mode = 0 is set for one shot mode. conversion starts from the channel b followed by conversion of channels d-e. at the end of conversion of channel e the scanning of channels stops. the nstart status bit in the msr is automatically set when the normal conversion starts. at the same time the mcr[nstart] bit is reset, allowing the software to program a new trigger 1 1 1 01 the conversion is started if the programmed level on the trigger signal is detected: the start of conversion is enabled if the external pin is low. 11 the conversion is started if the programmed level on the trigger signal is detected: the start of conversion is enabled if the external pin is high. table 285. configurations for star ting normal conversion (continued) type of conversion start mcr msr result trgen nstart edglev edge nstart sample b convert b sample c sample d convert d sample e convert e convert c analog-to-digital c onverter (adc) RM0017 583/904 doc id 14629 rev 8 start of conversion. in that case the new requested conversion starts after the running conversion is completed. in scan mode (mode = 1), a sequential conversion of n channels specified in the ncmr registers is continuously performed. as in the previous case, at the end of each conversion the digital result of the conversion is stored into the corresponding data register. the msr[nstart] status bit is automatically set when the normal conversion starts. unlike one shot mode, the mcr[nstart] bit is not reset. it can be reset by software when the user needs to stop scan mode. in that case, the adc completes the current scan conversion and, after the last conversion, also resets the msr[nstart] bit. example 4 scan mode (mode = 1) channels a-b-c-d-e-f-g-h are present in the device where channels b-d-e are to be converted in the scan mode. mode = 1 is set for scan mode. conversion starts from the channel b followed by conversion of the channels d-e. at the end of conversion of channel e the scanning of channel b starts followed by conversion of the channels d-e. this sequence repeats itself till the m cr[nstart] bit is cleared by software. if the conversion is started by an external trigger and edglev is ?0?, the mcr[nstart] bit is not set. as a consequence, once started the only way to stop scan mode conversion is to set the mode bit to ?0?. at the end of each conversion an end of conversion interrupt is issued (if enabled by the corresponding mask bit) and at the end of the conversion sequence an end of chain interrupt is issued (if enabled by the corresponding mask bit in the imr register). injected channel conversion a conversion chain can be injected into the ongoing normal conversion by configuring the injected conversion mask registers (jcmr). as normal conversion, each channel can be individually selected. this injected conversion (which can only occur in one shot mode) interrupts the normal conversion(which can be in one shot or scan mode). when an injected conversion is inserted, ongoing normal channel conversion is aborted and the injected channel request is processed. after the last channel in the injected chain is converted, normal conversion resumes from the channel at which the normal conversion was aborted as shown in figure 311 . figure 311. injected sample/conversion sequence the ongoing channel conversion is interrupted and the injected conversion chain is processed first. after the injected chain is converted the normal chain conversion resumes from the channel at which normal conversion was aborted. injected conversion of channels i and j normal conversion resumes from the last aborted channel. sample b convert b sample c sample d convert d sample e convert e convert c sample c abort c sample i sample j convert j sample c convert c convert i RM0017 analog-to-digital converter (adc) doc id 14629 rev 8 584/904 the injected conversion can be started using two options: by software setting the mcr[jstart]; the current conversion is suspended and the injected chain is converted. at the end of the chain, the jstart bit in the msr is reset and the normal chain conversion is resumed. by an internal trigger signal from the pit when mcr[jtrgen] is set; a programmed event (rising/falling edge depending on mcr[je dge]) on the signal coming from pit starts the injected conversion by setting the msr[jstart]. at the end of the chain, the msr[jstart] is cleared and the normal conversion chain is resumed. the msr[jstart] is automatically set when the injected conversion starts. at the same time the mcr[jstart] is reset, allowing the software to program a new start of conversion. in that case the new requested conversion starts after the running injected conversion is completed. at the end of each injected conversion, an end of injected conversion (jeoc) interrupt is issued (if enabled by the imr[mskjeoc]) and at the end of the sequence an end of injected chain (jech) interrupt is issued (if enabled by the imr[mskjeoc]). if the content of all the injected conversion mask registers (jcmr) is zero (that is, no channel is selected) the jech interrupt is immediately issued after the start of conversion. abort conversion two different abort functions are provided. the user can abort the ongoing conversion by setting the mcr[abort] bit. the current conversion is aborted and the conversion of the next channel of the chain is immediately started. in the case of an abort operation, the nstart/jstart bit remains set and the abort bit is reset after the conversion of the next channel starts. the eoc interrupt corresponding to the aborted channel is not generated. this behavior is true for normal or injected conversion modes. if the last channel of a chain is aborted, the end of chain is reported generating an ech interrupt. it is also possible to abort the current chain conversion by setting the mcr[abortchain] bit. in that case the behavior of the adc depends on the mode bit. if scan mode is disabled, the nstart bit is automatically reset together with the mcr[abortchain] bit. otherwise, if the scan mode is enabled, a new chain conversion is started. the eoc interrupt of the current aborted conversion is not generated but an ech interrupt is generated to signal the end of the chain. when a chain conversion abort is requested (abortchain bit is set) while an injected conversion is running over a suspended normal conversion, both injected chain and normal conversion chain are aborted (both the nstart and jstart bits are also reset). 25.3.2 analog clock generator and conversion timings the clock frequency ca n be selected by programming th e mcr[adclksel]. when this bit is set to ?1? the adc clock has the same frequency as the peripheral set 3 clock. otherwise, the adc clock is half of the peripheral set 3 clock frequency. the adclksel bit can be written only in power-down mode. when the internal divider is not enabled (adcclksel = 1), it is important that the associated clock divider in the clock generation module is ?1?. this is needed to ensure 50% clock duty cycle. analog-to-digital c onverter (adc) RM0017 585/904 doc id 14629 rev 8 the direct clock should basically be used only in low power mode when the device is using only the 16 mhz fast internal rc oscillator, but the conversion still requires a 16 mhz clock (an 8 mhz clock is not fast enough). in all other cases, the adc should use the clock divided by two internally. 25.3.3 adc sampling a nd conversion timing in order to support different loading and switching times, several different conversion timing registers (ctr) are present. there is one register per channel type. inplatch and inpcmp configurations are limited when the system clock frequency is greater than 20 mhz. when a conversion is started, the adc connects the internal sampling capacitor to the respective analog input pin, allowing the capacitance to charge up to the input voltage value. the time to load the capacitor is referred to as sampling time. after completion of the sampling phase, the evaluation phase starts and all the bits corresponding to the resolution of the adc are estimated to provide the conversion result. the conversion times are programmed via the bi t fields of the ctr. bit fields inplatch, inpcmp and inpsamp are used to defi ne the total conversion duration (t conv ) and in particular the partition between sampling phase duration (t sample ) and total evaluation phase duration (t eval ). adc_0 figure 312 represents the sampling and conversion sequence. figure 312. sampling and conversion timings the sampling phase duration is: 0.5 cycles 2.5 cycles sampling phase successive approximation / evaluation phase 10 cycles latching phase: the capacitors field input switch is opened note: operating conditions ? inplatch = 0, inpsam p = 3, inpcmp = 1 and fadc clk = 20 mhz end of conversion t sample inpsamp ndelay ? () t ck ? = inpsamp 3 RM0017 analog-to-digital converter (adc) doc id 14629 rev 8 586/904 where ndelay is equal to 0.5 if inpsamp is less than or equal to 06h, otherwise it is 1. inpsamp must be greater than or equal to 3 (hardware requirement). the total evaluation phase duration is: inpcmp must be greater than or equal to 1 and inplatch must be less than incmp (hardware requirements). the total conversion duration is (not including external multiplexing): the timings refer to the unit t ck , where f ck = (1/2 x adc peripheral set clock). 25.3.4 adc ctu (cross triggering unit) overview the adc cross triggering unit (ctu) is added to enhance the injected conversion capability of the adc. the ctu is triggered by multiple input events (emios and pit) and can be used to select the channels to be converted from the appropriate event configuration register. a t eval 10 t biteval ? 10 inpcmp t ck ? () ? == inpcmp 1 () and inplatch inpcmp < () ? () ++ = table 286. adc sampling and conversi on timing at 5 v / 3.3 v for adc_0 clock (mhz) t ck ( s) inpsample (1) 1. where: inpsample 3 ndelay (2) 2. where: inpsamp 6, n = 0.5; inpsamp > 6, n = 1 t sample (3) 3. where: t sample = (inpsamp-n)t ck ; must be 500 ns t sample /t ck inpcmp t eval ( s) inplatch t conv ( s) t conv / t ck 6 0.167 4 0.5 0.583 3.500 1 1.667 0 2.333 14.000 7 0.143 4 0.5 0.500 3.500 1 1.429 0 2.000 14.000 8 0.125 5 0.5 0.563 4.500 1 1.250 0 1.875 15.000 16 0.063 9 1 0.500 8.000 1 0.625 0 1.188 19.000 32 0.031 17 1 0.500 16.000 2 0.625 1 1.156 37.000 table 287. max/min adc_clk frequency and related configuration settings at 5 v / 3.3 v for adc_0 inpcmp inplatch max f adc_clk min f adc_clk 00/01 020+4%6 1?? 10 0?? 132+4%6 11 0?? 132+4%9 analog-to-digital c onverter (adc) RM0017 587/904 doc id 14629 rev 8 single channel is converted for each reques t. after performing the conversion, the adc returns the result on internal bus. the ctu can be enabled by setting mcr[ctuen]. the ctu and the adc are synchronous with the peripheral set 3 clock in both cases. ctu in trigger mode in ctu trigger mode, normal and injected conversions tr iggered by the cpu are still enabled. once the ctu event configuration register (ctu_evtcfgrx) is configured and the corresponding trigger from the emios or pit is received, the conversion starts. the msr[ctustart] is set automatically at this poi nt and it is also au tomatically reset when the ctu triggered conversion is completed. if an injected conversion (programmed by the user by setting the jstart bit) is ongoing and ctu conversion is triggered, then the injected channel conversion chain is aborted and only the ctu triggered conversion proceeds. by aborting the injected conversion, the msr[jstart] is reset. that abort is signalled through the status bit msr[jabort]. if a normal conversion is ongoing and a ctu conversion is triggered, then any ongoing channel conversion is aborted and the ctu triggered conversion is processed. when it is finished, the normal conversion resumes from the channel at which the normal conversion was aborted. if another ctu conversion is triggered before the end of the conversion, that request is discarded. when a normal conversion is requested during ctu conversion (ctustart bit = ?1?), the normal conversion starts when ctu conversion is completed (ctustart = ?0?). otherwise, when an injected conversion is requested during ctu conversion, the injected conversion is discarded and the mcr[jstart] is immediately reset. 25.3.5 presampling introduction presampling is used to precharge or discharge the adc internal capacitor before it starts sampling of the analog input coming from the input pins. this is useful for resetting information regarding the last converted data or to have more accurate control of conversion speed. during presampling, the adc sa mples the internally generated voltage. presampling can be enabled/disabled on a chan nel basis by setting the corresponding bits in the psr registers. after enabling the presampling for a channel , the normal sequence of operation will be presampling + sampling + conversion for that channel. sampling of the channel can be bypassed by setting the preconv bit in the pscr. when sampling of a channel is bypassed, the sampled data of internal voltage in the presampling state is converted ( figure 313 , figure 314 ). RM0017 analog-to-digital converter (adc) doc id 14629 rev 8 588/904 figure 313. presampling sequence figure 314. presampling sequence with preconv = 1 presampling channel enable signals it is possible to select between two internally generated voltages v0 and v1 depending on the value of the pscr[preval] as shown in ta b l e 2 8 8 . three presampling value fields, one per channel type, in the pscr make it possible to select different presampling values for each type. 25.3.6 programmable analog watchdog introduction the analog watchdogs are used for determining whether the result of a channel conversion lies within a given guarded area (as shown in figure 315 ) specified by an upper and a lower threshold value named thrh and thrl respectively. presampling is enabled in the channel c and d. for channel b total conversion clock cycles = (s) + (c). for channel c and d total conversion clock cycles = (p) + (s) + (c). sample b convert b presample c convert c presample d sample d convert d sample c sample e sample b convert b presample c presample d convert d sample e convert e convert c presampling enabled in channel c and d but sampling is bypass ed in these channels by setting preconv = 1 in the pscr. for channel c and d total conversion clock cycles = (p) + (c). table 288. presampling voltage selection based on prevalx fields pscr[prevalx] presampling voltage 00 v0 = v ss_hv_adc 01 v1 = v dd_hv_adc 10 reserved 11 reserved analog-to-digital c onverter (adc) RM0017 589/904 doc id 14629 rev 8 figure 315. guarded area after the conversion of the selected channel, a comparison is performed between the converted value and the threshold values. if the converted value lies outside that guarded area then corresponding threshold violation interrupts are generated. the comparison result is stored as wtisr[wdgxh] and wtisr[wdgxl] as explained in ta b l e 2 8 9 . depending on the mask bits wtimr[mskwdgxl] and wtimr[mskwdgxh], an interrupt is generated on threshold violation. the channel on which the analog watchdog is to be applied is selected by the trc[thrch]. the analog watchdog is enabled by setting the corresponding trc[thren]. the lower and higher threshold values for the analog watchdog are programmed using the registers thrhlr. for example, if channel number 3 is to be monitored with threshol d values in thrhlr1, then the trc[thrch] is programm ed to select channel number 3. a set of threshold registers (thrhlrx and trcx ) can be linked only to a single channel for a particular thrch value. if another channel is to be monitored with same threshold values, then the trcx[thrch] has to be programmed again. note: if the higher threshold for the analog watchdog is programmed lower than the lower threshold and the converted value is less than the lower threshold, then the wdgxl interrupt for the low threshold violation is set, else if the converted value is greater than the lower threshold (consequently also greater than the higher threshold) then the interrupt wdgxh for high threshold violation is set. thus , the user should avoid that situation as it could lead to misinterpretation of the watchdog interrupts. thrh thrl analog voltage upper threshold lower threshold guarded area table 289. values of wdgxh and wdgxl fields wdgxh wdgxl converted data 1 0 converted data > thrh 0 1 converted data < thrl 0 0 thrl <= converted data <= thrh RM0017 analog-to-digital converter (adc) doc id 14629 rev 8 590/904 25.3.7 interrupts the adc generates the following maskable interrupt signals: adc_eoc interrupt requests ? eoc (end of conversion) ? ech (end of chain) ? jeoc (end of injected conversion) ? jech (end of injected chain) ? eoctu (end of ctu conversion) wdgxl and wdgxh (watchdog threshold) interrupt requests interrupts are generated during the conversion process to signal events such as end of conversion as explained in register descri ption for ceocfr[0..2]. two registers named ceocfr[0..2] (channel pending registers) and imr (interrupt mask register) are provided in order to check and enable the interrupt request to int module. interrupts can be individually enabled on a channel by channel basis by programming the cimr (channel interrupt mask register). several ceocfr[0..2] are also provided in order to signal which of the channels? measurement has been completed. the analog watchdog interrupts are handled by two registers wtisr (watchdog threshold interrupt status register) and wtimr (watchdog threshold interrupt mask register) in order to check and enable the interrupt request to the intc module. the watchdog interrupt source sets two pending bits wdgxh and wdgxl in the wtisr for each of the channels being monitored. the ceocfr[0..2] contains the interrupt pending request status. if the user wants to clear a particular interrupt event status, then writing a ?1? to the corresponding status bit clears the pending interrupt flag (at this write operation all the other bits of the ceocfr[0..2] must be maintained at ?0?). 25.3.8 external decode signals delay the adc provides several external decode signals to select which external channel has to be converted. in order to take into account the control switching time of the external analog multiplexer, a decode signals delay register (dsdr) is provided. the delay between the decoding signal selection and the actual start of conversion can be programmed by writing the field dsd[0:7]. after having selected the channel to be converted, the ma[0:2] control lines are automatically reset. for instance, in the event of normal scan conversion on anp[0] followed by anx[0,7] (adc ch 71) all the ma[0:2] bits are set and subsequently reset. 25.3.9 power-down mode the analog part of the adc can be put in low power mode by setting the mcr[pwdn]. after releasing the reset signal the adc analog module is kept in power-down mode by default, so this state must be exited before starting any operation by resetting the appropriate bit in the mcr. the power-down mode can be requested at any time by setting the mcr[pwdn]. if a conversion is ongoing, the adc must complete the conversion before entering the power analog-to-digital c onverter (adc) RM0017 591/904 doc id 14629 rev 8 down mode. in fact, the adc enters power-down mode only after completing the ongoing conversion. otherwise, the ongoing operation should be aborted manually by resetting the nstart bit and using the abortchain bit. msr[adcstatus] bit is set only wh en adc enters power-down mode. after the power-down phase is completed the process ongoing before the power-down phase must be restarted manually by setting the appropriate mcr[start] bit. resetting mcr[pwdn] bit and setting mcr[nstart] or mcr[jstart] bit during the same cycle is forbidden. if a ctu trigger pulse is received during power-down, it is discarded. if the ctu is enabled and the csr[ctustart] bit is ?1?, then the mcr[pwdn] bit cannot be set. when ctu trigger mode is enabled, the application has to wait for the end of conversion (ctustart bit automatically reset). 25.3.10 auto-clock-off mode to reduce power consumption during the idle mode of operation (without going into power- down mode), an ?auto-clock-off? feature can be enabled by setting the mcr[acko] bit. when enabled, the analog clock is automatically switched off when no operation is ongoing, that is, no conversion is programmed by the user. 25.4 register descriptions 25.4.1 introduction table 290 lists adc_0 registers with their address offsets and reset values. table 290. adc_0 digital registers base address: 0xffe0_0000 location address offset register name 0x0000 main configuration register (mcr) on page 25- 596 0x0004 main status register (msr) on page 25- 598 0x0008 .. 0x000f reserved ? 0x0010 interrupt status register (isr) on page 25- 600 0x0014 channel pending register (ceocfr0) on page 25- 600 0x0018 channel pending register (ceocfr1) on page 25- 600 0x001c channel pending register (ceocfr2) on page 25- 600 RM0017 analog-to-digital converter (adc) doc id 14629 rev 8 592/904 0x0020 interrupt mask register (imr) on page 25- 602 0x0024 channel interrupt mask register (cimr0) on page 25- 603 0x0028 channel interrupt mask register (cimr1) on page 25- 603 0x002c channel interrupt mask register (cimr2) on page 25- 603 0x0030 watchdog threshold interrupt status register (wtisr) on page 25- 605 0x0034 watchdog threshold interrupt mask register (wtimr) on page 25- 605 0x0038 .. 0x004f reserved ? 0x0050 threshold control register 0 (trc0) on page 25- 607 0x0054 threshold control register 1 (trc1) on page 25- 607 0x0058 threshold control register 2 (trc2) on page 25- 607 0x005c threshold control register 3 (trc3) on page 25- 607 0x0060 threshold register 0 (thrhlr0) on page 25- 608 0x0064 threshold register 1 (thrhlr1) on page 25- 608 0x0068 threshold register 2 (thrhlr2) on page 25- 608 0x006c threshold register 3 (thrhlr3) on page 25- 608 0x0080 presampling control register (pscr) on page 25- 608 0x0084 presampling register 0 (psr0) on page 25- 609 0x0088 presampling register 1 (psr1) on page 25- 609 0x008c presampling register 2 (psr2) on page 25- 609 0x0090 .. 0x0093 reserved ? 0x0094 conversion timing register 0 (ctr0) on page 25- 611 table 290. adc_0 digital registers (continued) base address: 0xffe0_0000 location address offset register name analog-to-digital c onverter (adc) RM0017 593/904 doc id 14629 rev 8 0x0098 conversion timing register 1 (ctr1) on page 25- 611 0x009c conversion timing register 2 (ctr2) on page 25- 611 0x00a0 .. 0x00a3 reserved ? 0x00a4 normal conversion mask register 0 (ncmr0) on page 25- 611 0x00a8 normal conversion mask register 1 (ncmr1) on page 25- 611 0x00ac normal conversion mask register 2 (ncmr2) on page 25- 611 0x00b0 .. 0x00b3 reserved ? 0x00b4 injected conversion mask register 0 (jcmr0) on page 25- 614 0x00b8 injected conversion mask register 1 (jcmr1) on page 25- 614 0x00bc injected conversion mask register 2 (jcmr2) on page 25- 614 0x00c0 .. 0x00c3 reserved ? 0x00c4 decode signals delay register (dsdr) on page 25- 616 0x00c8 power-down exit delay register (pdedr) on page 25- 616 0x00cc .. 0x00ff reserved ? 0x0100 channel 0 data register (cdr0) on page 25- 617 0x0104 channel 1 data register (cdr1) on page 25- 617 0x0108 channel 2 data register (cdr2) on page 25- 617 0x010c channel 3 data register (cdr3) on page 25- 617 0x0110 channel 4 data register (cdr4) on page 25- 617 0x0114 channel 5 data register (cdr5) on page 25- 617 0x0118 channel 6 data register (cdr6) on page 25- 617 0x011c channel 7 data register (cdr7) on page 25- 617 table 290. adc_0 digital registers (continued) base address: 0xffe0_0000 location address offset register name RM0017 analog-to-digital converter (adc) doc id 14629 rev 8 594/904 0x0120 channel 8 data register (cdr8) on page 25- 617 0x0124 channel 9 data register (cdr9) on page 25- 617 0x0128 channel 10 data register (cdr10) on page 25- 617 0x012c channel 11 data register (cdr11) on page 25- 617 0x0130 channel 12 data register (cdr12) on page 25- 617 0x0134 channel 13 data register (cdr13) on page 25- 617 0x0138 channel 14 data register (cdr14) on page 25- 617 0x013c channel 15 data register (cdr15) on page 25- 617 0x0140 .. 0x017f reserved ? 0x0180 channel 32 data register (cdr32) on page 25- 617 0x0184 channel 33 data register (cdr33) on page 25- 617 0x0188 channel 34 data register (cdr34) on page 25- 617 0x018c channel 35 data register (cdr35) on page 25- 617 0x0190 channel 36 data register (cdr36) on page 25- 617 0x0194 channel 37 data register (cdr37) on page 25- 617 0x0198 channel 38 data register (cdr38) on page 25- 617 0x019c channel 39 data register (cdr39) on page 25- 617 0x01a0 channel 40 data register (cdr40) on page 25- 617 0x01a4 channel 41 data register (cdr41) on page 25- 617 0x01a8 channel 42 data register (cdr42) on page 25- 617 0x01ac channel 43 data register (cdr43) on page 25- 617 table 290. adc_0 digital registers (continued) base address: 0xffe0_0000 location address offset register name analog-to-digital c onverter (adc) RM0017 595/904 doc id 14629 rev 8 0x01b0 channel 44 data register (cdr44) on page 25- 617 0x01b4 channel 45 data register (cdr45) on page 25- 617 0x01b8 channel 46 data register (cdr46) on page 25- 617 0x01bc channel 47 data register (cdr47) on page 25- 617 0x01c0 .. 0x01ff reserved ? 0x0200 channel 64 data register (cdr64) on page 25- 617 0x0204 channel 65 data register (cdr65) on page 25- 617 0x0208 channel 66 data register (cdr66) on page 25- 617 0x020c channel 67 data register (cdr67) on page 25- 617 0x0210 channel 68 data register (cdr68) on page 25- 617 0x0214 channel 69 data register (cdr69) on page 25- 617 0x0218 channel 70 data register (cdr70) on page 25- 617 0x021c channel 71 data register (cdr71) on page 25- 617 0x0220 channel 72 data register (cdr72) on page 25- 617 0x0224 channel 73 data register (cdr73) on page 25- 617 0x0228 channel 74 data register (cdr74) on page 25- 617 0x022c channel 75 data register (cdr75) on page 25- 617 0x0230 channel 76 data register (cdr76) on page 25- 617 0x0234 channel 77 data register (cdr77) on page 25- 617 0x0238 channel 78 data register (cdr78) on page 25- 617 0x023c channel 79 data register (cdr79) on page 25- 617 table 290. adc_0 digital registers (continued) base address: 0xffe0_0000 location address offset register name RM0017 analog-to-digital converter (adc) doc id 14629 rev 8 596/904 25.4.2 control logic registers main configuration register (mcr) the main configuration register (mcr) prov ides configuration settings for the adc. 0x0240 channel 80 data register (cdr80) on page 25- 617 0x0244 channel 81 data register (cdr81) on page 25- 617 0x0248 channel 82 data register (cdr82) on page 25- 617 0x024c channel 83 data register (cdr83) on page 25- 617 0x0250 channel 84 data register (cdr84) on page 25- 617 0x0254 channel 85 data register (cdr85) on page 25- 617 0x0258 channel 86 data register (cdr86) on page 25- 617 0x025c channel 87 data register (cdr87) on page 25- 617 0x0260 channel 88 data register (cdr88) on page 25- 617 0x0264 channel 89 data register (cdr89) on page 25- 617 0x0268 channel 90 data register (cdr90) on page 25- 617 0x026c channel 91 data register (cdr91) on page 25- 617 0x0270 channel 92 data register (cdr92) on page 25- 617 0x0274 channel 93 data register (cdr93) on page 25- 617 0x0278 channel 94 data register (cdr94) on page 25- 617 0x027c channel 95 data register (cdr95) on page 25- 617 0x0280 .. 0x02ff reserved ? table 290. adc_0 digital registers (continued) base address: 0xffe0_0000 location address offset register name analog-to-digital c onverter (adc) RM0017 597/904 doc id 14629 rev 8 figure 316. main configur ation register (mcr) address: base + 0x0000 access: user read/write 0123456789101112131415 r owren wlside mode 0000 nstart 0 jtrgen jedge jstart 00 ctuen 0 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000 adclk sel abort chain abort acko 0000 pwdn w reset00000000 00000001 table 291. mcr field descriptions field description owren overwrite enable this bit enables or disables the functional ity to overwrite unread converted data. 0 prevents overwrite of unread converted data; new result is discarded 1 enables converted data to be overwritten by a new conversion wlside write left/right-aligned 0 the conversion data is written right-aligned. 1 data is left-aligned (from 15 to (15 ? resolution + 1)). the wlside bit affects all the c dr registers simultaneously. see figure 343 and figure 343 . mode one shot/scan 0 one shot mode?configures the nor mal conversion of one chain. 1 scan mode?configures continuous chain conversion mode; when the programmed chain conversion is finished it restarts immediately. nstart normal start conversion setting this bit starts the chain or scan conversi on. resetting this bit during scan mode causes the current chain conversion to finish, then stops the operation. this bit stays high while the conversion is ongoing (or pending during injection mode). 0 causes the current chain conversion to finish and stops the operation 1 starts the chain or scan conversion jtrgen injection external trigger enable 0 external trigger disabled for channel injection 1 external trigger enabled for channel injection jedge injection trigger edge selection edge selection for external trigger, if jtrgen = 1. 0 selects falling edge for the external trigger 1 selects rising edge for the external trigger jstart injection start setting this bit will start the configured injected analog channels to be converted by software. resetting this bit has no effect, as the injected chain conversion cannot be interrupted. RM0017 analog-to-digital converter (adc) doc id 14629 rev 8 598/904 main status register (msr) the main status register (msr) provides status bits for the adc. ctuen cross trigger unit conversion enable 0 ctu triggered conversion disabled 1 ctu triggered conversion enabled adclksel analog clock select this bit can only be written when adc in power-down mode 0 adc clock frequency is half peripheral set clock frequency 1 adc clock frequency is equal to peripheral set clock frequency abortchain abort chain when this bit is set, the ongoing chain conversion is aborted. this bit is reset by hardware as soon as a new conversion is requested. 0 conversion is not affected 1 aborts the ongoing chain conversion abort abort conversion when this bit is set, the ongoing conversion is aborted and a new conversion is invoked. this bit is reset by hardware as soon as a new conversion is invoked. if it is set during a scan chain, only the ongoing conversion is aborted and the next conversion is performed as planned. 0 conversion is not affected 1 aborts the ongoing conversion acko auto-clock-off enable if set, this bit enables the auto clock off feature. 0 auto clock off disabled 1 auto clock off enabled pwdn power-down enable when this bit is set, the analog module is request ed to enter power down mode. when adc status is pwdn, resetting this bit starts adc transition to idle mode. 0 adc is in normal mode 1 adc has been requested to power down table 291. mcr field de scriptions (continued) field description analog-to-digital c onverter (adc) RM0017 599/904 doc id 14629 rev 8 note: msr[jstart] is automatically set when the injected conversion starts. at the same time mcr[jstart] is reset, allowing the software to program a new start of conversion. the jcmr registers do not change their values. figure 317. main status register (msr) address: base + 0x0004 access: user read-only 0123456789101112131415 r0000000 nstart jabort 00 jstart 0 00 ctustart w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r chaddr 0 00 ack0 0 0 adcstatus w reset00000000 00000001 table 292. msr field descriptions field description nstart this status bit is used to signal that a normal conversion is ongoing. jabort this status bit is used to signal that an injected conversion has been aborted. this bit is reset when a new injected conversion starts. jstart this status bit is used to signal that an injected conversion is ongoing. ctustart this status bit is used to signal that a ctu conversion is ongoing. chaddr current conversion channel address this status field indicates cu rrent conversion channel address. acko auto-clock-off enable this status bit is used to signal if the auto-clock-off feature is on. adcstatus the value of this parameter depends on adc status: 000 idle 001 power-down 010 wait state 011 reserved 100 sample 101 reserved 110 conversion 111 reserved RM0017 analog-to-digital converter (adc) doc id 14629 rev 8 600/904 25.4.3 interrupt registers interrupt status register (isr) the interrupt status register (isr) contains interrupt status bits for the adc. channel pending registers (ceocfr[0..2]) ceocfr0 = end of conversion pending interrupt for channel 0 to 15 (precision channels) ceocfr1 = end of conversion pending interrupt for channel 32 to 47 (standard channels) ceocfr2 = end of conversion pending interrupt for channel 64 to 95 (external multiplexed channels) figure 318. interrupt status register (isr) address: base + 0x0010 access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000 0 000 eo ctu jeoc jech eoc ech w w1c w1c w1c w1c w1c reset00000000 00000000 table 293. isr field descriptions field description eoctu end of ctu conversion interrupt flag when this bit is set, an eoctu interrupt has occurred. jeoc end of injected channel conversion interrupt flag when this bit is set, a jeoc interrupt has occurred. jech end of injected chain conversion interrupt flag when this bit is set, a jech interrupt has occurred. eoc end of channel conversion interrupt flag when this bit is set, an eoc interrupt has occurred. ech end of chain conversion interrupt flag when this bit is set, an ech interrupt has occurred. analog-to-digital c onverter (adc) RM0017 601/904 doc id 14629 rev 8 figure 319. channel pending register 0 (ceocfr0) address: base + 0x0014 access: user read/write 0123456789101112131415 r00000000 00000000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eoc_ch15 eoc_ch14 eoc_ch13 eoc_ch12 eoc_ch11 eoc_ch10 eoc_ch9 eoc_ch8 eoc_ch7 eoc_ch6 eoc_ch5 eoc_ch4 eoc_ch3 eoc_ch2 eoc_ch1 eoc_ch0 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset00000000 00000000 figure 320. channel pending register 1 (ceocfr1) address: base + 0x0018 access: user read/write 0123456789101112131415 r00000000 00000000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eoc_ch47 eoc_ch46 eoc_ch43 eoc_ch44 eoc_ch43 eoc_ch42 eoc_ch41 eoc_ch40 eoc_ch39 eoc_ch38 eoc_ch37 eoc_ch36 eoc_ch35 eoc_ch34 eoc_ch33 eoc_ch32 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset00000000 00000000 RM0017 analog-to-digital converter (adc) doc id 14629 rev 8 602/904 interrupt mask register (imr) the interrupt mask register (imr) contains the interrupt enable bits for the adc. figure 321. channel pending register 2 (ceocfr2) address: base + 0x001c access: user read/write 0123456789101112131415 r eoc_ch95 eoc_ch94 eoc_ch93 eoc_ch92 eoc_ch91 eoc_ch90 eoc_ch89 eoc_ch88 eoc_ch87 eoc_ch86 eoc_ch85 eoc_ch84 eoc_ch83 eoc_ch82 eoc_ch81 eoc_ch80 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eoc_ch79 eoc_ch78 eoc_ch77 eoc_ch76 eoc_ch75 eoc_ch74 eoc_ch73 eoc_ch72 eoc_ch71 eoc_ch70 eoc_ch69 eoc_ch68 eoc_ch67 eoc_ch66 eoc_ch65 eoc_ch64 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset00000000 00000000 table 294. ceocfr field descriptions field description eoc_chn when set, the measure of channel n is completed. figure 322. interrupt mask register (imr) address: base + 0x0020 access: user read/write 0123456789101112131415 r0000000 0 00000000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000 0 000 mske octu msk jeoc msk jech msk eoc msk ech w reset00000000 00000000 analog-to-digital c onverter (adc) RM0017 603/904 doc id 14629 rev 8 channel interrupt mask register (cimr[0..2]) cimr0 = enable bits for channel 0 to 15 (precision channels) cimr1 = enable bits for channel 32 to 47 (standard channels) cimr2 = enable bits for channel 64 to 95 (external multiplexed channels) table 295. interrupt mask register (imr) field descriptions field description mskeoctu mask for end of ctu conversion (eoctu) interrupt when set, the eoctu interrupt is enabled. mskjeoc mask for end of injected channel conversion (jeoc) interrupt when set, the jeoc interrupt is enabled. mskjech mask for end of injected chain conversion (jech) interrupt when set, the jech interrupt is enabled. mskeoc mask for end of channel conversion (eoc) interrupt when set, the eoc interrupt is enabled. mskech mask for end of chain conversion (ech) interrupt when set, the ech interrupt is enabled. figure 323. channel interrupt mask register 0 (cimr0) address: base + 0x0024 access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cim 15 cim 14 cim 13 cim 12 cim 11 cim 10 cim 9 cim 8 cim 7 cim 6 cim 5 cim 4 cim 3 cim 2 cim 1 cim 0 w reset00000000 00000000 RM0017 analog-to-digital converter (adc) doc id 14629 rev 8 604/904 figure 324. channel interrupt mask register 1 (cimr1) address: base + 0x0028 access: user read/write 0123456789101112131415 r00000000 00000000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cim 47 cim 46 cim 43 cim 44 cim 43 cim 42 cim 41 cim 40 cim 39 cim 38 cim 37 cim 36 cim 35 cim 34 cim 33 cim 32 w reset00000000 00000000 figure 325. channel interrupt mask register 2 (cimr2) address: base + 0x002c access: user read/write 0123456789101112131415 r cim 95 cim 94 cim 93 cim 92 cim 91 cim 90 cim 89 cim 88 cim 87 cim 86 cim 85 cim 84 cim 83 cim 82 cim 81 cim 80 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cim 79 cim 78 cim 77 cim 76 cim 75 cim 74 cim 73 cim 72 cim 71 cim 70 cim 69 cim 68 cim 67 cim 66 cim 65 cim 64 w reset00000000 00000000 table 296. cimr field descriptions field description cimn interrupt enable when set (cimn = 1), interrupt for channel n is enabled. analog-to-digital c onverter (adc) RM0017 605/904 doc id 14629 rev 8 watchdog threshold interrupt status register (wtisr) watchdog threshold interrupt mask register (wtimr) figure 326. watchdog threshold interrupt status register (wtisr) address: base + 0x0030 access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000 0 wdg 3h wdg 2h wdg 1h wdg 0h wdg 3l wdg 2l wdg 1l wdg 0l w w1c w1c w1c w1c w1c w1c w1c w1c reset00000000 00000000 table 297. wtisr field descriptions field description wdgxh this corresponds to the status flag generate d on the converted value being higher than the programmed higher threshold (for [x = 0..3]). wdgxl this corresponds to the status flag generated on the converted value being lower than the programmed lower threshold (for [x = 0..3]). figure 327. watchdog threshold interrupt mask register (wtimr) address: base + 0x0034 access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000 0msk wdg 3h msk wdg 2h msk wdg 1h msk wdg 0h msk wdg 3l msk wdg 2l msk wdg 1l msk wdg 0l w reset00000000 00000000 RM0017 analog-to-digital converter (adc) doc id 14629 rev 8 606/904 table 298. wtimr field descriptions field description mskwdgxh this corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold (for [x = 0..3]). when set the interrupt is enabled. mskwdgxl this corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold (for [x = 0..3]). when set the interrupt is enabled. analog-to-digital c onverter (adc) RM0017 607/904 doc id 14629 rev 8 25.4.4 threshold registers introduction these four registers are used to store the user programmable lower and upper thresholds? values. threshold control register (trcx, x = [0..3]) figure 328. threshold control register (trcx, x = [0..3]) address: base + 0x0050 (trc0) base + 0x0054 (trc1) base + 0x0058 (trc2) base + 0x005c (trc3) access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r thr en 000000 0 0 thrch w reset00000000 00000000 table 299. trcx field descriptions field description thren threshold enable when set, this bit enables the threshold det ection feature for the selected channel. thrch choose the channel for threshold comparison. RM0017 analog-to-digital converter (adc) doc id 14629 rev 8 608/904 threshold register (thrhlr[0:3]) the four thrhlr n registers are used to store the user-programmable thresholds? 10-bit values. 25.4.5 presampling registers presampling control register (pscr) figure 329. threshold register (thrhlr[0:3]) address: base + 0x0060 (thrhlr0) base + 0x0064 (thrhlr1) base + 0x0068 (thrhlr2) base + 0x006c (thrhlr3) access: user read/write 0123456789101112131415 r000000 thrh w reset00000011 11111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000 thrl w reset00000000 00000000 table 300. thrhlrx field descriptions field description thrh high threshold value for channel n . thrl low threshold value for channel n . figure 330. presampling control register (pscr) address: base + 0x0080 access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000 0 0 preval2 preval1 preval0 pre conv w reset00000000 00000000 analog-to-digital c onverter (adc) RM0017 609/904 doc id 14629 rev 8 presampling register (psr[0..2]) psr0 = enable bits of presampling for channel 0 to 15 (precision channels) psr1 = enable bits of presampling for channel 32 to 47 (standard channels) psr2 = enable bits of presampling for channel 64 to 95 (external multiplexed channels) table 301. pscr field descriptions field description preval2 internal voltage selection for presampling selects analog input voltage for presampling from the available two internal voltages (external multiplexed channels). see table 288 . preval1 internal voltage selection for presampling selects analog input voltage for presampling from the available two internal voltages (standard channels). see ta b l e 2 8 8 . preval0 internal voltage selection for presampling selects analog input voltage for presampling from the available two internal voltages (precision channels). see ta b l e 2 8 8 . preconv convert presampled value if bit preconv is set, presampling is followed by the conversion. sampling will be bypassed and conversion of presampled data will be done. figure 331. presampling register 0 (psr0) address: base + 0x0084 access: user read/write 0123456789101112131415 r00000000 00000000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pres 15 pres 14 pres 13 pres 12 pres 11 pres 10 pres 9 pres 8 pres 7 pres 6 pres 5 pres 4 pres 3 pres 2 pres 1 pres 0 w reset00000000 00000000 RM0017 analog-to-digital converter (adc) doc id 14629 rev 8 610/904 figure 332. presampling register 1 (psr1) address: base + 0x0088 access: user read/write 0123456789101112131415 r00000000 00000000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pres 47 pres 46 pres 43 pres 44 pres 43 pres 42 pres 41 pres 40 pres 39 pres 38 pres 37 pres 36 pres 35 pres 34 pres 33 pres 32 w reset00000000 00000000 figure 333. presampling register 2 (psr2) address: base + 0x008c access: user read/write 0123456789101112131415 r pres 95 pres 94 pres 93 pres 92 pres 91 pres 90 pres 89 pres 88 pres 87 pres 86 pres 85 pres 84 pres 83 pres 82 pres 81 pres 80 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pres 79 pres 78 pres 77 pres 76 pres 75 pres 74 pres 73 pres 72 pres 71 pres 70 pres 69 pres 68 pres 67 pres 66 pres 65 pres 64 w reset00000000 00000000 table 302. psr field descriptions field description presn presampling enable when set (presn = 1), presampling is enabled for channel n. analog-to-digital c onverter (adc) RM0017 611/904 doc id 14629 rev 8 25.4.6 conversion ti ming registers ctr[0..2] ctr0 = associated to internal precision channels (from 0 to 15) ctr1 = associated to standard channels (from 32 to 47) ctr2 = associated to external mu ltiplexed channels (from 64 to 95) 25.4.7 mask registers introduction these registers are used to program which of the 96 input channels must be converted during normal and injected conversion. normal conversion mask registers (ncmr[0..2]) ncmr0 = enable bits of normal sampling for channel 0 to 15 (precision channels) figure 334. conversion ti ming registers ctr[0..2] address: base + 0x0094 (ctr0) base + 0x0098 (ctr1) base + 0x009c (ctr2) access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r inplatch 0 offshift (1) 1. available only on ctr0 0 inpcmp 0 inpsamp w reset00000010 00000101 table 303. ctr field descriptions field description inplatch configuration bit for latching phase duration offshift configuration for offset shift characteristic 00 no shift (that is the transition between codes 000h and 001h) is reached when the a vin (analog input voltage) is equal to 1 lsb. 01 transition between code 000h and 001h is reached when the a vin is equal to1/2 lsb 10 transition between code 00h and 001h is reached when the a vin is equal to 0 11 not used note: available only on ctr0 inpcmp configuration bits for comparison phase duration inpsamp configuration bits fo r sampling phase duration RM0017 analog-to-digital converter (adc) doc id 14629 rev 8 612/904 ncmr1 = enable bits of normal sampling for channel 32 to 47 (standard channels) ncmr2 = enable bits of normal sampling for channel 64 to 95 (external multiplexed channels) figure 335. normal conversion mask register 0 (ncmr0) address: base + 0x00a4 access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ch15 ch14 ch13 ch12 ch11 ch10 ch9 ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 w reset00000000 00000000 figure 336. normal conversion mask register 1 (ncmr1) address: base + 0x00a8 access: user read/write 0123456789101112131415 r00000000 00000000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ch47 ch46 ch45 ch44 ch43 ch42 ch41 ch40 ch39 ch38 ch37 ch36 ch35 ch34 ch33 ch32 w reset00000000 00000000 analog-to-digital c onverter (adc) RM0017 613/904 doc id 14629 rev 8 note: the implicit ch annel conversion priority in the case in which all channels are selected is the following: adc0_p[0:x], adc0_s[0:y], adc0_x[0:z]. the channels always start with 0, the lowest index. figure 337. normal conversion mask register 2 (ncmr2) address: base + 0x00ac access: user read/write 0123456789101112131415 r ch95 ch94 ch93 ch92 ch91 ch90 ch89 ch88 ch87 ch86 ch85 ch84 ch83 ch82 ch81 ch80 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ch79 ch78 ch77 ch76 ch75 ch74 ch73 ch72 ch71 ch70 ch69 ch68 ch67 ch66 ch65 ch64 w reset00000000 00000000 table 304. ncmr field descriptions field description chn sampling enable when set sampling is enabled for channel n. RM0017 analog-to-digital converter (adc) doc id 14629 rev 8 614/904 injected conversion mask registers (jcmr[0..2]) jcmr0 = enable bits of injected sampling for channel 0 to 15 (precision channels) jcmr1 = enable bits of injected sampling for channel 32 to 47(standard channels) jcmr2 = enable bits of injected sampling fo r channel 64 to 95 (external multiplexed channels) figure 338. injected conversion mask register 0 (jcmr0) address: base + 0x00b4 access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ch15 ch14 ch13 ch12 ch11 ch10 ch9 ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 w reset00000000 00000000 figure 339. injected conversion mask register 1 (jcmr1) address: base + 0x00b8 access: user read/write 0123456789101112131415 r00000000 00000000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ch47 ch46 ch45 ch44 ch43 ch42 ch41 ch40 ch39 ch38 ch37 ch36 ch35 ch34 ch33 ch32 w reset00000000 00000000 analog-to-digital c onverter (adc) RM0017 615/904 doc id 14629 rev 8 figure 340. injected conversion mask register 2 (jcmr2) address: base + 0x00bc access: user read/write 0123456789101112131415 r ch95 ch94 ch93 ch92 ch91 ch90 ch89 ch88 ch87 ch86 ch85 ch84 ch83 ch82 ch81 ch80 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ch79 ch78 ch77 ch76 ch75 ch74 ch73 ch72 ch71 ch70 ch69 ch68 ch67 ch66 ch65 ch64 w reset00000000 00000000 table 305. jcmr field descriptions field description chn sampling enable when set, sampling is enabled for channel n. RM0017 analog-to-digital converter (adc) doc id 14629 rev 8 616/904 25.4.8 delay registers decode signals delay register (dsdr) power-down exit delay register (pdedr) figure 341. decode signals delay register (dsdr) address: base + 0x00c4 access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000 0 dsd w reset00000000 00000000 table 306. dsdr field descriptions field description dsd delay between the external decode signals and the start of the sampling phase it is used to take into account the settling time of the external multiplexer. the decode signal delay is calculated as: dsd 1/frequency of adc clock. note: when adc clock = peripheral clock/2 the dsd has to be incremented by 2 to see an additional adc clock cycle delay on the decode signal. for example: dsd = 0; 0 adc clock cycle delay dsd = 2; 1 adc clock cycle delay dsd = 4; 2 adc clock cycles delay figure 342. power-down ex it delay register (pdedr) address: base + 0x00c8 access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000 0 pded w reset00000000 00000000 analog-to-digital c onverter (adc) RM0017 617/904 doc id 14629 rev 8 25.4.9 data registers introduction adc conversion results are stored in data registers. there is one register per channel. channel data register (cdr[0..95]) cdr[0..15] = precision channels cdr[32..47] = standard channels cdr[64..95] = external multiplexed channels each data register also gives information regarding the corresponding result as described below. table 307. pdedr field descriptions field description pded delay between the power-down bit reset and the start of conversion. the delay is to allow time for the adc power supply to settle before commencing conversions. the power down delay is calculated as: pded x 1/frequency of adc clock. figure 343. channel data register (cdr[0..95]) address: see table 290 access: user read/write 0123456789101112131415 r0000000 0 0000 va lid over w result w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000 cdata[0:9] (mcr[wlside] = 0) w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cdata[0:9] (mcr[wlside] = 1) 000000 w reset00000000 00000000 table 308. cdr field descriptions field description valid used to notify when the data is valid (a new value has been written). it is automatically cleared when data is read. RM0017 analog-to-digital converter (adc) doc id 14629 rev 8 618/904 overw overwrite data this bit signals that the previous converted data has been overwritten by a new conversion. this functionality depends on the value of mcr[owren]: ? when owren = 0, then overw is frozen to 0 and cdata field is protected against being overwritten until being read. ? when owren = 1, then overw flags the cdata field overwrite status. 0 converted data has not been overwritten 1 previous converted data has been overwritten before having been read result this bit reflects the mode of conversion for the corresponding channel. 00 data is a result of normal conversion mode 01 data is a result of injected conversion mode 10 data is a result of ctu conversion mode 11 reserved cdata channel 0-95 converted data. depending on the valu e of the mcr[wlside] bit, the position of this bitfield can be changed as shown in figure 343 and figure 343 . table 308. cdr field d escriptions (continued) field description cross triggering unit (ctu) RM0017 619/904 doc id 14629 rev 8 26 cross triggering unit (ctu) 26.1 introduction the cross triggering unit (ctu) allows to synchronize an adc conversion with a timer event from emios (every mode which can generate a dma request can trigger ctu) or pit. to select which adc channel must be converted on a particular timer event, the ctu provides the adc with a 7-bit channel number. this channel number can be configured for each timer channel event by the application. 26.2 main features single cycle delayed trigger output. the trigger output is a combination of 64 (generic value) input flags/events connected to different timers in the system. one event configuration register dedicated to each timer event allows to define the corresponding adc channel. acknowledgment signal to emios/pit for clearing the flag synchronization with adc to avoid collision 26.3 block diagram the ctu block diagram is shown in figure 344 . figure 344. cross triggering unit block diagram event gen event gen event gen flag_ack next_cmd channel value select tr i g 0 tr i g 1 tr i g 6 3 channel value event arbitration & masking event configuration register 0 event configuration register 1 event configuration register 63 . . . . . . . . . . RM0017 cross triggering unit (ctu) doc id 14629 rev 8 620/904 26.4 memory map and register descriptions the ctu registers are listed in table 309 . every register can have 32-bit access. the base address of the ctu is 0xffe6_4000. 26.4.1 event configuration regist ers (ctu_evtcfgrx) (x = 0...63) table 309. ctu memory map base address: 0xffe6_4000 address offset register location 0x000?0x02f reserved 0x030?0x12c event configuration registers 0..63 (ctu_evtcfgr0..63) on page 26-620 figure 345. event configuration regi sters (ctu_evtcfgrx) (x = 0...63) offsets: 0x030?0x12c access: read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r tm 0000000 clr_flag (1) 1. this bit implementation is generic based and impl emented only for inputs mapped to pit event flags. 0 channel_value w reset0000000000000000 table 310. ctu_evtcfgrx field descriptions field description tm trigger mask 0: trigger masked 1: trigger enabled clr_flag to provide flag_ack through software 1: flag_ack is forced to ?1? for the particular event 0: flag_ack is dependent on flag servicing channel_ value channel value to be provided to adc cross triggering unit (ctu) RM0017 621/904 doc id 14629 rev 8 these registers contain the adc channel number to be converted when the timer event occurs. the clr_flag is used to clear the respective timer event flag by software (this applies only to the pit as the emios flags are automatically cleared by the ctu). the clr_flag bit has to be used cautiously as setting this bit may result in a loss of events. the event input can be masked by writing ?0? to bit tm of the ctu_evtcfgr register. writing ?1? to bit tm enables the ctu triggering for the corresponding emios channel. 26.5 functional description this peripheral is used to synchronize adc conversions with timer events (from emios or pit). when a timer event occurs, the ctu triggers an adc conversion providing the adc channel number to be converted. in case concurrent events occur the priority is managed according to the index of the timer event. the trigger output is a single cycle pulse used to trigger adc conversion of the channel number provided by the ctu. each trigger input from the ctu is connected to the event trigger signal of an emios channel. the assignment between emios outputs and ctu trigger inputs is defined in table 311 . table 311. trigger source ctu trigger no. module source 0 emios 0 channel_0 1 emios 0 channel_1 2 emios 0 channel_2 3 emios 0 channel_3 4 emios 0 channel_4 5 emios 0 channel_5 6 emios 0 channel_6 7 emios 0 channel_7 8 emios 0 channel_8 9 emios 0 channel_9 10 emios 0 channel_10 11 emios 0 channel_11 12 emios 0 channel_12 13 emios 0 channel_13 14 emios 0 channel_14 15 emios 0 channel_15 16 emios 0 channel_16 17 emios 0 channel_17 18 emios 0 channel_18 19 emios 0 channel_19 RM0017 cross triggering unit (ctu) doc id 14629 rev 8 622/904 20 emios 0 channel_20 21 emios 0 channel_21 22 emios 0 channel_22 23 pit pit_3 24 emios 0 channel_24 25 reserved 26 reserved 27 reserved 28 reserved 29 reserved 30 reserved 31 reserved 32 emios 1 channel_0 33 emios 1 channel_1 34 emios 1 channel_2 35 emios 1 channel_3 36 emios 1 channel_4 37 emios 1 channel_5 38 emios 1 channel_6 39 emios 1 channel_7 40 emios 1 channel_8 41 emios 1 channel_9 42 emios 1 channel_10 43 emios 1 channel_11 44 emios 1 channel_12 45 emios 1 channel_13 46 emios 1 channel_14 47 emios 1 channel_15 48 emios 1 channel_16 49 emios 1 channel_17 50 emios 1 channel_18 51 emios 1 channel_19 52 emios 1 channel_20 53 emios 1 channel_21 54 emios 1 channel_22 table 311. trigger source (continued) ctu trigger no. module source cross triggering unit (ctu) RM0017 623/904 doc id 14629 rev 8 each event has a dedicated configuration register (ctu_evtcfgr). these registers store a channel number which is used to communicate which channel needs to be converted. in case several events are pending for adc request, the priority is managed according to the timer event index. the lowest index has the highest priority. once an event has been serviced (conversion requested to adc) the emios flag is cleared by the ctu and next prior event is handled. the acknowledgment signal can be forced to ?1? by setting the clr_flag bit of the ctu_evtcfgr register. these bits are implemented for only those input flags to which pit flags are connected. providing these bits offers the option of clearing pit flags by software. 26.5.1 channel value the channel value stored in an event configuration register is demultiplexed to 7 bits and then provided to the adc. the mapping of the channel number value to the corresponding adc channel is provided in table 311 . 55 reserved 56 emios 1 channel_24 table 311. trigger source (continued) ctu trigger no. module source table 312. ctu-to-adc channel assignment 10-bit adc signal name 10 -bit adc channel # channel number in ctu_evtcfgrx adc_p[0] ch0 0 adc_p[1] ch1 1 adc_p[2] ch2 2 adc_p[3] ch3 3 adc_p[4] ch4 4 adc_p[5] ch5 5 adc_p[6] ch6 6 adc_p[7] ch7 7 adc_p[8] ch8 8 adc_p[9] ch9 9 adc_p[10] ch10 10 adc_p[11] ch11 11 adc_p[12] ch12 12 adc_p[13] ch13 13 adc_p[14] ch14 14 adc_p[15] ch15 15 RM0017 cross triggering unit (ctu) doc id 14629 rev 8 624/904 ctu channel mapping should be taken into consideration when programming an event configuration register. for example, if the channel value of any event configuration register is programmed to 16, it will actua lly correspond to adc channe l 32 and conversion will occur for this channel. adc_s[0] ch32 16 adc_s[1] ch33 17 adc_s[2] ch34 18 adc_s[3] ch35 19 adc_s[4] ch36 20 adc_s[5] ch37 21 adc_s[6] ch38 22 adc_s[7] ch39 23 adc_s[8] ch40 24 adc_s[9] ch41 25 adc_s[10] ch42 26 adc_s[11] ch43 27 adc_s[12] ch44 28 adc_s[13] ch45 29 adc_s[14] ch46 30 adc_s[15] ch47 31 adc_x[0] ch64 : ch71 32 : 39 adc_x[1] ch72 : ch79 40 : 47 adc_x[2] ch80 : ch87 48 : 55 adc_x[3] ch88 : ch95 56 : 63 table 312. ctu-to-adc channel assignment (continued) 10-bit adc signal name 10 -bit adc channel # channel number in ctu_evtcfgrx static ram (sram) RM0017 625/904 doc id 14629 rev 8 27 static ram (sram) 27.1 introduction the general-purpose sram has a size of 48 kb. in every mode other than standby all the 48 kb of sram are powered, while during standby mode the user can decide to retain 32 kb or just 8 kb. see the mc_me chapter in this reference manual for details. the sram provides the following features: sram can be read/written from any bus master byte, halfword and word addressable ecc (error correction code) protected wit h single-bit correction and double-bit detection 27.2 low power configuration in order to reduce leakage a portion of the sram can be switched off/unpowered during standby mode. 27.3 register memory map the l2sram occupies 48 kb of memory starting at the base address as shown in table 314 . the internal sram has no registers. registers for the sram ecc are located in the ecsm (see the error correction status module (ecsm) chapter of the reference manual for more information). table 313. low power configuration mode configuration run, test, safe and stop the entire sram is powered and operational. standby either 32 kb or just 8 kb of the sram remains powered. this option is software- selectable. table 314. sram memory map address register name register description size 0x4000_0000 (base) ? sra up to 48 kb RM0017 static ram (sram) doc id 14629 rev 8 626/904 27.4 sram ecc mechanism the sram ecc detects the following conditions and produces the following results: detects and corrects all 1-bit errors detects and flags all 2-bit errors as non-correctable errors detects 39-bit reads (32-bit data bus plus the 7-bit ecc) that return all zeros or all ones, asserts an error indicator on the bus cycle, and sets the error flag sram does not detect all errors greater than 2 bits. internal sram write operations are performed on the following byte boundaries: 1 byte (0:7 bits) 2 bytes (0:15 bits) 4 bytes or 1 word (0:31 bits) if the entire 32 data bits are written to sram, no read operation is performed and the ecc is calculated across the 32-bit data bus. the 8-bit ecc is appended to the data segment and written to sram. if the write operation is less than the entire 32-bit data width (1 or 2-byte segment), the following occurs: 1. the ecc mechanism checks the entire 32-bit data bus for errors, detecting and either correcting or flagging errors. 2. the write data bytes (1 or 2-byte segment) are merged with the corrected 32 bits on the data bus. 3. the ecc is then calculated on the resulting 32 bits formed in the previous step. 4. the 7-bit ecc result is appended to the 32 bits from the data bus, and the 39-bit value is then written to sram. 27.4.1 access timing the system bus is a two-stage pipelined bus, which makes the timing of any access dependent on the access during the previous clock cycle. ta b l e 3 1 5 lists the various combinations of read and write operations to sram and the number of wait states used for the each operation. the table columns contain the following information: current operation ? lists the type of sram operation currently executing previous operation ? lists the valid types of sram operations that can precede the current sram operation (valid operation during the preceding clock) wait states ? lists the number of wait states (bus clocks) the operation requires which depends on the combination of the current and previous operation static ram (sram) RM0017 627/904 doc id 14629 rev 8 27.4.2 reset effects on sram accesses asynchronous reset will possibly corrupt sram if it asserts during a read or write operation to sram. the completion of that access depends on the cycle at which the reset occurs. data read from or written to sram before the reset event occurred is retained, and no other address locations are accessed or changed. in case of no access ongoing when reset occurs, the sram corruption does not happen. instead, synchronous reset (sw reset) should be used in controlled function (without sram accesses) in case an init ialization procedure without sr am initialization is needed. 27.5 functional description ecc checks are performed during the read portion of an sram ecc read/write (r/w) operation, and ecc calculations are performed during the write portion of a r/w operation. because the ecc bits can contain random data after the device is powered on, the sram must be initialized by executing 32-bit write operations prior to any read accesses. this is also true for implicit read accesses caused by any write accesses of less than 32 bits as discussed in section 27.4 sram ecc mechanism . 27.6 initialization and application information to use the sram, the ecc must check all bits that require initialization after power on. all writes must specify an even number of registers performed on 32-bit word-aligned table 315. number of wait states required for sram operations operation type current operation previous operation number of wait states required read read idle 1 pipelined read 8, 16 or 32-bit write 0 (read from the same address) 1 (read from a different address) pipelined read read 0 write 8 or 16-bit write idle 1 read pipelined 8 or 16-bit write 2 32-bit write 8 or 16-bit write 0 (write to the same address) pipelined 8, 16 or 32-bit write 8, 16 or 32-bit write 0 32-bit write idle 0 32-bit write read RM0017 static ram (sram) doc id 14629 rev 8 628/904 boundaries. if the write is not the entire 32 bits (8 or 16 bits), a read / modify / write operation is generated that checks the ecc value upon the read. see section 27.4 sram ecc mechanism . flash memory RM0017 629/904 doc id 14629 rev 8 28 flash memory 28.1 introduction the flash memory comprises a platform flash memory controller (pflash) interface and the following flash memory arrays: one array of 512 kb for code (cflash) one array of 64 kb for data (dflash) the flash memory archit ecture of this device is illustrated in figure 346 . figure 346. flash memory architecture the primary function of the flash memory module is to serve as electrically programmable and erasable nonvolatile memory. nonvolatile memory may be used for instruction and/or data storage. the module is a nonvolatile solid-state silicon memory device consisting of: blocks (also called ?sectors?) of single transistor storage elements an electrical means for selectively adding (programming) and removing (erasing) charge from these elements a means of selectively sensing (reading) the charge stored in these elements crossbar switch bank0 (cflash) bank1 (dflash) 32 data (for eeprom array 0 512 kb array 0 1x128 page buffer 4x128 page buffer pflash controller emulation) cflash_pfcr0[b0_p0_bfe] cflash_mcr ... ... ... cflash_umisr4 cflash_pfcr1[b1_p0_bfe] dflash_mcr ... ... ... dflash_umisr4 flash memory flash memory 128 128 64 kb RM0017 flash memory doc id 14629 rev 8 630/904 the flash memory module is arra nged as two functional units: the flash memory core the memory interface the flash memory core is composed of arrayed nonvolatile storage elements, sense amplifiers, row decoders, column decoders and charge pumps. the arrayed storage elements in the flash memory core are subdivided into physically separate units referred to as blocks (or sectors). the memory interface contains the registers and logic which control the operation of the flash memory core. the memory interface is also the interface between the flash memory module and a platform flash memory controller. it contains the ecc logic and redundancy logic. a platform flash memory controller connects the flash memory module to a system bus, and contains all system level customizatio n required for the device application. 28.2 main features 28.3 block diagram the flash memory module contains one matrix module, composed of a single bank (bank 0) normally used for code storage. rww operations are not possible. modify operations are managed by an embedded flash memory program/erase controller (fpec). commands to the fpec are given through a user registers interface. the read data bus is 128 bits wide, while the flash memory registers are on a separate bus 32 bits wide addressed in the user memory map. the high voltages needed for program/erase operations are generated internally. table 316. flash memory features feature cflash dflash high read parallelism (128 bits) yes error correction code (sec-ded) to enhance data retention yes double word program (64 bits) yes sector erase ye s single bank?read-while-write (rww) no erase suspend ye s program suspend no software programmable program/erase protection to avoid unwanted writings ye s censored mode against piracy yes shadow sector available yes no one-time programmable (otp) area in test flash block yes boot sectors yes no flash memory RM0017 631/904 doc id 14629 rev 8 figure 347. cflash and dflash module structures 28.4 functional description 28.4.1 module structure the flash memory module is addressable by double word (64 bits) for program, and page (128 bits) for read. reads to the flash memory always return 128 bits, although read page buffering may be done in the platform flash memory controller. each read of the flash memory module retrieves a page, or four consecutive words (128 bits) of information. the address for each word retrieved within a page differs from the other addresses in the page only by address bits (3:2). the flash memory module supports fault tolerance through error correction code (ecc) or error detection, or both. the ecc implemented within the fl ash memory module will correct single bit failures and de tect double bit failures. the flash memory module uses an embedded hardware algorithm implemented in the memory interface to program and erase the flash memory core. the embedded hardware algorithm includes control logic that works with software block enables and software lock mechanisms to guard against accidental program/erase. the hardware algorithm performs the steps necessary to ensure that the storage elements are programmed and erased with sufficient margin to guarantee data inte grity and reliability. 512 kb: + 16 kb testflash hv generator flash memory controller flash memory matrix register program/erase registers interface flash memory interface + 16 kb shadow bank 0 cflash structure 64 kb: + 16 kb testflash hv generator flash memory controller flash memory matrix register program/erase registers interface flash memory interface bank 1 dflash structure 32 kb 2 16 kb 2 32 kb 3 128 kb 4 16 kb RM0017 flash memory doc id 14629 rev 8 632/904 in the flash memory module, logic levels are defined as follows: a programmed bit reads as logic level 0 (or low). an erased bit reads as logic level 1 (or high). program and erase of the flash memory module requires multiple system clock cycles to complete. the erase sequence may be suspended. the program and erase sequences may be aborted. 28.4.2 flash memory module sectorization cflash module sectorization the cflash module supports 512 kbof user memory, plus 16 kb of test memory (a portion of which is one-time programmable by the user). an extra 16 kb sector is available as shadow space usable for user option bits and censorship settings. the module is composed of a single bank (bank 0): read-while-write is not supported. bank 0 of the module is divided in 10 sectors including a reserved sector, named testflash, in which some one-time programmable (otp) user data are stored, as well as a shadow sector in which user erasable configuration values can be stored. the matrix module sectorization is shown in ta bl e 3 1 7 . the division into blocks of the flash memory module is also used to implement independent erase/program protection. a software mechanism is provided to independently lock/unlock each block in low and mid address space against program and erase. dflash module sectorization the dflash module supports 64 kb of user memory, plus 16 kb of test memory (a portion of which is one-time programmable by the user). the module is composed of a single bank (bank 0): read-while-write is not supported. table 317. cflash module sectorization bank sector addresses size (kb) address space cflash_lml field for locking the address space 0 0 0x00000000?0x00007fff 32 low llk0 1 0x00008000?0x0000bfff 16 llk1 2 0x0000c000?0x0000ffff 16 llk2 3 0x00010000?0x00017fff 32 llk3 4 0x00018000?0x0001ffff 32 llk4 5 0x00020000?0x0003ffff 128 llk5 6 0x00040000?0x0005ffff 128 mid mlk0 7 0x00060000?0x0007ffff 128 mlk1 shadow 0x00200000?0x00203fff 16 shadow tslk test 0x00400000?0x00403fff 16 test tslk flash memory RM0017 633/904 doc id 14629 rev 8 bank 0 of the 80 kb module is divided in four sectors. bank 0 also contains a reserved sector named testflash in which some one-time programmable user data are stored. the sectorization of the 80 kb matrix module is shown in ta b l e 3 1 8 . the flash memory module is divided into blocks also to implement independent erase/program protection. a software mechanism is provided to independently lock/unlock each block in low and mid address space against program and erase. 28.4.3 testflash block a testflash block is available in both the cflash and dflash modules. the testflash block exists outside the normal address space and is programmed and read independently of the other blocks. the independent testflash block is included to also support systems which require nonvolatile memory for se curity or to store system init ialization information, or both. a section of the testflash is reserved to store the nonvolatile information related to redundancy, configuration and protection. the ecc is also applied to testflash. the structure of the testflash sector is detailed in table 319 and ta b l e 3 2 0 . table 318. dflash module sectorization bank sector addresses size (kb) address space dflash_lml field for locking the address space 0 0 0x00800000?0x00803fff 16 low llk0 1 0x00804000?0x00807fff llk1 2 0x00808000?0x0080bfff llk2 3 0x0080c000?0x0080ffff llk3 test 0x00c00000?0x00c03fff test tslk table 319. cflash testflash structure name description addresses size ? user otp area 0x400000?0x401fff 8192 bytes ? reserved 0x402000?0x403cff 7424 bytes ? user otp area 0x403d00?0x403de7 232 bytes cflash_nvlml cflash nonvolatile low/mid address space block locking register 0x403de8?0x403def 8 bytes ? reserved 0x403df0?0x403df7 8 bytes cflash_nvsll cflash nonvolatile secondary low/mid address space block locking register 0x403df8?0x403dff 8 bytes ? user otp area 0x403e00?0x403eff 256 bytes ? reserved 0x403f00?0x403fff 256 bytes RM0017 flash memory doc id 14629 rev 8 634/904 erase of the testflash block is always locked. user mode program of the testflash bloc k are enabled only when mcr[peas] is high. the testflash block may be locked/unlocked against program by using the lml[tslk] and sll[stslk] registers. programming of the testflash block has similar restrictions as the array in terms of how ecc is calculated. only one programming op eration is allowed per 64-bit ecc segment. the first 8 kb of testflash block may be used for user defined functions (possibly to store serial numbers, other configuration words or factory process codes). locations of the testflash other than the first 8 kb of otp area cannot be programmed by the user application. 28.4.4 shadow sector the shadow sector is only present in the cflash module. user mode program and erase of the shadow sector are enabled only when cflash_mcr[peas] is high. the shadow sector may be locked/unlocked against program or erase by using the cflash_lml[tslk] and cflash_sll[stslk] fields. programming of the shadow sector has similar restrictions as the array in terms of how ecc is calculated. only one programming operation is allowed per 64-bit ecc segment between erases. erase of the shadow sector is done similarly to a sector erase. the shadow sector contains specified data that are needed for user features. the user area of shadow sector may be used for user defined functions (possibly to store boot code, other configuration words or factory process codes). the structure of the shadow sector is detailed in ta b l e 3 2 1 . table 320. dflash testflash structure name description addresses size ? user otp area 0xc00000?0xc01fff 8192 bytes ? reserved 0xc02000?0xc03cff 7424 bytes ? user otp area 0xc03d00?0xc03de7 232 bytes dflash_nvlml dflash nonvolatile low/mid address space block locking register 0xc03de8?0xc03def 8 bytes ? reserved 0xc03df0?0xc03df7 8 bytes dflash_nvsll dflash nonvolatile secondary low/mid address space block locking register 0xc03df8?0xc03dff 8 bytes ? user otp area 0xc03e00?0xc03eff 256 bytes ? reserved 0xc03f00?0xc03fff 256 bytes flash memory RM0017 635/904 doc id 14629 rev 8 28.4.5 user mode operation in user mode the flash memory module may be read and written (register writes and interlock writes), programmed or erased. the default state of the flash memory module is read. the main, shadow and test address space can be read only in the read state. the majority of cflash and dflash memory-mapped registers can be read even when the cflash or dflash is in power-down or lo w-power mode. the exceptions are as follows: cflash ? ut0[mre, mrv, ais, dsi0:7] ?ut1 ?ut2 dflash ? ut0[mre, mrv, ais, dsi0:7] ?ut1 ?ut2 the flash memory module enters the read state on reset. the module is in the read state under two sets of conditions: the read state is active when the module is enabled (user mode read). the read state is active when the ers and esus fields in the corresponding mcr (cflash_mcr or dflash_mcr) are 1 and the pgm field is 0 (erase suspend). flash memory core reads return 128 bits (1 page = 2 double words). registers reads return 32 bits (1 word). flash memory core reads are done through the platform flash memory controller. registers reads to unmapped register address space will return all 0?s. registers writes to unmapped register address space will have no effect. table 321. shadow sector structure name description addresses size (bytes) ? user area 0x200000?0x203dcf 15824 ? reserved 0x203dd0?0x203dd7 8 nvpwd0?1 nonvolatile private censorship password 0?1 registers 0x203dd8?0x203ddf 8 nvscc0?1 nonvolatile system censorship control 0?1 registers 0x203de0?0x203de7 8 ? reserved 0x203de8?0x203dff 24 nvpfapr nonvolatile platform flash memory access protection register 0x203e00?0x203e07 8 ? reserved 0x203e08?0x203e17 16 nvusro nonvolatile user opti ons register 0x203e18?0x203e1f 8 ? reserved 0x203e20?0x203fff 480 RM0017 flash memory doc id 14629 rev 8 636/904 attempted array reads to invalid locations will result in indete rminate data. invalid locations occur when blocks that do not exist in non 2 n array sizes are addressed. attempted interlock writes to invalid locations will result in an interlock oc curring, but attempts to program these blocks will not occur since they are forced to be locked. erase will occur to selected and unlocked blocks even if the interlock write is to an invalid location. simultaneous read cycle on the flash matrix and read/write cycles on the registers are possible . on the contrary, registers read/write accesses simultaneous to a flash matrix interlock write are forbidden. 28.4.6 reset a reset is the highest priority operation for the flash memory module and terminates all other operations. the flash memory module uses reset to initialize register and status bits to their default reset values. if the flash memory module is executing a program or erase operation (pgm = 1 or ers = 1 in cflash_mcr or dflash_mcr) and a reset is issued, the operation will be suddenly termin ated and the module will disa ble the high voltage logic without damage to the high voltage circuits. reset terminates all operations and forces the flash memory module into user mode ready to receive accesses. reset and power-off must not be used as a systematic way to terminate a program or erase operation. after reset is negated, read register access may be done , although it should be noted that registers that require updating from shadow information, or other inputs, may not read updated values until the done field (in cflash_mcr or dflash_mcr) transitions. the done field may be polled to determine if the flash memory module has transitioned out of reset. notice that the registers cannot be written until the done field is high. 28.4.7 power-down mode all flash memory dc current sources can be turned off in power-down mode, so that all power dissipation is due only to leakage in this mode. flash memory power-down mode can be selected at me_ flash memory RM0017 637/904 doc id 14629 rev 8 28.4.8 low power mode the low power mode turns off most of the dc current sources within the flash memory module. flash memory low power mode can be selected at me_ RM0017 flash memory doc id 14629 rev 8 638/904 in the following some nonvolatile registers are described. please notice that such entities are not flip-flops, but locations of testflash or shadow sectors with a special meaning. 0x004c cflash user multiple i nput signature register 1 (cflash_umisr1) on page 28-660 0x0050 cflash user multiple i nput signature register 2 (cflash_umisr2) on page 28-661 0x0054 cflash user multiple i nput signature register 3 (cflash_umisr3) on page 28-662 0x0058 cflash user multiple i nput signature register 4 (cflash_umisr4) on page 28-663 table 323. dflash registers address offset register name location 0x0000 dflash module configuration register (dflash_mcr) on page 28-668 0x0004 dflash low/mid address space block locking register (dflash_lml) on page 28-674 0x0008 reserved ? 0x000c dflash secondary low/mid address space block locking register (dflash_sll) on page 28-678 0x0010 dflash low/mid address space block select register (dflash_lms) on page 28-682 0x0014 reserved ? 0x0018 dflash address register (dflash_adr) on page 28-682 0x001c?0x0038 reserved ? 0x003c dflash user test 0 register (dflash_ut0) on page 28-683 0x0040 dflash user test 1 register (dflash_ut1) on page 28-686 0x0044 dflash user test 2 register (dflash_ut2) on page 28-686 0x0048 dflash user multiple i nput signature register 0 (dflash_umisr0) on page 28-687 0x004c dflash user multiple i nput signature register 1 (dflash_umisr1) on page 28-688 0x0050 dflash user multiple i nput signature register 2 (dflash_umisr2) on page 28-689 0x0054 dflash user multiple i nput signature register 3 (dflash_umisr3) on page 28-690 0x0058 dflash user multiple i nput signature register 4 (dflash_umisr4) on page 28-691 table 322. cflash registers (continued) address offset register location flash memory RM0017 639/904 doc id 14629 rev 8 during the flash memory initialization phase, the fpec reads these nonvolatile registers and updates the corresponding volatile registers. when the fpec detects ecc double errors in these special locations, it behaves in the following way: in case of a failing system locations (c onfigurations, device options, redundancy, embedded firmware), the initialization phase is interrupted and a fatal error is flagged. in case of failing user loca tions (protections, censorship, platform flash memory controller, ...), the volatile registers ar e filled with all ?1?s and the flash memory initialization ends setting low the peg bit of the corresponding mcr (cflash_mcr or dflash_mcr). 28.5.1 cflash register description cflash module configuration register (cflash_mcr) the cflash module configuration register is used to enable and monitor all modify operations of the flash memory module. figure 348. cflash module configuration register (cflash_mcr) offset: 0x0000 access: read/write 0123456789101112131415 redc0000 size 0 las 000mas ww1c reset0000001000100000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reer rwe 0 0 peas done peg0000 pgm psus ers esus ehv ww1c w1c reset0000011000000000 table 324. cflash_mcr field descriptions field description edc ecc data correction edc provides information on previous reads. if an ecc single error detection and correction occurred, the edc bit is set to ?1?. th is bit must then be cleared, or a reset must occur before this bit will return to a 0 state. this bit may not be set to ?1? by the user. in the event of an ecc double error detection, this bit will not be set. if edc is not set, or remains 0, this indicates that all previous reads (from the last reset, or clearing of edc) were not corrected through ecc. 0: reads are occurring normally. 1: an ecc single error occurred and was corrected during a previous read. size array space size the value of size field is dependent upon th e size of the flash memory module; see ta bl e 3 2 5 . RM0017 flash memory doc id 14629 rev 8 640/904 las low address space the value of the las field corresponds to the configuration of the low address space; see ta bl e 3 2 6 . mas mid address space the value of the mas field corresponds to the configuration of the mid address space; see ta bl e 3 2 7 . eer ecc event error eer provides information on previous reads. if an ecc double error detection occurred, the eer bit is set to ?1?. this bit must then be cleared, or a reset must occur before this bit will return to a 0 state. this bit may not be set to ?1? by the user. in the event of an ecc single error detection and correction, this bit will not be set. if eer is not set, or remains 0, this indicates th at all previous reads (from the last reset, or clearing of eer) were correct. 0: reads are occurring normally. 1: an ecc double error occurred during a previous read. rwe read-while-write event error rwe provides information on previous reads when a modify operation is on going. if a rww error occurs, the rwe bit is set to ?1?. read-while-write erro r means that a read access to the flash memory matrix has occurred while the fpec was performing a program or erase operation or an array integrity check. this bit must then be cleared, or a reset must occur before this bit will return to a 0 state. this bit may not be set to ?1? by the user. if rwe is not set, or remains 0, this indicates that all previous rww reads (from the last reset, or clearing of rwe) were correct. 0: reads are occurring normally. 1: a rww error occurred during a previous read. peas program/erase access space peas is used to indicate which space is valid for program and erase operations: main array space or shadow/test space. peas = 0 indicates that the main address space is active for all flash memory module program and erase operations. peas = 1 indicates that the test or shadow address space is active for program and erase. the value in peas is captured and held with the first interlock write done for modify operations. the va lue of peas is retained between sampling events (that is, subsequent first interlock writes). 0: shadow/test address space is disabled for program/erase and main address space enabled. 1: shadow/test address space is enabled for program/erase and main address space disabled. table 324. cflash_mcr field descriptions (continued) field description flash memory RM0017 641/904 doc id 14629 rev 8 done modify operation done done indicates if the flash memory mo dule is performing a high voltage operation. done is set to 1 on termination of the flash memory module reset. done is cleared to 0 just after a 0 to 1 tran sition of ehv, which initiates a high voltage operation, or after resuming a suspended operation. done is set to 1 at the end of prog ram and erase high voltage sequences. done is set to 1 (within t pabt or t eabt , equal to p/e abort latency) after a 1 to 0 transition of ehv, which aborts a high voltage program/erase operation. done is set to 1 (within t esus , time equals to erase suspend latency) after a 0 to 1 transition of esus, which suspends an erase operation. 0: flash memory is executing a high voltage operation. 1: flash memory is not executing a high voltage operation. peg program/erase good the peg bit indicates the completion status of the last flash memory program or erase sequence for which high voltage operations we re initiated. the value of peg is updated automatically during the program and erase high voltage operations. aborting a program/erase high voltage operation will cause peg to be cleared to 0, indicating the sequence failed. peg is set to 1 when the fl ash memory module is reset, unless a flash memory initialization error has been detected. the value of peg is valid only when pgm=1 and/or ers=1 and after done transitions from 0 to 1 due to an abort or the completion of a program/erase operation. peg is valid until pgm/ers makes a 1 to 0 transition or ehv makes a 0 to 1 transition. the value in peg is not valid after a 0 to 1 transition of done caused by esus being set to logic 1. if program or erase are attempted on blocks that are locked, the response will be pe g=1, indicating that the operation was succesful, and the content of the block were properly protected from the program or erase operation. if a program operation tries to program at ?1? bits that are at ?0?, the program operation is correctly executed on the new bits to be progra mmed at ?0?, but peg is cleared, indicating that the requested operation has failed. in array integrity check or margin read peg is set to 1 when the operation is completed, regardl ess the occurrence of any error. the presence of errors can be detected only comparing checksum value stored in umirs0-1. aborting an array integrity check or a margin read operation will cause peg to be cleared to 0, indicating the sequence failed. 0: program, erase operation failed or program, erase, array integrity check or maring mode aborted. 1: program or erase operation succesful or array integrity check or maring mode completed. pgm program pgm is used to set up the flash memory module for a program operation. a 0 to 1 transition of pgm initiates a program sequence. a 1 to 0 transition of pgm ends the program sequence. pgm can be set only under user mode read (ers is low and ut0[aie] is low). pgm can be cleared by the user only when ehv is low and done is high. pgm is cleared on reset. 0: flash memory is not executing a program sequence. 1: flash memory is executing a program sequence. psus program suspend write this bit has no effect, but the written data can be read back. table 324. cflash_mcr field descriptions (continued) field description RM0017 flash memory doc id 14629 rev 8 642/904 ers erase ers is used to set up the flash memory module for an erase operation. a 0 to 1 transition of ers initiates an erase sequence. a 1 to 0 transition of ers ends the erase sequence. ers can be set only under user mode read (pgm is low and ut0[aie] is low). ers can be cleared by the user only when esus and ehv are low and done is high. ers is cleared on reset. 0: flash memory is not executing an erase sequence. 1: flash memory is executing an erase sequence. esus erase suspend esus is used to indicate that the flash memory module is in erase suspend or in the process of entering a suspend state. the flas h memory module is in erase suspend when esus = 1 and done = 1. esus can be set high only when ers and ehv are high and pgm is low. a 0 to 1 transition of esus starts the sequ ence which sets done and places the flash memory in erase suspend. the flash memory module enters suspend within t esus of this transition. esus can be cleared only when done and ehv are high and pgm is low. a 1 to 0 transition of esus with ehv = 1 starts the sequence which clears done and returns the module to erase. the flash memory module cannot exit erase suspend and clear done while ehv is low. esus is cleared on reset. 0: erase sequence is not suspended. 1: erase sequence is suspended. ehv enable high voltage the ehv bit enables the flash memory module for a high voltage program/erase operation. ehv is cleared on reset. ehv must be set after an interlock write to start a program/erase sequence. ehv may be set under one of the following conditions: erase (ers = 1, esus = 0, ut0[aie] = 0) program (ers = 0, esus = 0, pgm = 1, ut0[aie] = 0) in normal operation, a 1 to 0 transition of ehv with done high and esus low terminates the current program/erase high voltage operation. when an operation is aborted, there is a 1 to 0 transition of ehv with done low and the eventual suspend bit low. an abort causes the value of peg to be cleared, indicating a failing program/erase; address locations being operated on by the aborted operation contain indeterminate data after an abort. a susp ended operation cannot be aborted. aborting a high voltage operation will leave the flash memory module addresses in an indeterminate data state. this may be recovere d by executing an erase on the affected blocks. ehv may be written during suspend. ehv must be high to exit suspend. ehv may not be written after esus is set and before done transitions high. ehv may not be cleared after esus is cleared and before done transitions low. 0: flash memory is not enabled to perform an high voltage operation. 1: flash memory is enabled to perform an high voltage operation. table 324. cflash_mcr field descriptions (continued) field description flash memory RM0017 643/904 doc id 14629 rev 8 a number of cflash_mcr bits are protected against write when another bit, or set of bits, is in a specific state. these write locks are covered on a bit by bit basis in the preceding description, but those locks do not consider the effects of trying to write two or more bits simultaneously. the flash memory module does not allow the user to write bits simultaneously which would put the device into an illegal state. this is implemented through a pr iority mechanism among the bits. the bit changing priorities are detailed in ta b l e 3 2 8 . table 325. array space size size array space size 000 128 kb 001 256 kb 010 512 kb 011 1024 kb 100 1536 kb 101 reserved (2048 kb) 110 64 kb 111 reserved table 326. low address space configuration las low address space sectorization 000 reserved 001 reserved 010 32 kb + 2 x 16 kb + 2 x 32 kb + 128 kb 011 reserved 100 reserved 101 reserved 110 4 x 16 kb 111 reserved table 327. mid address space configuration mas mid address space sectorization 0 2 x 128 kb or 0 kb 1 reserved RM0017 flash memory doc id 14629 rev 8 644/904 if the user attempts to write two or more cflash_mcr bits simultaneously then only the bit with the lowest priority level is written. if stall/abort-while-write is enabled and an erase operation is started on one sector while fetching code from another then the following sequence is executed: cpu is stalled when flash is unavailable peg flag set (stall case) or reset (abort case) interrupt triggered if enabled if stall/abort-while-write is used then application software should ignore the setting of the rwe flag. the rwe flag should be cleared after each hv operation. if stall/abort-while-write is not used the application software should handle rwe error. see section 28.8.10, read-while-write functionality . cflash low/mid address space block locking register (cflash_lml) the cflash low/mid address space block locking register provides a means to protect blocks from being modified. these bits, along with bits in the cflash_sll register, determine if the block is locked from program or erase. an ?or? of cflash_lml and cflash_sll determine the final lock status. table 328. cflash_mcr bits set/clear priority levels priority level cflash_mcr bits 1ers 2pgm 3ehv 4 esus figure 349. cflash low/mid address sp ace block locking register (cflash_lml) offset: 0x0004 access: read/write 0123456789101112131415 rlme0000000000 tslk 00 mlk w reset defined by cflash_nvlml at cflash test sector address 0x403de8. this location is user otp (one time programmable). the cflash_nvlml register influences only the r/w bits of the cflash_lml register. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000 llk w reset defined by cflash_nvlml at cflash test sector address 0x403de8. this location is user otp (one time programmable). the cflash_nvlml register influences only the r/w bits of the cflash_lml register. flash memory RM0017 645/904 doc id 14629 rev 8 table 329. cflash_l ml field descriptions field description lme low/mid address space block enable this bit is used to enable the lock registers (tslk, mlk1-0 and llk15-0) to be set or cleared by registers writes. this bit is a status bit only. the method to set this bit is to write a password, and if the password matches, the lme bit will be set to re flect the status of enabled, and is enabled until a reset operation occurs. for lme the password 0xa1a11111 must be written to the cflash_lml register. 0 low address locks are disabled: tslk, mlk1-0 and llk15-0 cannot be written. 1 low address locks are enabled: tslk, mlk1-0 and llk15-0 can be written. tslk test/shadow address space block lock this bit is used to lock the block of test and shadow address space from program and erase (erase is any case forbidden for test block). a value of 1 in the tslk register signifies th at the test/shadow sector is locked for program and erase. a value of 0 in the tslk register signifies that the test/shadow sector is available to receive program and erase pulses. the tslk register is not writable once an interlock write is completed until cflash_mcr[done] is set at the completion of the requested operation. likewise, the tslk register is not writable if a high voltage operation is suspended. upon reset, information from the testflash bloc k is loaded into the tslk register. the tslk bit may be written as a register. reset will cause the bit to go back to its testflash block value. the default value of the tslk bit (assuming erased fuses) would be locked. tslk is not writable unless lme is high. 0: test/shadow address space block is unlocked and can be modified (also if cflash_sll[stslk] = 0). 1: test/shadow address space block is locked and cannot be modified. RM0017 flash memory doc id 14629 rev 8 646/904 cflash nonvolatile low/mid address space block locking register (cflash_nvlml) the cflash_lml register has a related cflash nonvolatile low/mid address space block locking register located in testflash that contains the default reset value for cflash_lml. during the reset phase of the flash memory module, the cflash_nvlml register content is read and loaded into the cflash_lml. mlk mid address space block lock this field is used to lock the blocks of mid address space from program and erase. mlk is related to sector s b0f7-6, respectively. a value of 1 in a bit of the mlk field signifies that the corresponding block is locked for program and erase. a value of 0 in a bit of the mlk field signifies that the corresponding block is available to receive program and erase pulses. the mlk field is not writable after an interlock write is completed until cflash_mcr[done] is set at the completion of the requested operation. likewise, the mlk field is not writable if a high voltage operation is suspended. upon reset, information from the testflash bloc k is loaded into the mlk field. the mlk field may be written as a register. reset will cause the bits to go back to their testflash block value. the default value of the mlk field (assuming erased fuses) would be locked. in the event that blocks are not present (due to configuration or total memory size), the mlk field will default to locked, and will not be writable. the reset value will always be 1 (independent of the testflash block), and register writes will have no effect. mlk is not writable unless lme is high. 0: mid address space block is unlocked and can be modified (also if cflash_sll[smlk] = 0). 1: mid address space block is locked and cannot be modified. llk low address space block lock this field is used to lock the blocks of low address space from program and erase. llk[5:0] are related to sectors b0f5-0, respecti vely. llk[15:6] are not used for this memory cut. a value of 1 in a bit of the llk field signifies that the corresponding block is locked for program and erase. a value of 0 in a bit of the llk field signifies that the corresponding block is available to receive program and erase pulses. the llk field is not writable after an interlock write is completed until cflash_mcr[done] is set at the completion of the requested operation. likewise, the llk field is not writable if a high voltage operation is suspended. upon reset, information from the testflash block is loaded into the llk field. the llk field may be written as a register. reset will cause the field to go back to its testflash block value. the default value of the llk field (assuming erased fuses) would be locked. in the event that blocks are not present (due to configuration or total memory size), the llk field will default to locked, and will not be writable. the reset value will always be 1 (independent of the testflash block), and register writes will have no effect. bits llk[15:6] are read-only and locked at ?1?. llk is not writable unless lme is high. 0: low address space block is unlocked and ca n be modified (also if cflash_sll[slk] = 0). 1: low address space block is locked and cannot be modified. table 329. cflash_lml fiel d descriptions (continued) field description flash memory RM0017 647/904 doc id 14629 rev 8 the cflash_nvlml register is a 64-bit register , of which the 32 most significant bits 63:32 are ?don?t care? and are used to manage ecc codes. figure 350. cflash nonvolatile low/mid address space block locking register (cflash_nvlml) offset: 0x403de8 access: read/write 0123456789101112131415 rlme1111111111 tslk 11 mlk w reset1111111111111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r1111111111 llk w reset1111111111111111 table 330. cflash_nvlml field descriptions field description lme low/mid address space block enable this bit is used to enable the lock registers (tslk, mlk1-0 and llk15-0) to be set or cleared by registers writes. this bit is a status bit only. the method to set this bit is to write a password, and if the password matches, the lme bit will be set to re flect the status of enabled, and is enabled until a reset operation occurs. for lme the password 0xa1a11111 must be written to the cflash_lml register. 0 low address locks are disabled: tslk, mlk1-0 and llk15-0 cannot be written. 1 low address locks are enabled: tslk, mlk1-0 and llk15-0 can be written. tslk test/shadow address space block lock this bit is used to lock the block of test and shadow address space from program and erase (erase is any case forbidden for test block). a value of 1 in the tslk register signifies th at the test/shadow sector is locked for program and erase. a value of 0 in the tslk register signifies that the test/shadow sector is available to receive program and erase pulses. the tslk register is not writable once an interlock write is completed until cflash_mcr[done] is set at the completion of the requested operation. likewise, the tslk register is not writable if a high voltage operation is suspended. upon reset, information from the testflash bloc k is loaded into the tslk register. the tslk bit may be written as a register. reset will cause the bit to go back to its testflash block value. the default value of the tslk bit (assuming erased fuses) would be locked. tslk is not writable unless lme is high. 0: test/shadow address space block is unlocked and can be modified (also if cflash_sll[stslk] = 0). 1: test/shadow address space block is locked and cannot be modified. RM0017 flash memory doc id 14629 rev 8 648/904 cflash secondary low/mid address space block locking register (cflash_sll) the cflash secondary low/mid address space block locking register provides an alternative means to protect blocks from being modified. these bits, along with bits in the cflash_lml register, determine if the block is locked from program or erase. an ?or? of cflash_lml and cflash_sll determine the final lock status. mlk mid address space block lock these bits are used to lock the blocks of mid address space from program and erase. mlk[1:0] are related to se ctors b0f7-6, respectively. a value of 1 in a bit of the mlk register signifies that the corresponding block is locked for program and erase. a value of 0 in a bit of the mlk register signif ies that the corresponding block is available to receive program and erase pulses. the mlk register is not writable once an interlock write is completed until cflash_mcr[done] is set at the completion of the requested operation. likewise, the mlk register is not writable if a high voltage operation is suspended. upon reset, information from the testflash bloc k is loaded into the mlk registers. the mlk bits may be written as a register. reset will caus e the bits to go back to their testflash block value. the default value of the mlk bits (assuming erased fuses) would be locked. in the event that blocks are not present (due to configuration or total memory size), the mlk bits will default to locked, and will not be writable. the reset value will always be 1 (independent of the testflash block), and register writes will have no effect. mlk is not writable unless lme is high. 0: mid address space block is unlocked and can be modified (also if cflash_sll[smlk] = 0). 1: mid address space block is locked and cannot be modified. llk low address space block lock these bits are used to lock the blocks of low address space from program and erase. llk[5:0] are related to sectors b0f5-0, respecti vely. llk[15:6] are not used for this memory cut. a value of 1 in a bit of the llk register signi fies that the corresponding block is locked for program and erase. a value of 0 in a bit of the llk register signifi es that the corresponding block is available to receive program and erase pulses. the llk register is not writable once an interlock write is completed until cflash_mcr[done] is set at the completion of the requested operation. likewise, the llk register is not writable if a high voltage operation is suspended. upon reset, information from the testflash bl ock is loaded into the llk registers. the llk bits may be written as a register. reset will caus e the bits to go back to their testflash block value. the default value of the llk bits (assuming erased fuses) would be locked. in the event that blocks are not present (due to configuration or total memory size), the llk bits will default to locked, and will not be writable. the reset value will always be 1 (independent of the testflash block), and register writes will have no effect. bits llk[15:6] are read-only and locked at ?1?. llk is not writable unless lme is high. 0: low address space block is unlocked and ca n be modified (also if cflash_sll[slk] = 0). 1: low address space block is locked and cannot be modified. table 330. cflash_nvlml field descriptions (continued) field description flash memory RM0017 649/904 doc id 14629 rev 8 figure 351. cflash secondary low/mid address space block locking register (cflash_sll) offset: 0x000c access: read/write 0123456789101112131415 rsle0000000000 stslk 00 smk w reset defined by cflash_nvsll at cflash test sector address 0x403df8. this location is user otp (one time programmable). the cflash_nvsll register in fluences only the r/w bits of the cflash_sll register. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000 slk w reset defined by cflash_nvsll at cflash test sector address 0x403df8. this location is user otp (one time programmable). the cflash_nvsll register in fluences only the r/w bits of the cflash_sll register. table 331. cflash_sll field descriptions field description sle secondary low/mid address space block enable this bit is used to enable the lock register s (stslk, smk1-0 and slk15-0) to be set or cleared by registers writes. this bit is a status bit only. the method to set this bit is to write a password, and if the password matches, the sle bit will be set to reflect the status of enabled, and is enabled until a reset operation occurs. for sle the password 0xc3c33333 must be written to the cflash_sll register. 0: secondary low/mid address locks are di sabled: stslk, smk1-0 and slk15-0 cannot be written. 1: secondary low/mid address locks are en abled: stslk, smk1-0 and slk15-0 can be written. stslk secondary test/shadow address space block lock this bit is used as an alternate means to lo ck the block of test and shadow address space from program and erase (erase is any case forbidden for test block). a value of 1 in the stslk regi ster signifies that the test /shadow sector is locked for program and erase. a value of 0 in the stslk regi ster signifies that the test/s hadow sector is available to receive program and erase pulses. the stslk register is not writable once an interlock write is completed until cflash_mcr[done] is set at the completion of the requested operation. likewise, the stslk register is not writable if a high voltage operation is suspended. upon reset, information from the testflash block is loaded into the stslk register. the stslk bit may be written as a register. reset will cause the bit to go back to its testflash block value. the default value of the stslk bit (assuming erased fuses) would be locked. stslk is not writable unless sle is high. 0: test/shadow address space block is unlocked and can be modified (also if cflash_lml[tslk] = 0). 1: test/shadow address space block is locked and cannot be modified. RM0017 flash memory doc id 14629 rev 8 650/904 smk secondary mid address space block lock these bits are used as an alternate means to lock the blocks of mid address space from program and erase. smk[1:0] are related to sectors b0f7-6, respectively. a value of 1 in a bit of the smk register signi fies that the corresponding block is locked for program and erase. a value of 0 in a bit of the smk register signif ies that the corresponding block is available to receive program and erase pulses. the smk register is not writable once an interlock write is completed until cflash_mcr[done] is set at the completion of the requested operation. likewise, the smk register is not writable if a high voltage operation is suspended. upon reset, information from the testflash block is loaded into the smk registers. the smk bits may be written as a register. reset will caus e the bits to go back to their testflash block value. the default value of the smk bits (assuming erased fuses) would be locked. in the event that blocks are not present (due to configuration or total memory size), the smk bits will default to locked, and will not be writable. the reset value will always be 1 (independent of the testflash block), and register writes will have no effect. smk is not writable unless sle is high. 0: mid address space block is unlocked and can be modified (also if cflash_lml[mlk] = 0). 1: mid address space block is locked and cannot be modified. slk secondary low address space block lock these bits are used as an alternate means to lock the blocks of low address space from program and erase. slk[5:0] are related to sectors b0f5-0, respectively. slk[15:6] are not used for this memory cut. a value of 1 in a bit of the slk register signifies that the corresponding block is locked for program and erase. a value of 0 in a bit of the slk register signifies that the corresponding block is available to receive program and erase pulses. the slk register is not writable once an interlock write is completed until cflash_mcr[done] is set at the completion of the requested operation. likewise, the slk register is not writable if a high voltage operation is suspended. upon reset, information from the testflash block is loaded into the slk registers. the slk bits may be written as a register. reset will caus e the bits to go back to their testflash block value. the default value of the slk bits (assuming erased fuses) would be locked. in the event that blocks are not present (due to configuration or total memory size), the slk bits will default to locked, and will not be writable. the reset value will always be 1 (independent of the testflash block), and register writes will have no effect. bits slk[15:6] are read-only and locked at ?1?. slk is not writable unless sle is high. 0: low address space block is unlocked and can be modified (also if cflash_lml[llk] = 0). 1: low address space block is locked and cannot be modified. table 331. cflash_sll field descriptions (continued) field description flash memory RM0017 651/904 doc id 14629 rev 8 cflash nonvolatile secondary low/mid address space block locking register (cflash_nvsll) the cflash_sll register has a related nonvolatile secondary low/mid address space block locking register located in testflash that contains the default reset value for sll. during the reset phase of the flash memory module, the cflash_nvsll register content is read and loaded into the cflash_sll. the cflash_nvsll register is a 64-bit register, of which the 32 most significant bits 63:32 are ?don?t care? and are used to manage ecc codes. figure 352. cflash nonvolatile secondary low /mid address space block locking register (cflash_nvsll) offset: 0x403df8 access: read/write 0123456789101112131415 rsle1111111111 stslk 11 smk w reset1111111111111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r1111111111 slk w reset1111111111111111 RM0017 flash memory doc id 14629 rev 8 652/904 table 332. cflash_nvsll field descriptions field description sle secondary low/mid address space block enable this bit is used to enable the lock register s (stslk, smk1-0 and slk15-0) to be set or cleared by registers writes. this bit is a status bit only. the method to set this bit is to write a password, and if the password matches, the sle bit will be set to reflect the status of enabled, and is enabled until a reset operation occurs. for sle the password 0xc3c33333 must be written to the cflash_sll register. 0: secondary low/mid address locks are di sabled: stslk, smk1-0 and slk15-0 cannot be written. 1: secondary low/mid address locks are en abled: stslk, smk1-0 and slk15-0 can be written. stslk secondary test/shadow address space block lock this bit is used as an alternate means to lo ck the block of test and shadow address space from program and erase (erase is any case forbidden for test block). a value of 1 in the stslk regi ster signifies that the test /shadow sector is locked for program and erase. a value of 0 in the stslk regi ster signifies that the test/s hadow sector is available to receive program and erase pulses. the stslk register is not writable once an interlock write is completed until cflash_mcr[done] is set at the completion of the requested operation. likewise, the stslk register is not writable if a high voltage operation is suspended. upon reset, information from the testflash block is loaded into the stslk register. the stslk bit may be written as a register. reset will cause the bit to go back to its testflash block value. the default value of the stslk bit (assuming erased fuses) would be locked. stslk is not writable unless sle is high. 0: test/shadow address space block is unlocked and can be modified (also if cflash_lml[tslk] = 0). 1: test/shadow address space block is locked and cannot be modified. flash memory RM0017 653/904 doc id 14629 rev 8 smk secondary mid address space block lock these bits are used as an alternate means to lock the blocks of mid address space from program and erase. smk[1:0] are related to sectors b0f7-6, respectively. a value of 1 in a bit of the smk register signi fies that the corresponding block is locked for program and erase. a value of 0 in a bit of the smk register signif ies that the corresponding block is available to receive program and erase pulses. the smk register is not writable once an interlock write is completed until cflash_mcr[done] is set at the completion of the requested operation. likewise, the smk register is not writable if a high voltage operation is suspended. upon reset, information from the testflash block is loaded into the smk registers. the smk bits may be written as a register. reset will caus e the bits to go back to their testflash block value. the default value of the smk bits (assuming erased fuses) would be locked. in the event that blocks are not present (due to configuration or total memory size), the smk bits will default to locked, and will not be writable. the reset value will always be 1 (independent of the testflash block), and register writes will have no effect. smk is not writable unless sle is high. 0: mid address space block is unlocked and can be modified (also if cflash_lml[mlk] = 0). 1: mid address space block is locked and cannot be modified. slk secondary low address space block lock these bits are used as an alternate means to lock the blocks of low address space from program and erase. slk[5:0] are related to sectors b0f5-0, respectively. slk[15:6] are not used for this memory cut. a value of 1 in a bit of the slk register signifies that the corresponding block is locked for program and erase. a value of 0 in a bit of the slk register signifies that the corresponding block is available to receive program and erase pulses. the slk register is not writable once an interlock write is completed until cflash_mcr[done] is set at the completion of the requested operation. likewise, the slk register is not writable if a high voltage operation is suspended. upon reset, information from the testflash block is loaded into the slk registers. the slk bits may be written as a register. reset will caus e the bits to go back to their testflash block value. the default value of the slk bits (assuming erased fuses) would be locked. in the event that blocks are not present (due to configuration or total memory size), the slk bits will default to locked, and will not be writable. the reset value will always be 1 (independent of the testflash block), and register writes will have no effect. bits slk[15:6] are read-only and locked at ?1?. slk is not writable unless sle is high. 0: low address space block is unlocked and can be modified (also if cflash_lml[llk] = 0). 1: low address space block is locked and cannot be modified. table 332. cflash_nvsll fiel d descriptions (continued) field description RM0017 flash memory doc id 14629 rev 8 654/904 cflash low/mid address space block select register (cflash_lms) the cflash_lms register provides a means to select blocks to be operated on during erase. figure 353. cflash low/mid address sp ace block select register (cflash_lms) offset: 0x00010 access: read/write 0123456789101112131415 r00000000000000 msl w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000 lsl w reset0000000000000000 flash memory RM0017 655/904 doc id 14629 rev 8 cflash address register (cflash_adr) table 333. cflash_lms field descriptions field description msl mid address space block select a value of 1 in the select register signifies that the block is selected for erase. a value of 0 in the select regist er signifies that the block is not selected for erase. the reset value for the select register is 0, or unselected. msl[1:0] are related to se ctors b0f7-6, respectively. the blocks must be selected (or unselected) before doing an erase interlock write as part of the erase sequence. the select r egister is not writable once an interlock write is completed or if a high voltage operation is suspended. in the event that blocks are not present (due to configuration or total memory size), the corresponding msl bits will default to unselected, and will not be writable. the reset value will always be 0, and register writes will have no effect. 0: mid address space block is unselected for erase. 1: mid address space block is selected for erase. lsl low address space block select a value of 1 in the select register signifies that the block is selected for erase. a value of 0 in the select regist er signifies that the block is not selected for erase. the reset value for the select register is 0, or unselected. lsl[5:0] are related to sectors b0f5-0, respectively. lsl[15:6] are not used for this memory cut. the blocks must be selected (or unselected) before doing an erase interlock write as part of the erase sequence. the select r egister is not writable once an interlock write is completed or if a high voltage operation is suspended. in the event that blocks are not present (due to configuration or total memory size), the corresponding lsl bits will default to unselected, and will not be writable. the reset value will always be 0, and register writes will have no effect. bits lsl[15:6] are read-only and locked at ?0?. 0: low address space block is unselected for erase. 1: low address space block is selected for erase. figure 354. cflash address register (cflash_adr) offset: 0x00018 access: read 0123456789101112131415 r 0 0 0 0 0 0 0 0 0 ad22 ad21 ad20 ad19 ad18 ad17 ad16 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 0 0 0 w reset0000000000000000 RM0017 flash memory doc id 14629 rev 8 656/904 the cflash_adr provides the first failing ad dress in the event module failures (ecc or fpec) occur or the first address at which an ecc single error correction occurs. cflash user test 0 register (cflash_ut0) the user test registers provid e the user with the ability to test features on the flash memory module. the user test 0 register allows to control the way in which the flash memory content check is done. bits mre, mrv, ais, eie and dsi[7:0] of the user test 0 register are not accessible whenever cflash_mcr[done] or ut0[aid] are low: reading returns indeterminate data while writing has no effect. table 334. cflash_adr field descriptions field description ad address 22-3 (read only) the address register provides the first failing address in the event of ecc error (cflash_mcr[eer] = 1) or the first failing address in the event of rww error (cflash_mcr[rwe] = 1), or the address of a failure that may have occurred in a fpec operation (cflash_mcr[peg] = 0). the address register also provides the first address at which an ecc single error correction occurs (cflash_mcr[edc] = 1). the ecc double error detection takes the highest priority, followed by the fpec error and the ecc single error correction. when ac cessed cflash_adr will provide the address related to the first event occurred with the highest priority. the priorities between these four possible events is summarized in ta bl e 3 3 5 . this address is always a double word address that selects 64 bits. in case of a simultaneous ecc double error detection on both double words of the same page, bit ad3 will output 0. the same is valid for a simultaneous ecc single error correction on both double words of the same page. table 335. cflash_adr content: priority list priority level error flag cflash_adr content 1 cflash_mcr[eer] = 1 address of first ecc double error 2 cflash_mcr[rwe] = 1 address of first rww error 3 cflash_mcr[peg] = 0 address of first fpec error 4 cflash_mcr[edc] = 1 address of fi rst ecc single error correction flash memory RM0017 657/904 doc id 14629 rev 8 figure 355. cflash user test 0 register (cflash_ut0) offset: 0x0003c access: read/write 0123456789101112131415 rute0000000 dsi ww1c reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000 x mre mrv eie ais aie aid w reset0000000000000001 table 336. cflash_ut0 field descriptions field description ute user test enable this status bit gives indication when user te st is enabled. all bits in cflash_ut0-2 and cflash_umisr0-4 are locked when this bit is 0. the method to set this bit is to provide a password, and if the password matches, the ute bit is set to reflect the status of enabled, and is enabled until it is cleared by a register write. for ute the password 0xf9f99999 must be written to the cflash_ut0 register. dsi data syndrome input these bits represent the input of syndrome bi ts of ecc logic used in the ecc logic check. bits dsi[7:0] correspond to the 8 syndrome bits on a double word. these bits are not accessible whenever cf lash_mcr[done] or cflash_ut0[aid] are low: reading returns indeterminate data while writing has no effect. 0: the syndrome bit is forced at 0. 1: the syndrome bit is forced at 1. x reserved this bit can be written and its value can be r ead back, but there is no function associated. this bit is not accessible whenever cflash_mcr[done] or cflash_ut0[aid] are low: reading returns indeterminate data while writing has no effect. mre margin read enable mre enables margin reads to be done. this bit, combined with mrv, enables regular user mode reads to be replaced by margin reads inside the array integrity checks sequences. margin reads are only active during array integrity checks; normal user reads are not affected by mre. this bit is not accessible whenever cflash_mcr[done] or cflash_ut0[aid] are low: reading returns indeterminate data while writing has no effect. 0: margin reads are not enabled 1: margin reads are enabled. RM0017 flash memory doc id 14629 rev 8 658/904 cflash user test 1 register (cflash_ut1) the cflash_ut1 register allows to enable the checks on the ecc logic related to the 32 lsb of the double word. the user test 1 register is not acce ssible whenever cf lash_mcr[done] or cflash_ut0[aid] are low: reading returns inde terminate data while writing has no effect. mrv margin read value if mre is high, mrv selects the margin level that is being checked. margin can be checked to an erased level (mrv = 1) or to a programmed level (mrv = 0). this bit is not accessible whenever cflash_mcr[done] or cflash_ut0[aid] are low: reading returns indeterminate data while writing has no effect. 0: zero?s (programmed) margin reads are requested (if mre = 1). 1: one?s (erased) margin reads are requested (if mre = 1). eie ecc data input enable eie enables the ecc logic check operation to be done. this bit is not accessible whenever cflash_mcr[done] or cflash_ut0[aid] are low: reading returns indeterminate data while writing has no effect. 0: ecc logic check is not enabled. 1: ecc logic check is enabled. ais array integrity sequence ais determines the address sequence to be us ed during array integrity checks or margin read . the default sequence (ais=0) is meant to replicate sequences normal user code follows, and thoroughly checks the read propagation paths. this sequence is proprietary. the alternative sequence (ais=1) is just logica lly sequential. it should be noted that the time to run a sequential sequence is significantly shorter than the time to run the proprietary sequence. the usage of proprietary sequence is forbidden in margin read. this bit is not accessible whenever cflash_mcr[done] or cflash_ut0[aid] are low: reading returns indeterminate data while writing has no effect. 0: array integrity sequence is proprietary sequence. 1: array integrity or f sequence is sequential. aie array integrity enable aie set to ?1? starts the array integrity check done on all selected and unlocked blocks. the pattern is selected by ais, and the mi sr (cflash_umisr0-4) can be checked after the operation is complete, to determi ne if a correct signature is obtained. aie can be set only if cflash _mcr[ers], cflash _mcr[pgm] and cflash_mcr[ehv] are all low. 0: array integrity checks, margin read and ecc logic checks are not enabled. 1: array integrity checks, margin read and ecc logic checks are enabled. aid array integrity done aid will be cleared upon an array integrity chec k being enabled (to signify the operation is on-going). once completed, aid will be set to indicate that the array in tegrity check is complete. at this time the misr (cflash_umisr0-4) can be checked. 0: array integrity check is on-going. 1: array integrity check is done. table 336. cflash_ut0 fiel d descriptions (continued) field description flash memory RM0017 659/904 doc id 14629 rev 8 cflash user test 2 register (cflash_ut2) the cflash_ut2 register allows to enable the checks on the ecc logic related to the 32 msb of the double word. the user test 2 register is not acce ssible whenever cf lash_mcr[done] or cflash_ut0[aid] are low: reading returns inde terminate data while writing has no effect. figure 356. cflash user test 1 register (cflash_ut1) offset: 0x00040 access: read/write 0123456789101112131415 r dai[31:16] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dai[15:0] w reset0000000000000000 table 337. cflash_ut1 field descriptions field description dai[31:0] data array input, bits 31?0 these bits represent the input of even word of ecc logic used in the ecc logic check. bits dai[31:00] correspond to the 32 array bits representing word 0 within the double word. 0: the array bit is forced at 0. 1: the array bit is forced at 1. figure 357. cflash user test 2 register (cflash_ut2) offset: 0x00044 access: read/write 0123456789101112131415 r dai[63:48] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dai[47:32] w reset0000000000000000 RM0017 flash memory doc id 14629 rev 8 660/904 cflash user multiple input signature register 0 (cflash_umisr0) the cflash_umisr0 register provides a mean to evaluate the array integrity. the user multiple input signature register 0 represents the bits 31:0 of the whole 144 bits word (2 double words including ecc). the cflash_umisr0 register is not acce ssible whenever cflash_mcr[done] or cflash_ut0[aid] are low: reading returns inde terminate data while writing has no effect. cflash user multiple input signature register 1 (cflash_umisr1) the cflash_umisr1 provides a means to evaluate the array integrity. the cflash_umisr1 represents the bits 63:32 of the whole 144 bits word (2 double words including ecc). table 338. cflash_ut2 field descriptions field description dai[63:32] data array input, bits 63?32 these bits represent the input of odd word of ecc logic used in the ecc logic check. bits dai[63:32] correspond to the 32 array bits representing word 1 within the double word. 0: the array bit is forced at 0. 1: the array bit is forced at 1. figure 358. cflash user multiple input signature register 0 (cflash_umisr0) offset: 0x00048 access: read/write 0123456789101112131415 r ms0[31:16] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ms0[15:0] w reset0000000000000000 table 339. cflash_umisr 0 field descriptions field description ms0[31:0] multiple input signature, bits 31?0 these bits represent the misr value obtained accumulating the bits 31:0 of all the pages read from the flash memory. the ms can be seeded to any value by writing the cflash_umisr0 register. flash memory RM0017 661/904 doc id 14629 rev 8 the cflash_umisr1 is not accessible whenever cflash_mcr[done] or cflash_ut0[aid] are low: reading returns inde terminate data while writing has no effect. cflash user multiple input signature register 2 (cflash_umisr2) the cflash_umisr2 provides a means to evaluate the array integrity. the cflash_umisr2 represents the bits 95:64 of the whole 144 bits word (2 double words including ecc). the cflash_umisr2 is not accessible whenever cflash_mcr[done] or cflash_ut0[aid] are low: reading returns inde terminate data while writing has no effect. figure 359. cflash user multiple input signature register 1 (cflash_umisr1) offset: 0x0004c access: read/write 0123456789101112131415 r ms0[63:48] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ms0[47:32] w reset0000000000000000 table 340. cflash_umisr 1 field descriptions field description ms0[63:32] multiple input signature, bits 63?32 these bits represent the misr value obtained accumulating the bits 63:32 of all the pages read from the flash memory. the ms can be seeded to any value by writing the cflash_umisr1. RM0017 flash memory doc id 14629 rev 8 662/904 cflash user multiple input signature register 3 (cflash_umisr3) the cflash_umisr3 provides a mean to evaluate the array integrity. the cflash_umisr3 represents the bits 127:96 of the whole 144 bits word (2 double words including ecc). the cflash_umisr3 is not accessible whenever cflash_mcr[done] or cflash_ut0[aid] are low: reading returns inde terminate data while writing has no effect. figure 360. cflash user multiple input signature register 2 (cflash_umisr2) offset: 0x00050 access: read/write 0123456789101112131415 r ms0[95:80] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ms0[79:64] w reset0000000000000000 table 341. cflash_umisr 2 field descriptions field description ms0[95:64] multiple input signature, bits 95?64 these bits represent the misr value obtained accumulating the bits 95:64 of all the pages read from the flash memory. the ms can be seeded to any value by writing the cflash_umisr2. flash memory RM0017 663/904 doc id 14629 rev 8 cflash user multiple input signature register 4 (cflash_umisr4) the cflash_umisr4 provides a mean to evaluate the array integrity. the cflash_umisr4 represents the ecc bits of the whole 144 bits word (2 double words including ecc): bits 8:15 are ecc bits for the odd double word and bits 24:31 are the ecc bits for the even double word; bits 4:5 and 20:21 of misr are respectively the double and single ecc error detection for odd and even double word. the cflash_umisr4 is not accessible whenever cflash_mcr[done] or cflash_ut0[aid] are low: reading returns inde terminate data while writing has no effect. figure 361. cflash user multiple input signature register 3 (cflash_umisr3) offset: 0x00054 access: read/write 0123456789101112131415 r ms[127:112] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ms[111:96] w reset0000000000000000 table 342. cflash_umisr 3 field descriptions field description ms[127:96] multiple input signature, bits127?96 these bits represent the misr value obtained accumulating the bits 127:96 of all the pages read from the flash memory. the ms can be seeded to any value by writing the cflash_umisr3. RM0017 flash memory doc id 14629 rev 8 664/904 cflash nonvolatile private censorship password 0 register (nvpwd0) the nonvolatile private censorship password 0 register contains the 32 lsb of the password used to validate the censorship inform ation contained in nvscc0?1 registers. figure 362. cflash user multiple input signature register 4 (cflash_umisr4) offset: 0x00058 access: read/write 0123456789101112131415 r ms[159:144] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ms[143:128] w reset0000000000000000 table 343. cflash_umisr 4 field descriptions field description ms[159:128] multiple input signature, bits 159?128 these bits represent the misr value obtained accumulating: the 8 ecc bits for the even double word (on ms[135:128]); the single ecc error detection for even double word (on ms138); the double ecc error detection for even double word (on ms139); the 8 ecc bits for the odd double word (on ms[151:144]); the single ecc error detection for odd double word (on ms154); the double ecc error detection for odd double word (on ms155). the ms can be seeded to any value by writing the cflash_umisr4 register. flash memory RM0017 665/904 doc id 14629 rev 8 cflash nonvolatile private censorship password 1 register (nvpwd1) the nonvolatile private censorship password 1 register contains the 32 msb of the password used to validate the censorship information contained in nvscc0?1 registers. figure 363. cflash nonvolatile private censorship password 0 register (nvpwd0) offset: 0x203dd8 access: read/write 0123456789101112131415 r pwd[31:16] w reset1111111011101101 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pwd[15:0] w reset1111101011001110 table 344. nvpwd0 field descriptions field description pwd[31:0] password, bits 31?0 these bits represent the 32 lsb of the private censorship password. figure 364. cflash nonvolatile private censorship password 1 register (nvpwd1) offset: 0x203ddc access: read/write 0123456789101112131415 r pwd[63:48] w reset1100101011111110 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pwd[47:32] w reset1011111011101111 RM0017 flash memory doc id 14629 rev 8 666/904 note: in a secured device, starting with a serial boot, it is possible to read the content of the four flash locations where the rchw can be stored. for example if the rchw is stored at address 0x00000000, the reads at address 0x00000000, 0x00000004, 0x00000008 and 0x0000000c will return a correct value. an y other flash address cannot be accessed. cflash nonvolatile system censorship control 0 register (nvscc0) the nvscc0 register stores the 32 lsb of the censorship control word of the device. the nvscc0 is a nonvolatile re gister located in the shadow sector: it is read during the reset phase of the flash memory module and the protection mechanisms are activated consequently. the parts are delivered uncensored to the user. table 345. nvpwd1 field descriptions field description pwd[63:32] password, bits 63?32 these bits represent the 32 msb of the private censorship password. figure 365. cflash nonvolatile system censorship control 0 register (nvscc0) offset: 0x203de0 access: read/write 0123456789101112131415 r sc[15:0] w reset0101010110101010 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cw[15:0] w reset0101010110101010 table 346. nvscc0 field descriptions field description sc[15:0] serial censorship control word, bits 15-0 these bits represent the 16 lsb of the serial censorship control word (sccw). if sc15-0 = 0x55aa and nvscc1 = nvscc0 the public access is disabled. if sc15-0 0x55aa or nvscc1 nvscc0 the public access is enabled. cw[15:0] censorship control word, bits 15-0 these bits represent the 16 lsb of the censorship control word (ccw). if cw15-0 = 0x55aa and nvscc1 = nvscc0 the censored mode is disabled. if cw15-0 0x55aa or nvscc1 nvscc0 the censored mode is enabled. flash memory RM0017 667/904 doc id 14629 rev 8 cflash nonvolatile system censorship control 1 register (nvscc1) the nvscc1 register stores the 32 msb of the censorship control word of the device. the nvscc1 is a nonvolatile re gister located in the shadow sector: it is read during the reset phase of the flash memory module and the protection mechanisms are activated consequently. the parts are delivered uncensored to the user. cflash nonvolatile user options register (nvusro) the nonvolatile user options register contains configuration information for the user application. the nvusro register is a 64-bit register, of which the 32 most significant bits 63:32 are ?don?t care? and are used to manage ecc codes. figure 366. cflash nonvolatile system censorship control 1 register (nvscc1) offset: 0x203de4 access: read/write 0123456789101112131415 r sc[31:16] w reset0101010110101010 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cw[31:16] w reset0101010110101010 table 347. nvscc1 field descriptions field description sc[31:16] serial censorship control word, bits 31-16 these bits represent the 16 msb of the serial censorship control word (sccw). if sc15-0 = 0x55aa and nvscc1 = nvscc0 the public access is disabled. if sc15-0 0x55aa or nvscc1 nvscc0 the public access is enabled. cw[31:16] censorship control word, bits 31-16 these bits represent the 16 msb of the censorship control word (ccw). if cw15-0 = 0x55aa and nvscc1 = nvscc0 the censored mode is disabled. if cw15-0 0x55aa or nvscc1 nvscc0 the censored mode is enabled. RM0017 flash memory doc id 14629 rev 8 668/904 28.5.2 dflash register description dflash module configuration register (dflash_mcr) the module configuration register is used to enable and monitor all modify operations of the flash memory module. figure 367. cflash nonvolatile us er options register (nvusro) offset: 0x203e18 access: read/write 0123456789101112131415 r watchdog_en oscillator_margin pa d 3 v 5 v 1111111111111 w reset1111111111111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r1111111111111111 w reset1111111111111111 table 348. nvusro field descriptions field description watchdog_en watchdog_en 0: disable after reset 1: enable after reset default manufacturing value before flash memory initialization is ?1? oscillator_ margin oscillator_margin 0: low consumption conf iguration (4 mhz/8 mhz) 1: high margin config uration (4 mhz/16 mhz) default manufacturing value before flash memory initialization is ?1? pa d 3 v 5 v pa d 3 v 5 v 0: high voltage supply is 5.0 v 1: high voltage supply is 3.3 v default manufacturing value before flash memory initialization is ?1? (3.3 v) which should ensure correct minimum slope for boundary scan. flash memory RM0017 669/904 doc id 14629 rev 8 figure 368. dflash module configuration register (dflash_mcr) address offset: 0x0000 access: read/write 0123456789101112131415 redc0000 size 0 las 000mas ww1c reset0000011001100000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eer rwe 0 0 peas done peg0000 pgm psus ers esus ehv ww1c w1c reset0000011000000000 table 349. dflash_mcr field descriptions field description edc ecc data correction edc provides information on previous reads. if an ecc single error detection and correction occurred, the edc bit is set to ?1?. th is bit must then be cleared, or a reset must occur before this bit will return to a 0 state. this bit may not be set to ?1? by the user. in the event of an ecc double error detection, this bit will not be set. if edc is not set, or remains 0, this indicates that all previous reads (from the last reset, or clearing of edc) were not corrected through ecc. the function of this bit is device depend ent and it can be configured to be disabled. 0: reads are occurring normally. 1: an ecc single error occurred and was corrected during a previous read. size array space size the value of size field is dependent upon th e size of the flash memory module; see ta bl e 3 5 0 . las low address space the value of the las field corresponds to the configuration of the low address space; see ta bl e 3 5 1 . mas mid address space the value of the mas field corresponds to the configuration of the mid address space; see ta bl e 3 5 2 . eer ecc event error eer provides information on previous reads. if an ecc double error detection occurred, the eer bit is set to ?1?. this bit must then be cleared, or a reset must occur before this bit will return to a 0 state. this bit may not be set to ?1? by the user. in the event of an ecc single error detection and correction, this bit will not be set. if eer is not set, or remains 0, this indicates th at all previous reads (from the last reset, or clearing of eer) were correct. 0: reads are occurring normally. 1: an ecc double error occurred during a previous read. RM0017 flash memory doc id 14629 rev 8 670/904 rwe read-while-write event error rwe provides information on previous reads when a modify operation is on going. if a rww error occurs, the rwe bit will be set to ?1 ?. read-while-write erro r means that a read access to the flash memory matrix has occurred while the fpec was performing a program or erase operation or an array integrity check. this bit must then be cleared, or a reset must occur before this bit will return to a 0 state. this bit may not be set to ?1? by the user. if rwe is not set, or remains 0, this indicates that all previous rww reads (from the last reset, or clearing of rwe) were correct. 0: reads are occurring normally. 1: a rww error occurred during a previous read. peas program/erase access space peas is used to indicate which space is valid for program and erase operations: main array space or shadow/test space. peas = 0 indicates that the main address space is active for all flash memory module program and erase operations. peas = 1 indicates that the test or shadow address space is active for program and erase. the value in peas is captured and held with the first interlock write done for modify operations. the va lue of peas is retained between sampling events (that is, subsequent first interlock writes). 0: shadow/test address space is disabled for program/erase and main address space enabled. 1: shadow/test address space is enabled for program/erase and main address space disabled. done modify operation done done indicates if the flash memory mo dule is performing a high voltage operation. done is set to 1 on termination of the flash memory module reset. done is cleared to 0 just after a 0 to 1 tran sition of ehv, which initiates a high voltage operation, or after resuming a suspended operation. done is set to 1 at the end of prog ram and erase high voltage sequences. done is set to 1 (within t pabt or t eabt , equal to p/e abort latency) after a 1 to 0 transition of ehv, which aborts a high voltage program/erase operation. done is set to 1 (within t esus , time equals to erase suspend latency) after a 0 to 1 transition of esus, which suspends an erase operation. 0: flash memory is executing a high voltage operation. 1: flash memory is not executing a high voltage operation. table 349. dflash_mcr field descriptions (continued) field description flash memory RM0017 671/904 doc id 14629 rev 8 peg program/erase good the peg bit indicates the completion status of the last flash memory program or erase sequence for which high voltage operations we re initiated. the value of peg is updated automatically during the program and erase high voltage operations. aborting a program/erase high voltage operation will cause peg to be cleared to ?0?, indicating the sequence failed. peg is set to ?1? when the flash memory module is reset, unless a flash memory initialization error has been detected. the value of peg is valid only when pgm = 1 and/or ers = 1 and after done transitions from 0 to 1 due to an abort or the completion of a program/erase operation. peg is valid until pgm/ers makes a 1 to 0 transition or ehv makes a 0 to 1 transition. the value in peg is not valid after a 0 to 1 tr ansition of done caused by esus being set to logic 1. if program or erase are attempted on blocks that are locked, the response will be peg = 1, indicating that the operation was successful, and the content of the block were properly protected from the program or erase operation. if a program operation tries to program at ?1? bi ts that are at ?0?, t he program operation is correctly executed on the new bits to be progra mmed at ?0?, but peg is cleared, indicating that the requested operation has failed. in array integrity check or margin read peg is set to 1 when the operation is completed, regardless the occurrence of any error. the presence of errors can be detected only comparing checksum value stored in umirs0-1. aborting an array integrity check or a margin read operation will cause peg to be cleared to 0, indicating the sequence failed. 0: program, erase operation failed or program, erase, array integrity check or maring mode aborted. 1: program or erase operation succesful or array integrity check or maring mode completed. pgm program pgm is used to set up the flash memory module for a program operation. a 0 to 1 transition of pgm initiates a program sequence. a 1 to 0 transition of pgm ends the program sequence. pgm can be set only under user mode read (ers is low and dflash_ut0[aie] is low). pgm can be cleared by the user only when ehv is low and done is high. pgm is cleared on reset. 0: flash memory is not executing a program sequence. 1: flash memory is executing a program sequence. psus psus: program suspend write this bit has no effect, but the written data can be read back. ers erase ers is used to set up the flash memory module for an erase operation. a 0 to 1 transition of ers initiates an erase sequence. a 1 to 0 transition of ers ends the erase sequence. ers can be set only under user mode read (pgm is low and dflash_ut0[aie] is low). ers can be cleared by the user only when esus and ehv are low and done is high. ers is cleared on reset. 0: flash memory is not executing an erase sequence. 1: flash memory is executing an erase sequence. table 349. dflash_mcr field descriptions (continued) field description RM0017 flash memory doc id 14629 rev 8 672/904 esus erase suspend esus is used to indicate that the flash memory module is in erase suspend or in the process of entering a suspend state. the flas h memory module is in erase suspend when esus = 1 and done = 1. esus can be set high only when ers and ehv are high and pgm is low. a 0 to 1 transition of esus starts the sequ ence which sets done and places the flash memory in erase suspend. the flash memory module enters suspend within t esus of this transition. esus can be cleared only when done and ehv are high and pgm is low. a 1 to 0 transition of esus with ehv = 1 starts the sequence which clears done and returns the module to erase. the flash memory module cannot exit erase suspend and clear done while ehv is low. esus is cleared on reset. 0: erase sequence is not suspended. 1: erase sequence is suspended. ehv enable high voltage the ehv bit enables the flash memory module for a high voltage program/erase operation. ehv is cleared on reset. ehv must be set after an interlock write to start a program/erase sequence. ehv may be set under one of the following conditions: erase (ers = 1, esus = 0, dflash_ut0[aie] = 0) program (ers = 0, esus = 0, pgm = 1, dflash_ut0[aie] = 0) in normal operation, a 1 to 0 transition of ehv with done high and esus low terminates the current program/erase high voltage operation. when an operation is aborted, there is a 1 to 0 transition of ehv with done low and the eventual suspend bit low. an abort causes the value of peg to be cleared, indicating a failing program/erase; address locations being operated on by the aborted operation contain indeterminate data after an abort. a susp ended operation cannot be aborted. aborting a high voltage operation will leave the flash memory module addresses in an indeterminate data state. this may be recovere d by executing an erase on the affected blocks. ehv may be written during suspend. ehv must be high to exit suspend. ehv may not be written after esus is set and before done transitions high. ehv may not be cleared after esus is cleared and before done transitions low. 0: flash memory is not enabled to perform an high voltage operation. 1: flash memory is enabled to perform an high voltage operation. table 350. array space size size array space size 000 128 kb 001 256 kb 010 512 kb 011 reserved (1024 kb) 100 reserved (1536 kb) 101 reserved (2048 kb) table 349. dflash_mcr field descriptions (continued) field description flash memory RM0017 673/904 doc id 14629 rev 8 a number of dflash_mcr bits are protected against write when another bit, or set of bits, is in a specific state. these write locks are covered on a bit by bit basis in the preceding description, but those locks do not consider the effects of trying to write two or more bits simultaneously. the flash memory module does not allow the user to write bits simultaneously which would put the device into an illegal state. this is implemented through a pr iority mechanism among the bits. the bit changing priorities are detailed in the ta b l e 3 5 3 . if the user attempts to write two or more dflash_mcr bits simultaneously then only the bit with the lowest priority level is written. 110 64 kb 111 reserved table 351. low address space configuration las low address space sectorization 000 reserved 001 reserved 010 32 kb + 2 x 16 kb + 2 x 32 kb + 128 kb 011 reserved 100 reserved 101 reserved 110 4 x 16 kb 111 reserved table 352. mid address space configuration mas mid address space sectorization 0 2 x 128kb 1 reserved table 350. array space size (continued) size array space size table 353. dflash_mcr bits set/clear priority levels priority level dflash_mcr bits 1ers 2pgm 3ehv 4 esus RM0017 flash memory doc id 14629 rev 8 674/904 if stall/abort-while-write is enabled and an erase operation is started on one sector while fetching code from another then the following sequence is executed: cpu is stalled when flash is unavailable peg flag set (stall case) or reset (abort case) interrupt triggered if enabled if stall/abort-while-write is used then application software should ignore the setting of the rwe flag. the rwe flag should be cleared after each hv operation. if stall/abort-while-write is not used the application software should handle rwe error. see section 28.8.10, read-while-write functionality . dflash low/mid address space block locking register (dflash_lml) the dflash low/mid address space block locking register provides a means to protect blocks from being modified. these bits, along with bits in the dflash_sll register, determine if the block is locked from program or erase. an ?or? of dflash_lml and dflash_sll determine the final lock status. figure 369. dflash low/mid address sp ace block locking register (dflash_lml) offset: 0x0004 access: read/write 0123456789101112131415 rlme0000000000 tslk 0000 w reset defined by dflash_nvlml at dflash test sector ad dress 0xc03de8. this location is user otp (one time programmable). the dflash_nvlml register influences only the r/w bits of the dflash_lml register. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000000 llk w reset defined by dflash_nvlml at dflash test sector ad dress 0xc03de8. this location is user otp (one time programmable). the dflash_nvlml register influences only the r/w bits of the dflash_lml register. flash memory RM0017 675/904 doc id 14629 rev 8 table 354. dflash_l ml field descriptions field description lme low/mid address space block enable this bit is used to enable the lock registers (tslk, mlk1-0 and llk15-0) to be set or cleared by registers writes. this bit is a status bit only. the method to set this bit is to write a password, and if the password matches, the lme bit will be set to re flect the status of enabled, and is enabled until a reset operation occurs. for lme the password 0xa1a11111 must be written to the dflash_lml register. 0 low address locks are disabled: tslk, mlk1-0 and llk15-0 cannot be written. 1 low address locks are enabled: tslk, mlk1-0 and llk15-0 can be written. tslk test/shadow address space block lock this bit is used to lock the block of test and shadow address space from program and erase (erase is any case forbidden for test block). a value of 1 in the tslk register signifies th at the test/shadow sector is locked for program and erase. a value of 0 in the tslk register signifies that the test/shadow sector is available to receive program and erase pulses. the tslk register is not writable once an interlock write is completed until dflash_mcr[done] is set at the completion of the requested operation. likewise, the tslk register is not writable if a high voltage operation is suspended. upon reset, information from the testflash bloc k is loaded into the tslk register. the tslk bit may be written as a register. reset will cause the bit to go back to its testflash block value. the default value of the tslk bit (assuming erased fuses) would be locked. tslk is not writable unless lme is high. 0: test/shadow address space block is unlocked and can be modified (also if dflash_sll[stslk] = 0). 1: test/shadow address space block is locked and cannot be modified. llk low address space block lock this field is used to lock the blocks of low address space from program and erase. llk[3:0] are related to sectors b1f3-0, respecti vely. llk[15:4] are not used for this memory cut. a value of 1 in a bit of the llk field signifies that the corresponding block is locked for program and erase. a value of 0 in a bit of the llk field signifies that the corresponding block is available to receive program and erase pulses. the llk field is not writable after an interlock write is completed until dflash_mcr[done] is set at the completion of the requested operation. likewise, the llk field is not writable if a high voltage operation is suspended. upon reset, information from the testflash block is loaded into the llk field. the llk field may be written as a register. reset will cause the field to go back to its testflash block value. the default value of the llk field (assuming erased fuses) would be locked. in the event that blocks are not present (due to configuration or total memory size), the llk field will default to locked, and will not be writable. the reset value will always be 1 (independent of the testflash block), and register writes will have no effect. in the 64 kb flash memory module bits llk [15:4] are read-only and locked at ?1?. llk is not writable unless lme is high. 0: low address space block is unlocked and ca n be modified (also if dflash_sll[slk] = 0). 1: low address space block is locked and cannot be modified. RM0017 flash memory doc id 14629 rev 8 676/904 dflash nonvolatile low/mid address space block locking register (dflash_nvlml) the dflash_lml register has a related nonvolatile low/mid address space block locking register located in testflash that contains the default reset value for dflash_lml. during the reset phase of the flash memory module, the dflash_nvlml register content is read and loaded into the dflash_lml. the dflash_nvlml register is a 64-bit register , of which the 32 most significant bits 63:32 are ?don?t care? and are used to manage ecc codes. figure 370. dflash nonvolatile low/mid address space block locking register (dflash_nvlml) offset: 0xc03de8 access: read/write 0123456789101112131415 rlme1111111111 tslk 1111 w reset1111111111111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r111111111111 llk w reset1111111111111111 flash memory RM0017 677/904 doc id 14629 rev 8 table 355. dflash_nvlml field descriptions field description lme low/mid address space block enable this bit is used to enable the lock registers (tslk, mlk1-0 and llk15-0) to be set or cleared by registers writes. this bit is a status bit only. the method to set this bit is to write a password, and if the password matches, the lme bit will be set to re flect the status of enabled, and is enabled until a reset operation occurs. for lme the password 0xa1a11111 must be written to the dflash_lml register. 0 low address locks are disabled: tslk, mlk1-0 and llk15-0 cannot be written. 1 low address locks are enabled: tslk, mlk1-0 and llk15-0 can be written. tslk test/shadow address space block lock this bit is used to lock the block of test and shadow address space from program and erase (erase is any case forbidden for test block). a value of 1 in the tslk register signifies th at the test/shadow sector is locked for program and erase. a value of 0 in the tslk register signifies that the test/shadow sector is available to receive program and erase pulses. the tslk register is not writable once an interlock write is completed until dflash_mcr[done] is set at the completion of the requested operation. likewise, the tslk register is not writable if a high voltage operation is suspended. upon reset, information from the testflash bloc k is loaded into the tslk register. the tslk bit may be written as a register. reset will cause the bit to go back to its testflash block value. the default value of the tslk bit (assuming erased fuses) would be locked. tslk is not writable unless lme is high. 0: test/shadow address space block is unlocked and can be modified (also if dflash_sll[stslk] = 0). 1: test/shadow address space block is locked and cannot be modified. llk low address space block lock these bits are used to lock the blocks of low address space from program and erase. llk[3:0] are related to sectors b1f3-0, respecti vely. llk[15:4] are not used for this memory cut. a value of 1 in a bit of the llk register signi fies that the corresponding block is locked for program and erase. a value of 0 in a bit of the llk register signifi es that the corresponding block is available to receive program and erase pulses. the llk register is not writable once an interlock write is completed until dflash_mcr[done] is set at the completion of the requested operation. likewise, the llk register is not writable if a high voltage operation is suspended. upon reset, information from the testflash bl ock is loaded into the llk registers. the llk bits may be written as a register. reset will caus e the bits to go back to their testflash block value. the default value of the llk bits (assuming erased fuses) would be locked. in the event that blocks are not present (due to configuration or total memory size), the llk bits will default to locked, and will not be writable. the reset value will always be 1 (independent of the testflash block), and register writes will have no effect. in the 64 kb flash memory module bits llk [15:4] are read-only and locked at ?1?. llk is not writable unless lme is high. 0: low address space block is unlocked and ca n be modified (also if dflash_sll[slk] = 0). 1: low address space block is locked and cannot be modified. RM0017 flash memory doc id 14629 rev 8 678/904 dflash secondary low/mid address space block locking register (dflash_sll) the dflash secondary low/mid address space block locking register provides an alternative means to protect blocks from being modified. these bits, along with bits in the dflash_lml register, determine if the block is locked from program or erase. an ?or? of dflash_lml and dflash_sll determine the final lock status. figure 371. dflash secondary low/mid address space block locking register (dflash_sll) offset: 0x000c access: read/write 0123456789101112131415 rsle0000000000 stslk 0000 w reset defined by dflash_nvsll at dflash test sector address 0xc03df8. this location is user otp (one time programmable). the dflash_nvsll register in fluences only the r/w bits of the dflash_sll register. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000000 slk w reset defined by dflash_nvsll at dflash test sector address 0xc03df8. this location is user otp (one time programmable). the dflash_nvsll register in fluences only the r/w bits of the dflash_sll register. flash memory RM0017 679/904 doc id 14629 rev 8 table 356. dflash_sll field descriptions field description sle secondary low/mid address space block enable this bit is used to enable the lock register s (stslk, smk1-0 and slk15-0) to be set or cleared by registers writes. this bit is a status bit only. the method to set this bit is to write a password, and if the password matches, the sle bit will be set to reflect the status of enabled, and is enabled until a reset operation occurs. for sle the password 0xc3c33333 must be written to the dflash_sll register. 0: secondary low/mid address locks are di sabled: stslk, smk1-0 and slk15-0 cannot be written. 1: secondary low/mid address locks are en abled: stslk, smk1-0 and slk15-0 can be written. stslk secondary test/shadow address space block lock this bit is used as an alternate means to lo ck the block of test and shadow address space from program and erase (erase is any case forbidden for test block). a value of 1 in the stslk regi ster signifies that the test /shadow sector is locked for program and erase. a value of 0 in the stslk regi ster signifies that the test/s hadow sector is available to receive program and erase pulses. the stslk register is not writable once an interlock write is completed until dflash_mcr[done] is set at the completion of the requested operation. likewise, the stslk register is not writable if a high voltage operation is suspended. upon reset, information from the testflash block is loaded into the stslk register. the stslk bit may be written as a register. reset will cause the bit to go back to its testflash block value. the default value of the stslk bit (assuming erased fuses) would be locked. stslk is not writable unless sle is high. 0: test/shadow address space block is unlocked and can be modified (also if dflash_lml[tslk] = 0). 1: test/shadow address space block is locked and cannot be modified. slk secondary low address space block lock these bits are used as an alternate means to lock the blocks of low address space from program and erase. slk[3:0] are related to sectors b1f3-0, respectively. slk[15:4] are not used for this memory cut. a value of 1 in a bit of the slk register signifies that the corresponding block is locked for program and erase. a value of 0 in a bit of the slk register signifies that the corresponding block is available to receive program and erase pulses. the slk register is not writable once an interlock write is completed until dflash_mcr[done] is set at the completion of the requested operation. likewise, the slk register is not writable if a high voltage operation is suspended. upon reset, information from the testflash block is loaded into the slk registers. the slk bits may be written as a register. reset will caus e the bits to go back to their testflash block value. the default value of the slk bits (assuming erased fuses) would be locked. in the event that blocks are not present (due to configuration or total memory size), the slk bits will default to locked, and will not be writable. the reset value will always be 1 (independent of the testflash block), and register writes will have no effect. in the 64 kb flash memory module bits slk[15:4] are read-only and locked at ?1?. slk is not writable unless sle is high. 0: low address space block is unlocked and can be modified (also if dflash_lml[llk] = 0). 1: low address space block is locked and cannot be modified. RM0017 flash memory doc id 14629 rev 8 680/904 dflash nonvolatile secondary low/mid address space block locking register (dflash_nvsll) the dflash_sll register has a related nonvolatile secondary low/mid address space block locking register located in testflash that contains the default reset value for dflash_sll. during the reset phase of the flash memory module, the dflash_nvsll register content is read and loaded into the dflash_sll. the dflash_nvsll register is a 64-bit register, of which the 32 most significant bits 63:32 are ?don?t care? and are used to manage ecc codes. figure 372. dflash nonvolatile secondary low /mid address space block locking register (dflash_nvsll) offset: 0xc03df8 access: read/write 0123456789101112131415 rsle1111111111 stslk 1111 w reset1111111111111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r111111111111 slk w reset1111111111111111 flash memory RM0017 681/904 doc id 14629 rev 8 table 357. dflash_nvsll field descriptions field description sle secondary low/mid address space block enable this bit is used to enable the lock register s (stslk, smk1-0 and slk15-0) to be set or cleared by registers writes. this bit is a status bit only. the method to set this bit is to write a password, and if the password matches, the sle bit will be set to reflect the status of enabled, and is enabled until a reset operation occurs. for sle the password 0xc3c33333 must be written to the dflash_sll register. 0: secondary low/mid address locks are di sabled: stslk, smk1-0 and slk15-0 cannot be written. 1: secondary low/mid address locks are en abled: stslk, smk1-0 and slk15-0 can be written. stslk secondary test/shadow address space block lock this bit is used as an alternate means to lo ck the block of test and shadow address space from program and erase (erase is any case forbidden for test block). a value of 1 in the stslk regi ster signifies that the test /shadow sector is locked for program and erase. a value of 0 in the stslk regi ster signifies that the test/s hadow sector is available to receive program and erase pulses. the stslk register is not writable once an interlock write is completed until dflash_mcr[done] is set at the completion of the requested operation. likewise, the stslk register is not writable if a high voltage operation is suspended. upon reset, information from the testflash block is loaded into the stslk register. the stslk bit may be written as a register. reset will cause the bit to go back to its testflash block value. the default value of the stslk bit (assuming erased fuses) would be locked. stslk is not writable unless sle is high. 0: test/shadow address space block is unlocked and can be modified (also if dflash_lml[tslk] = 0). 1: test/shadow address space block is locked and cannot be modified. slk secondary low address space block lock these bits are used as an alternate means to lock the blocks of low address space from program and erase. slk[3:0] are related to sectors b1f3-0, respectively. slk[15:4] are not used for this memory cut. a value of 1 in a bit of the slk register signifies that the corresponding block is locked for program and erase. a value of 0 in a bit of the slk register signifies that the corresponding block is available to receive program and erase pulses. the slk register is not writable once an interlock write is completed until dflash_mcr[done] is set at the completion of the requested operation. likewise, the slk register is not writable if a high voltage operation is suspended. upon reset, information from the testflash block is loaded into the slk registers. the slk bits may be written as a register. reset will caus e the bits to go back to their testflash block value. the default value of the slk bits (assuming erased fuses) would be locked. in the event that blocks are not present (due to configuration or total memory size), the slk bits will default to locked, and will not be writable. the reset value will always be 1 (independent of the testflash block), and register writes will have no effect. in the 64 kb flash memory module bits slk[15:4] are read-only and locked at ?1?. slk is not writable unless sle is high. 0: low address space block is unlocked and can be modified (also if dflash_lml[llk] = 0). 1: low address space block is locked and cannot be modified. RM0017 flash memory doc id 14629 rev 8 682/904 dflash low/mid address space block select register (dflash_lms) the dflash_lms register provides a means to select blocks to be operated on during erase. dflash address register (dflash_adr) the dflash_adr provides the first failing ad dress in the event module failures (ecc, rww or fpec) occur or the first address at which an ecc single error correction occurs. figure 373. dflash low/mid address space block select register (dflash_lms) offset: 0x00010 access: read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000000 lsl w reset0000000000000000 table 358. dflash_lms field descriptions field description lsl low address space block select a value of 1 in the select register signifi es that the block is selected for erase. a value of 0 in the select register signifies that the block is not selected for erase. the reset value for the select register is 0, or unselected. lsl[3:0] are related to sectors b1f3-0, respectively. lsl[15:4] are not used for this memory cut. the blocks must be selected (or unselected) before doing an erase interlock write as part of the erase sequence. the select register is not writable once an interlock write is completed or if a high voltage operation is suspended. in the event that blocks are not present (due to configuration or total memory size), the corresponding lsl bits will default to unselected, and will not be writable. the reset value will always be 0, and register writes will have no effect. in the 80 kb flash memory module bits ls l[15:4] are read-only and locked at ?0?. 0: low address space block is unselected for erase. 1: low address space block is selected for erase. flash memory RM0017 683/904 doc id 14629 rev 8 dflash user test 0 register (dflash_ut0) the user test registers provid e the user with the ability to test features on the flash memory module. figure 374. dflash address register (dflash_adr) address offset: 0x00018 access: read 0123456789101112131415 r 0 0 0 0 0 0 0 0 0 ad22 ad21 ad20 ad19 ad18 ad17 ad16 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 0 0 0 w reset0000000000000000 table 359. dflash_adr field descriptions field description ad[22:3] address 22-3 the address register provides the first failing address in the event of ecc error (dflash_mcr[eer] set) or the first failin g address in the event of rww error (dflash_mcr[rwe] set), or the address of a failure that may have occurred in a fpec operation (dflash_mcr[peg] cleared). the address register also provides the first address at which an ecc single error correction occurs (dflash_mcr[edc] set), if the device is configured to show this feature. the ecc double error detection takes the highest priority, followed by the rww error, the fpec error and the ecc single error correction. when accessed dflash_adr will provide the address related to the first event occurred with the highest priority. the priorities between these four possible events is summarized in the ta b l e 3 6 0 . this address is always a double word address that selects 64 bits. in case of a simultaneous ecc double error detection on both double words of the same page, bit ad3 will output 0. the same is valid for a simultaneous ecc single error correction on both double words of the same page. in user mode the address register is read only. table 360. dflash_adr content: priority list priority level error flag dflash_adr content 1 dflash_mcr[eer] = 1 address of first ecc double error 2 dflash_mcr[rwe] = 1 address of first rww error 3 dflash_mcr[peg] = 0 address of first fpec error 4 dflash_mcr[edc] = 1 address of first ecc single error correction RM0017 flash memory doc id 14629 rev 8 684/904 the user test 0 register allows to control the way in which the flash memory content check is done. bits mre, mrv, ais, eie and dsi[7:0] of the user test 0 register are not accessible whenever dflash_mcr[done] or dflash _ut0[aid] are low: reading returns indeterminate data while writing has no effect. figure 375. dflash user test 0 register (dflash_ut0) offset: 0x0003c access: read/write 0123456789101112131415 rute0000000 dsi w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000 x mre mrv eie ais aie aid w reset0000000000000001 table 361. dflash_ut0 field descriptions field description ute user test enable this status bit gives indication when user test is enabled. all bits in dflash_ut0-2 and dflash_umisr0-4 are locked when this bit is 0. this bit is not writeable to a 1, but may be cleared. the reset value is 0. the method to set this bit is to provide a password, and if the password matches, the ute bit is set to reflect the status of enabled, and is enabl ed until it is cleared by a register write. for ute the password 0xf9f99999 must be written to the dflash_ut0 register. dsi data syndrome input these bits represent the input of syndrome bits of ecc logic used in the ecc logic check. bits dsi[7:0] correspond to the 8 syndrome bits on a double word. these bits are not accessible whenever dflash_mcr[done] or dflash_ut0[aid] are low: reading returns indeterminate data wh ile writing has no effect. 0: the syndrome bit is forced at 0. 1: the syndrome bit is forced at 1. x reserved this bit can be written and its value can be read back, but there is no function associated. this bit is not accessible whenever dflash_mcr [done] or dflash_ut0[aid] are low: reading returns indeterminate data wh ile writing has no effect. flash memory RM0017 685/904 doc id 14629 rev 8 mre margin read enable mre enables margin reads to be done. this bit, combined with mrv, enables regular user mode reads to be replaced by margin reads. margin reads are only active during array integrit y checks; normal user reads are not affected by mre. this bit is not accessible whenever dflash_mcr [done] or dflash_ut0[aid] are low: reading returns indeterminate data while writing has no effect. 0: margin reads are not enabled, all reads are user mode reads. 1: margin reads are enabled. mrv margin read value if mre is high, mrv selects the margin level that is being checked. margin can be checked to an erased level (mrv = 1) or to a programmed level (mrv = 0). this bit is not accessible whenever dflash_mcr [done] or dflash_ut0[aid] are low: reading returns indeterminate data wh ile writing has no effect. 0: zero?s (programmed) margin reads are requested (if mre = 1). 1: one?s (erased) margin reads are requested (if mre = 1). eie ecc data input enable eie enables the ecc logic check operation to be done. this bit is not accessible whenever dflash_mcr [done] or dflash_ut0[aid] are low: reading returns indeterminate data wh ile writing has no effect. 0: ecc logic check is not enabled. 1: ecc logic check is enabled. ais array integrity sequence ais determines the address sequence to be used during array integrity checks or margin read. the default sequence (ais = 0) is meant to replicate sequences normal user code follows, and thoroughly checks the read propagation paths. this sequence is proprietary. the alternative sequence (ais = 1) is just logically sequential. proprietary sequence is forbidden in margin read. it should be noted that the time to run a sequential se quence is significantly shorter than the time to run the proprietary sequence. this bit is not accessible whenever dflash_mcr [done] or dflash_ut0[aid] are low: reading returns indeterminate data wh ile writing has no effect. 0: array integrity equence is proprietary sequence. 1: array integrity or margin read sequence is sequential. aie array integrity enable aie set to ?1? starts the array integrity check done on all selected and unlocked blocks. the pattern is selected by ais, and the misr (dflash_umisr0-4) can be checked after the operation is complete, to determine if a correct signature is obtained. aie can be set only if dflash_mcr[ers], df lash_mcr[pgm] and dflash_mcr[ehv] are all low. 0: array integrity checks are not enabled. 1: array integrity checks are enabled. aid array integrity done aid will be cleared upon an array integrity check being enabled (to signify the operation is on-going). once completed, aid will be set to indicate that the array integrity check is complete. at this time the misr (dflash_umisr0-4) can be checked. 0: array integrity check is on-going. 1: array integrity check is done. table 361. dflash_ut0 fiel d descriptions (continued) field description RM0017 flash memory doc id 14629 rev 8 686/904 dflash user test 1 register (dflash_ut1) the dflash_ut1 register allows to enable the checks on the ecc logic related to the 32 lsb of the double word. the user test 1 register is not acce ssible whenever df lash_mcr[done] or dflash_ut0[aid] are low: reading returns inde terminate data while writing has no effect. dflash user test 2 register (dflash_ut2) the dflash_ut2 register allows to enable the checks on the ecc logic related to the 32 msb of the double word. the user test 2 register is not acce ssible whenever df lash_mcr[done] or dflash_ut0[aid] are low: reading returns inde terminate data while writing has no effect. figure 376. dflash user test 1 register (dflash_ut1) address offset: 0x00040 access: read/write 0123456789101112131415 r dai[31:16] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dai[15:0] w reset0000000000000000 table 362. dflash_ut1 field descriptions field description dai[31:16] data array input, bits 31-0 these bits represent the input of even word of ecc lo gic used in the ecc logic check. bits dai[31:00] correspond to the 32 array bits repres enting word 0 within the double word. 0: the array bit is forced at 0. 1: the array bit is forced at 1. flash memory RM0017 687/904 doc id 14629 rev 8 dflash user multiple input signature register 0 (dflash_umisr0) the dflash_umisr0 provides a means to evaluate the array integrity. the dflash_umisr0 represents the bits 31:0 of the whole 144 bits word (2 double words including ecc). the dflash_umisr0 is not accessible whenever dflash_mcr[done] or dflash_ut0[aid] are low: reading returns inde terminate data while writing has no effect. figure 377. dflash user test 2 register (dflash_ut2) offset: 0x00044 reset value: 0x0000_0000 0123456789101112131415 r dai[63:48] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dai[47:32] w reset0000000000000000 table 363. dflash_ut2 field descriptions field description dai[63:32] data array input, bits 63-32 these bits represent the input of odd word of ecc logic used in the ecc logic check. bits dai[63:32] correspond to the 32 array bits representing word 1 within the double word. 0: the array bit is forced at 0. 1: the array bit is forced at 1. RM0017 flash memory doc id 14629 rev 8 688/904 dflash user multiple input signature register 1 (dflash_umisr1) the dflash_umisr1 provides a mean to evaluate the array integrity. the dflash_umisr1 represents the bits 63:32 of the whole 144 bits word (2 double words including ecc). the dflash_umisr1 is not accessible whenever dflash_mcr[done] or dflash_ut0[aid] are low: reading returns inde terminate data while writing has no effect. figure 378. dflash user multiple input signature register 0 (dflash_umisr0) address offset: 0x00048 reset value: 0x0000_0000 0123456789101112131415 r ms[31:16] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ms[15:0] w reset0000000000000000 table 364. dflash_umisr 0 field descriptions field description ms[31:0] multiple input signature, bits 31?0 these bits represent the misr value obtained accumu lating the bits 31:0 of all the pages read from the flash memory. the ms can be seeded to any value by writing the dflash_umisr0 register. flash memory RM0017 689/904 doc id 14629 rev 8 dflash user multiple input signature register 2 (dflash_umisr2) the dflash_umisr2 provides a mean to evaluate the array integrity. the dflash_umisr2 represents the bits 95:64 of the whole 144 bits word (2 double words including ecc). the dflash_umisr2 is not accessible whenever dflash_mcr[done] or dflash_ut0[aid] are low: reading returns inde terminate data while writing has no effect. figure 379. dflash user multiple input signature register 1 (dflash_umisr1) address offset: 0x0004c reset value: 0x0000_0000 0123456789101112131415 r ms[63:48] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ms[47:32] w reset0000000000000000 table 365. dflash_umisr 1 field descriptions field description ms[63:32] multiple input signature, bits 63-32 these bits represent the misr value obtained accumu lating the bits 63:32 of all the pages read from the flash memory. the ms can be seeded to any value by writing the dflash_umisr1. RM0017 flash memory doc id 14629 rev 8 690/904 dflash user multiple input signature register 3 (dflash_umisr3) the dflash_umisr3 provides a mean to evaluate the array integrity. the dflash_umisr3 represents the bits 127:96 of the whole 144 bits word (2 double words including ecc). the dflash_umisr3 is not accessible whenever dflash_mcr[done] or dflash_ut0[aid] are low: reading returns inde terminate data while writing has no effect. figure 380. dflash user multiple input signature register 2 (dflash_umisr2) address offset: 0x00050 reset value: 0x0000_0000 0123456789101112131415 r ms[95:80] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ms[79:64] w reset0000000000000000 table 366. dflash_umisr 2 field descriptions field description ms[95:64] multiple input signature, bits 95-64 these bits represent the misr va lue obtained accumulating the bits 95:64 of all the pages read from the flash memory. the ms can be seeded to any value by writing the dflash_umisr2. flash memory RM0017 691/904 doc id 14629 rev 8 dflash user multiple input signature register 4 (dflash_umisr4) the multiple input signature register provides a mean to evaluate the array integrity. the user multiple input signature register 4 represents the ecc bits of the whole 144 bits word (2 double words including ecc): bits 23-168:15 are ecc bits for the odd double word and bits 7-024:31 are the ecc bits for the even double word; bits 27-264:5 and 11-1020:21 of misr are respectively the double and single ecc error detection for odd and even double word. the dflash_umisr4 register is not acce ssible whenever dflash_mcr[done] or dflash_ut0[aid] are low: reading returns inde terminate data while writing has no effect. figure 381. dflash user multiple input signature register 3 (dflash_umisr3) address offset: 0x00054 access: read/write 0123456789101112131415 r ms[127:112] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ms[111:96] w reset0000000000000000 table 367. dflash_umisr 3 field descriptions field description ms[127:96] multiple input signature, bits 127096 these bits represent the misr value obtained accumu lating the bits 127:96 of all the pages read from the flash memory. the ms can be seeded to any value by writing the dflash_umisr3. RM0017 flash memory doc id 14629 rev 8 692/904 28.6 programming considerations in the following sections, register names can refer to the cflash or dflash versions of those registers. thus, for example, the term ?mcr? can refer to the cflash_mcr or dflash_mcr based on context. 28.6.1 modify operation all modify operations of the flash memory module are managed through the flash memory user registers interface. all the sectors of the flash memory module belong to the same partition (bank), therefore when a modify operation is active on some sectors no read access is possible on any other sector (read-while-write is not supported). during a flash memory modify operation any at tempt to read any flash memory location will output invalid data and bit mcr[rwe] will be au tomatically set. this means that the flash memory module is not fetchable when a modify operation is active and these commands must be executed from another memory (internal sram or another flash memory module). if during a modify operation a reset occurs, the operation is suddenly terminated and the macrocell is reset to read mode. the data integrity of the flash memory section where the figure 382. dflash user multiple input signature register 4 (dflash_umisr4) address offset: 0x00058 reset value: 0x0000_0000 0123456789101112131415 r ms[159:144] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ms[143:128] w reset0000000000000000 table 368. dflash_umisr 4 field descriptions field description ms[159:128] multiple input signature, bits 159-128 these bits represent the misr value obtained accumulating: the 8 ecc bits for the even double word (on ms[135:128]); the single ecc error detection for even double word (on ms138); the double ecc error detection for even double word (on ms139); the 8 ecc bits for the odd double word (on ms[151:144]); the single ecc error detection for odd double word (on ms154); the double ecc error detection for odd double word (on ms155). the ms can be seeded to any value by writing the dflash_umisr4 register. flash memory RM0017 693/904 doc id 14629 rev 8 modify operation has been terminated is not guaranteed: the interrupted flash memory modify operation must be repeated. in general each modify operation is started through a sequence of three steps: 1. the first instruction is used to select the desired operation by setting its corresponding selection bit in mcr (pgm or ers) or ut0 (mre or eie). 2. the second step is the definition of the operands: the address and the data for programming or the sectors for erase or margin read. 3. the third instruction is used to start the modify operation, by setting mcr[ehv] or ut0[aie]. once selected, but not yet started, one operation can be canceled by resetting the operation selection bit. a summary of the available flash memory modify operations is shown in ta bl e 3 6 9 . once the mcr[ehv] bit (or ut0[aie]) is set, all the operands can no more be modified until the mcr[done] bit (or ut0[aid]) is high. in general each modify operation is completed through a sequence of four steps: 1. wait for operation completion: wait for th e mcr[done] bit (or ut0[aid]) to go high. 2. check operation result: check the mcr[peg] bit (or compare umisr0-4 with expected value). 3. switch off fpec by resetting the mcr[ehv] bit (or ut0[aie]). 4. deselect current operation by clearing the mcr[pgm] / mcr[ers] fields (or ut0[mre] /ut0[eie]). if the device embeds more than one flash memory module and a modify operation is on- going on one of them, then it is forbidden to start any other modify operation on the other flash memory modules. in the following all the possible modify operations are described and some examples of the sequences needed to activate them are presented. 28.6.2 double word program a flash memory program sequence operates on any double word within the flash memory core. up to two words within the double word may be altered in a single program operation. ecc is handled on a 64-bit boundary. thus, if only one word in any given 64-bit ecc segment is programmed, the adjoining word (in that segment) should not be programmed table 369. flash memory modify operations operation select bit operands start bit double word program mcr[pgm] address and data by interlock writes mcr[ehv] sector erase mcr[ers] lms mcr[ehv] array integrity check none lms ut0[aie] margin read ut0[mre] ut0[mrv] + lms ut0[aie] ecc logic check ut0[eie] ut0[dsi], ut1, ut2 ut0[aie] RM0017 flash memory doc id 14629 rev 8 694/904 since ecc calculation has already completed fo r that 64-bit segment. attempts to program the adjoining word will probably result in an operation failure . it is recommended that all programming operations be of 64 bits. the progra mming operation should completely fill selected ecc segments within the double word. programming changes the value stored in an array bit from logic 1 to logic 0 only. programming cannot change a stored logic 0 to a logic 1. addresses in locked/disabled blocks cannot be programmed. the user may program the values in any or all of two words, of a double word, with a single program sequence. double word-bound words have addresses which differ only in address bit 2. the program operation consists of the following sequence of events: 1. change the value in the mcr[pgm] bit from 0 to 1. 2. ensure the block that contains the address to be programmed is unlocked. write the first address to be programmed with the program data. the flash memory module latches address bits (22:3) at this time. the flash memory module latches data written as well. this write is referred to as a program data interlock write. an interlock write may be as large as 64 bits, and as small as 32 bits (depending on the cpu bus). 3. if more than 1 word is to be programmed, write the additional address in the double word with data to be programmed. this is referred to as a program data write. the flash memory module ignores address bits (22:3) for program data writes. the eventual unwritten data word default to 0xffffffff. 4. write a logic 1 to the mcr[ehv] bit to star t the internal program sequence or skip to step 9 to terminate. 5. wait until the mcr[done] bit goes high. 6. confirm that the mcr[peg] bit is 1. 7. write a logic 0 to the mcr[ehv] bit. 8. if more addresses are to be programmed, return to step 2. 9. write a logic 0 to the mcr[pgm] bit to terminate the program operation. program may be initiated with the 0 to 1 transition of the mcr[pgm] bit or by clearing the mcr[ehv] bit at the end of a previous program. the first write after a program is initiated determines the page address to be programmed. this first write is referred to as an interlock write. the interlock write determines if the shadow, test or normal array space will be programmed by causing the mcr[peas] field to be set/cleared. an interlock write must be performed before setting mcr[ehv]. the user may terminate a program sequence by clearing mcr[pgm] prior to setting mcr[ehv]. after the interlock write, additional writes only affect the data to be programmed at the word location determined by address bit 2. unwritten locations default to a data value of 0xffffffff. if multiple writes are done to the same location the data for the last write is used in programming. while mcr[done] is low and mcr[ehv] is high, the user may clear ehv, resulting in a program abort. a program abort forces the module to step 8 of the program sequence. flash memory RM0017 695/904 doc id 14629 rev 8 an aborted program will result in mcr[peg] be ing set low, indicating a failed operation. mcr[done] must be checked to know when the aborting command has completed. the data space being op erated on before the abort will co ntain indeterminate data. this may be recovered by repeating the same program instruction or executing an erase of the affected blocks. example 5 double word program of data 0x55aa55aa at address 0x00aaa8 and data 0xaa55aa55 at address 0x00aaac mcr = 0x00000010; /* set pgm in mcr: select operation */ (0x00aaa8) = 0x55aa55aa; /* latch address and 32 lsb data */ (0x00aaac) = 0xaa55aa55; /* latch 32 msb data */ mcr = 0x00000011; /* set ehv in mcr: operation start */ do /* loop to wait for done=1 */ { tmp = mcr; /* read mcr */ } while ( !(tmp & 0x00000400) ); status = mcr & 0x00000200; /* check peg flag */ mcr = 0x00000010; /* reset ehv in mcr: operation end */ mcr = 0x00000000; /* reset pgm in mcr: deselect operation */ 28.6.3 sector erase erase changes the value stored in all bits of the selected block(s) to logic 1. an erase sequence operates on any combination of blocks (sectors) in the low, mid or high address space, or the shadow sector (if available). the test block cannot be erased. the erase sequence is fully automated within the flash memory. the user only needs to select the blocks to be erased and initiate the erase sequence. locked/disabled blocks cannot be erased. if multiple blocks are selected for erase during an erase sequence, no specific operation order must be assumed. the erase operation consists of the following sequence of events: 1. change the value in the mcr[ers] bit from 0 to 1. 2. select the block(s) to be erased by writing ?1?s to the appropriate bit(s) in the lms register. if the shadow sector is to be erased, this step may be skipped, and lms is ignored. note that lock and select are independent. if a block is selected and locked, no erase will occur. 3. write to any address in flash memory. this is referred to as an erase interlock write. 4. write a logic 1 to the mcr[ehv] bit to start the internal erase sequence or skip to step 9 to terminate. 5. wait until the mcr[done] bit goes high. 6. confirm mcr[peg] = 1. 7. write a logic 0 to the mcr[ehv] bit. 8. if more blocks are to be erased, return to step 2. 9. write a logic 0 to the mcr[ers] bit to terminate the erase operation. after setting mcr[ers], one write, referred to as an interlock write, must be performed before mcr[ehv] can be set to ?1?. data words written during erase sequence interlock writes are ignored. RM0017 flash memory doc id 14629 rev 8 696/904 the user may terminate the erase sequence by clearing ers before setting ehv. an erase operation may be aborted by clearing mcr[ehv] assuming mcr[done] is low, mcr[ehv] is high and mcr[esus] is low. an erase abort forces the module to step 8 of the erase sequence. an aborted erase will result in mcr[peg] bein g set low, indicating a failed operation. mcr[done] must be checked to know when the aborting command has completed. the block(s) being operated on before the abort contain indeterminate data. this may be recovered by executing an erase on the affected blocks. the user may not abort an erase sequence while in erase suspend. example 6 erase of sectors b0f1 and b0f2 mcr = 0x00000004; /* set ers in mcr: select operation */ lms = 0x00000006; /* set lsl2-1 in lms: select sectors to erase */ (0x000000) = 0xffffffff; /* latch a flash memory address with any data */ mcr = 0x00000005; /* set ehv in mcr: operation start */ do /* loop to wait for done=1 */ { tmp = mcr; /* read mcr */ } while ( !(tmp & 0x00000400) ); status = mcr & 0x00000200;/* check peg flag */ mcr = 0x00000004; /* reset ehv in mcr: operation end */ mcr = 0x00000000; /* reset ers in mcr: deselect operation */ erase suspend/resume the erase sequence may be suspended to allow read access to the flash memory core. it is not possible to program or to erase during an erase suspend. during erase suspend, all reads to blocks targeted for erase return indeterminate data. an erase suspend can be initiated by changing the value of the mcr[esus] bit from 0 to 1. mcr[esus] can be set to ?1? at any time when mcr[ers] and mcr[ehv] are high and mcr[pgm] is low. a 0 to 1 transition of mcr[esus] causes the module to start the sequence which places it in erase suspend. the user must wait until mcr[done] = 1 before the module is suspended and further actions are attempted. mcr[do ne] will go high no more than t esus after mcr[esus] is set to ?1?. once suspended, the array may be read. flash memory core reads while mcr[esus] = 1 from the block(s) being erased return indeterminate data. example 7 sector erase suspend mcr = 0x00000007; /* set esus in mcr: erase suspend */ do /* loop to wait for done=1 */ { tmp = mcr; /* read mcr */ } while ( !(tmp & 0x00000400) ); notice that there is no need to clear mcr[ehv] and mcr[ers] in order to perform reads during erase suspend. the erase sequence is resumed by writing a logic 0 to mcr[esus]. mcr[ehv] must be set to ?1? before mcr[esus] can be cleared to resume the operation. flash memory RM0017 697/904 doc id 14629 rev 8 the module continues the erase sequence from one of a set of predefined points. this may extend the time required for the erase operation. example 8 sector erase resume mcr = 0x00000005; /* reset esus in mcr: erase resume */ user test mode the user can perform specific tests to check flash memory module integrity by putting the flash memory module in user test mode. three kinds of test can be performed: array integrity self check margin read ecc logic check the user test mode is equivalent to a modify operation: read accesses attempted by the user during user test mode generates a read-while-write error (mcr[rwe] set). it is not allowed to perform user test operations on the test and shadow sectors. array integrity self check array integrity is checked using a predefined address sequence (proprietary), and this operation is executed on selected and unlocked blocks. once the operation is completed, the results of the reads can be checked by reading the misr value (stored in umisr0?4), to determine if an incorrect read, or ecc detection was noted. the internal misr calculator is a 32-bit register. the 128 bit data, the 16 ecc data and the single and double ecc errors of the two double words are therefore captured by the misr through five different read accesses at the same location. the whole check is done through five complete scans of the memory address space: 1. the first pass will scan only bits 31:0 of each page. 2. the second pass will scan only bits 63:32 of each page. 3. the third pass will scan only bits 95:64 of each page. 4. the fourth pass will scan only bits 127:96 of each page. 5. the fifth pass will scan only the ecc bits (8 + 8) and the single an d double ecc errors (2 + 2) of both double words of each page. the 128 bit data and the 16 ecc data are sampled before the eventual ecc correction, while the single and double error flags are sampled after the ecc evaluation. only data from existing and unlocked locations are captured by the misr. the misr can be seeded to any value by writing the umisr0?4 registers. the array integrity self check consists of the following sequence of events: 1. set ut0[ute] by writing t he related password in ut0. 2. select the block(s) to be checked by writing ?1?s to the appropriate bit(s) in the lms register. RM0017 flash memory doc id 14629 rev 8 698/904 note that lock and select are independent. if a block is selected and locked, no array integrity check will occur. 3. set eventually ut0[ais] bit for a sequential addressing only. 4. write a logic 1 to the ut0[aie] bit to start the array integrity check. 5. wait until the ut0[aid] bit goes high. 6. compare umisr0-4 content with the expected result. 7. write a logic 0 to the ut0[aie] bit. 8. if more blocks are to be checked, return to step 2. it is recommended to leave ut0[ais] at 0 and use the proprietary address sequence that checks the read path more fully, although this sequence takes more time. during the execution of the array integrity check operation it is forbidden to modify the content of block select (lms) and lock (lml, sll) registers, otherwise the misr value can vary in an unpredictable way. while ut0[aid] is low and ut0[aie] is high, the user may clear aie, resulting in a array integrity check abort. ut0[aid] must be checked to know when the aborting command has completed. example 9 array integrity check of sectors b0f1 and b0f2 ut0 = 0xf9f99999; /* set ute in ut0: enable user test */ lms = 0x00000006; /* set lsl2-1 in lms: select sectors */ ut0 = 0x80000002; /* set aie in ut0: operation start */ do /* loop to wait for aid=1 */ { tmp = ut0; /* read ut0 */ } while ( !(tmp & 0x00000001) ); data0 = umisr0; /* read umisr0 content*/ data1 = umisr1; /* read umisr1 content*/ data2 = umisr2; /* read umisr2 content*/ data3 = umisr3; /* read umisr3 content*/ data4 = umisr4; /* read umisr4 content*/ ut0 = 0x00000000; /* reset ute and aie in ut0: operation end */ margin read margin read procedure (either margin 0 or margin 1), can be run on unlocked blocks in order to unbalance the sense amplifiers, respect to standard read conditions, so that all the read accesses reduce the margin vs ?0? (ut0[mrv] = ?0?) or vs ?1? (ut0[mrv] = ?1?). locked sectors are ignored by misr calculation and ecc flagging. the results of the margin reads can be checked comparing checksum value in umisr0-4. since margin reads are done at voltages that differ than the normal read voltage, lifetime expectancy of the flash memory macrocell is impacted by the execution of ma rgin reads. doing marg in reads repetitively results in degradation of the flash memory array, and shorten expected lifetime experienced at normal read levels. for these reasons the margin read usage is allowed only in factory, while it is forbidden to use it inside the user application. in any case the charge losses detected through the margin read cannot be considered failures of the device and no failure analysis will be op ened on them. t he margin read setup operation consists of the following sequence of events: 1. set ut0[ute] by writing t he related password in ut0. 2. select the block(s) to be checked by writing 1?s to the appropriate bit(s) in the lms register. flash memory RM0017 699/904 doc id 14629 rev 8 note that lock and select are independent. if a block is selected and locked, no array integrity check will occur. 3. set t0.ais bit for a sequential addressing only. 4. change the value in the ut0[mre] bit from 0 to 1. 5. select the margin level: ut0[mrv]=0 for 0?s margin, ut0[mrv]=1 for 1?s margin. 6. write a logic 1 to the ut0[aie] bit to start the margin read setup or skip to step 6 to terminate. 7. wait until the ut0[aid] bit goes high. 8. compare umisr0-4 content with the expected result. 9. write a logic 0 to the ut0[aie], ut0[mre] and ut0[mrv] bits. 10. if more blocks are to be checked, return to step 2. it is mandatory to leave ut0[ais] at 1 and use the linear address sequence, the usage of the proprietary sequence in margin read is forbidden. during the execution of the margin read operation it is forbidden to modify the content of block select (lms) and lock (lml, sll) registers, otherwise the misr value can vary in an unpredictable way. the read accesses will be done with the addition of a proper number of wait states to guarantee the correctness of the result. while ut0[aid] is low and ut0[aie] is high, the user may clear aie, resulting in a array integrity check abort. ut0[aid] must be checked to know when the aborting command has completed. example 10 margin read setup versus ?1?s umisr0 = 0x00000000; /* reset umisr0 content */ umisr1 = 0x00000000; /* reset umisr1 content */ umisr2 = 0x00000000; /* reset umisr2 content */ umisr3 = 0x00000000; /* reset umisr3 content */ umisr4 = 0x00000000; /* reset umisr4 content */ ut0 = 0xf9f99999; /* set ute in ut0: enable user test */ lms = 0x00000006; /* set lsl2-1 in lms: select sectors */ ut0 = 0x80000004; /* set ais in ut0: select operation */ ut0 = 0x80000024; /* set mre in ut0: select operation */ ut0 = 0x80000034; /* set mrv in ut0: select margin versus 1?s */ ut0 = 0x80000036; /* set aie in ut0: operation start */ do /* loop to wait for aid=1 */ { tmp = ut0; /* read ut0 */ } while ( !(tmp & 0x00000001) ); data0 = umisr0; /* read umisr0 content*/ data1 = umisr1; /* read umisr1 content*/ data2 = umisr2; /* read umisr2 content*/ data3 = umisr3; /* read umisr3 content*/ data4 = umisr4; /* read umisr4 content*/ ut0 = 0x80000034; /* reset aie in ut0: operation end */ ut0 = 0x00000000; /* reset ute, mre, mrv, ais in ut0: deselect op. */ to exit from the margin read mode a read reset operation must be executed. RM0017 flash memory doc id 14629 rev 8 700/904 ecc logic check ecc logic can be checked by forcing the input of ecc logic: the 64 bits of data and the 8 bits of ecc syndrome can be individually forced and they will drive simultaneously at the same value the ecc logic of the whole page (2 double words). the results of the ecc logic check can be verified by reading the misr value. the ecc logic check operation consists of the following sequence of events: 1. set ut0[ute] by writing t he related password in ut0. 2. write in ut1[dai31?0] and ut2[dai63?32] the double word input value. 3. write in ut0[dsi7?0] the syndrome input value. 4. select the ecc logic check: write a logic 1 to the ut0[eie] bit. 5. write a logic 1 to the ut0[aie] bit to start the ecc logic check. 6. wait until the ut0[aid] bit goes high. 7. compare umisr0?4 content with the expected result. 8. write a logic 0 to the ut0[aie] bit. notice that when ut0[aid] is low umisr0?4 , ut1?2 and bits mre, mrv, eie, ais and dsi7?0 of ut0 are not accessible: reading returns indeterminate data and write has no effect. example 11 ecc logic check ut0 = 0xf9f99999; /* set ute in ut0: enable user test */ ut1 = 0x55555555; /* set dai31-0 in ut1: even word input data */ ut2 = 0xaaaaaaaa; /* set dai63-32 in ut2: odd word input data */ ut0 = 0x80ff0000; /* set dsi7-0 in ut0: syndrome input data */ ut0 = 0x80ff0008; /* set eie in ut0: select ecc logic check */ ut0 = 0x80ff000a; /* set aie in ut0: operation start */ do /* loop to wait for aid=1 */ { tmp = ut0; /* read ut0 */ } while ( !(tmp & 0x00000001) ); data0 = umisr0; /* read umisr0 content (expected 0x55555555) */ data1 = umisr1; /* read umisr1 content (expected 0xaaaaaaaa) */ data2 = umisr2; /* read umisr2 content (expected 0x55555555) */ data3 = umisr3; /* read umisr3 content (expected 0xaaaaaaaa) */ data4 = umisr4; /* read umisr4 content (expected 0x00ff00ff) */ ut0 = 0x00000000; /* reset ute, aie and eie in ut0: operation end */ error correction code the flash memory module provides a method to improve the relia bility of the da ta stored in flash memory: the usage of an error correction code. the word size is fixed at 64 bits. eight ecc bits, programmed to guarantee a single error correction and a double error detection (sec-ded), are associated to each 64-bit double word. ecc circuitry provides correction of single bit faults and is used to achieve automotive reliability targets. some units will experience single bit correcti ons throughout t he life of the product with no impact to product reliability. ecc algorithms the flash memory module supports one ecc algorithm: ?all ?1?s no error?. a modified hamming code is used that ensures the all er ased state (that is, 0xffff.....ffff) data is a flash memory RM0017 701/904 doc id 14629 rev 8 valid state, and will not cause an ecc error. th is allows the user to perform a blank check after a sector erase operation. eeprom emulation the choosen ecc algorithm allows some bit manipulations so that a double word can be rewritten several times without needing an erase of the sector. this allows to use a double word to store flags useful for the eeprom emulation. as an example the choosen ecc algorithm allows to start from an all ?1?s doub le word value and rewrite whichever of its four 16-bits half-words to an all ?0?s content by keeping the same ecc value. table 370 shows a set of double words sharing the same ecc value. when some flash memory sectors are used to perform an eeprom emulation, it is reccomended for safety reason s to reserve at least 3 sectors to this purpose. all ?1?s no error the all ?1?s no error algorithm detects as valid any double word read on a just erased sector (all the 72 bits are ?1?s). this option allows to perform a blank check after a sector erase operation. protection strategy two kinds of protection are available: modify protection to avoid unwanted program/erase in flash memory sectors and censored mode to avoid piracy. table 370. bit manipulation: double words with the same ecc value double word ecc all ?1?s no error 0xffff_ffff_ffff_ffff 0xff 0xffff_ffff_ffff_0000 0xff 0xffff_ffff_0000_ffff 0xff 0xffff_0000_ffff_ffff 0xff 0x0000_ffff_ffff_ffff 0xff 0xffff_ffff_0000_0000 0xff 0xffff_0000_ffff_0000 0xff 0x0000_ffff_ffff_0000 0xff 0xffff_0000_0000_ffff 0xff 0x0000_ffff_0000_ffff 0xff 0x0000_0000_ffff_ffff 0xff 0xffff_0000_0000_0000 0xff 0x0000_ffff_0000_0000 0xff 0x0000_0000_0000_0000 0xff RM0017 flash memory doc id 14629 rev 8 702/904 modify protection the flash memory modify protection information is stored in nonvolatile flash memory cells located in the testflash. this information is read once during the flash memory initialization phase following the exiting from reset and is stored in volatile registers that act as actuators. the reset state of all the volatile modify protection registers is the protected state. all the nonvolatile modify protection registers can be programmed through a normal double word program operation at the related locations in testflash. the nonvolatile modify protection registers cannot be erased. the nonvolatile modify protection registers are physically located in testflash their bits can be programmed to ?0? only once and they can no more be restored to ?1?. the volatile modify protection registers are read/write registers which bits can be written at ?0? or ?1? by the user application. a software mechanism is provided to independently lock/unlock each low, mid and high address space block against program and erase. software locking is done through the lml register. an alternate means to enable software locking for blocks of low address space only is through the sll. all these registers have a nonvolatile image stored in testflash (nvlml, nvsll), so that the locking information is kept on reset. on delivery the testflash nonvolatile image is at all ?1?s, meaning all sectors are locked. by programming the nonvolatile locations in testflash the selected sectors can be unlocked. being the testflash one time programmable (that is, not erasable), once unlocked the sectors cannot be locked again. of course, on the contrary, all the volatile registers can be written at 0 or 1 at any time, therefore the user application can lock and unlock sectors when desired. censored mode the censored mode information is stored in nonvolatile flash memory cells located in the shadow sector. this information is read once during the flash memory initialization phase following the exiting from reset and is stored in volatile registers that act as actuators. the reset state of all the volatile censored mode registers is the protected state. all the nonvolatile censored mode registers can be programmed through a normal double word program operation at the related locations in the shadow sector. the nonvolatile censored mode registers can be erased by erasing the shadow sector. the nonvolatile censored mode registers are physically located in the shadow sector their bits can be programmed to ?0? and restored to ?1? by erasing the shadow sector. the volatile censored mode registers are registers not accessible by the user application. flash memory RM0017 703/904 doc id 14629 rev 8 the flash memory module provides two levels of protection against piracy: if bits cw15:0 of nvscc0 are programmed at 0x55aa and nvsc1 = nvscc0 the censored mode is disabled, while all the other possible values enable the censored mode. if bits sc15:0 of nvscc0 are programmed at 0x55aa and nvsc1 = nvscc0 the public access is disabled, wh ile all the other possible values enable the public access. the parts are delivered to the user with censored mode and public access disabled. 28.7 platform flash memory controller 28.7.1 introduction the platform flash memory controller acts as the interface between the system bus (ahb- lite 2.v6) and up to two banks of integrated flash memory arrays (program and data). it intelligently converts the protoc ols between the system bus a nd the dedicated flash memory array interfaces. a block diagram of the e200z0h power architecture reduced product platform (rpp) reference design is shown below in figure 383 with the platform flash memory controller module and its attached off-platform flash memory arrays highlighted. RM0017 flash memory doc id 14629 rev 8 704/904 figure 383. power architecture e200z0h rpp reference platform block diagram the module list includes: power architecture e200z0h (harvard) core with nexus1 or optional nexus2+ debug ahb crossbar swit ch ?lite? (xbar) memory protection unit (mpu) platform flash memory controller with connections to 2 memory banks platform sram memory controller (pram) ahb-to-ips/apb bus controller (pbridge) for access to on- and off-platform slave modules interrupt controller (intc) 4-channel system timers (stm) software watchdog timer (swt) error correction status module (ecsm) xbar memarray rpp_z0h_ref s0 s2 m0 s7 memarray pram pflash ips/apb intc ahb platform flash memory controller branch unit load/store i-fetcher dispatch gpr integer unit e200z0h core p_i_h* p_d_h* m1 m2 mpu on-platform irqs off-platform irqs debug unit nexus1, nexus2+ m3 stm ips bus ips+apb bus flash regs ips+apb slave modules memarray flash regs bank0 bank1 ecsm swt flash memory RM0017 705/904 doc id 14629 rev 8 throughout this document, several important terms are used to describe the platform flash memory controller module and its connections. these terms are defined here: port ? this is used to describe the amba-ahb connection(s) into the platform flash memory controller. from an architectural and programming model viewpoint, the definition supports up to two ahb ports, even though this specific controller only supports a single ahb connection. bank ? this term is used to describe the attached flash memories. from the platform flash memory controller?s perspective, there may be one or two attached banks of flash memory. the ?code flash memory? is required and always attached to bank0. additionally, there is a ?data flash memory? attached to bank1. the platform flash memory controller interface supports two separate connections, one to each memory bank. array ? within each memory bank, there is one flash memory array instantiations. page ? this value defines the number of bits read from the flash memory array in a single access. for this controller and memory, the page size is 128 bits (16 bytes). the nomenclature ?page buffers and ?line buffers? are used interchangeably. overview the platform flash memory controller supports a 32-bit data bus width at the ahb port and connections to 128-bit read data interfaces from two memory banks, where each bank contains one instantiations of the flash memory array. one flash memory bank is connected to the code flash memory and the other bank is connected to the optional data flash memory. the memory controller capabilities vary between t he two banks with each bank?s functionality optimized with the typical use cases associated with the attached flash memory. as an example, the platform flash memory controller logic associated with the code flash memory bank contains a four-entry ?page? buffer, each entry containing 128 bits of data (1 flash memory page) plus an associat ed controller which prefetches sequential lines of data from the flash memory array into the buffer, while the controller logic associated with the data flash memory bank only supports a 128-bit register which serves as a temporary page holding register and does not support any prefetching. prefetch buffer hits from the code flash memory bank support zero-wait ahb data phase responses. ahb read requests which miss the buffers generate the needed flash memory array access and are forwarded to the ahb upon completion, typically incurring two wait-states at an operating frequency of 60?64 mhz. this memory controller is optimized for applications where a cacheless processor core, e.g., the power e200z0h, is connected through the platform to on-chip memories, e.g., flash memory and sram, where the processor and platform operate at the same frequency. for these applications, the 2-stage pipeline amba-ahb system bus is effectively mapped directly into stages of the processor?s pipeline and zero wait-state responses for most memory accesses are critical for providing the required level of system performance. RM0017 flash memory doc id 14629 rev 8 706/904 features the following list summarizes the key features of the platform flash memory controller: dual array interfaces support up to a total of 16 mb of flash memory, partitioned as two separate 8 mb banks single ahb port interface supports a 32-bit data bus. all ahb aligned and unaligned reads within the 32-bit container are supported. only aligned word writes are supported. array interfaces support a 128-bit read data bus and a 64-bit write data bus for each bank interface with code flash memory (bank0) provides configurable read buffering and page prefetch support. four page read buffers (each 128 bits wide) and a prefetch controller are used to support single-cycle read responses (zero ahb data phase wait- states) for hits in the buffers. the buffers implement a least-recently-used replacement algorithm to maximize performance. interface with optional data flash memory (bank1) includes a 128-bit register to temporarily hold a single flash memory page. this logic supports single-cycle read responses (zero ahb data phase wait-states) for accesses that hit in the holding register. there is no support for prefetching associated with this bank. programmable response for read-while-write sequences including support for stall- while-write, optional stall notification interrupt, optional flash memory operation abort, and optional abort notification interrupt separate and independent configurable access timing (on a per bank basis) to support use across a wide range of platforms and frequencies support of address-based read access timing for emulation of other memory types support for reporting of single- and multi-bit flash memory ecc events typical operating configuration loaded in to programming model by system reset 28.7.2 memory map and register description two memory maps are associated with the platform flash memory controller: one for the flash memory space and another for the program- visible control and configuration registers. the flash memory space is accessed via the amba-ahb port and the program-visible registers are accessed via the slave peripheral bus. details on both memory spaces are provided in section , memory map . there are no program-visible registers that ph ysically reside inside the platform flash memory controller. rather, the platform flash memory controller receives control and configuration information from the flash memory array controller(s) to determine the operating configuration. these are part of the flash memory array?s configuration registers mapped into its slave peripheral (ips) address space but are described here. memory map first, consider the flash memory space access ed via transactions from the platform flash memory controller?s ahb port. to support the two separate flash memory banks, each up to 8 mb in size, the platform flash memory controller uses address bit 23 (haddr[23]) to steer the access to the appropriate memory bank. in addition to the actual flash memory regions, the system memory map includes shadow and test sectors. the program-visible control and configuration registers associated with each memory array are included in the slave peripheral address region. the flash memory RM0017 707/904 doc id 14629 rev 8 system memory map defines one code flash memory array and one data flash memory array. see ta bl e 3 7 1 . for additional information on the address-based read access timing for emulation of other memory types, see section 28.8.11, wait-state emulation . next, consider the memory map associated with the control and configuration registers. regardless of the number of populated banks or the number of flash memory arrays included in a given bank, the configuration of the platform flash memory controller is wholly specified by the platform flash memory controller registers associated with code flash memory array 0. the code array0 register settings define the operating behavior of both flash memory banks; it is recommended that the platform flash memory controller registers for all physically-present arrays be set to the code flash memory array0 values. note: to perform program and erase operations, the control registers in the actual referenced flash memory array must be programmed, but the configuration of the platform flash memory controller module is defined by the platform flash controller registers of code array0. the 32-bit memory map for the platform flash memory controller control registers is shown in table 372 . the base address of the controller is 0xc3f8_8000. table 371. flash memory-related regions in the system memory map start address end address size [kb] region 0x0000_0000 0x0007_ffff 512 code flash memory array 0 0x0008_0000 0x001f_ffff 1536 reserved 0x0020_0000 0x0027_ffff 16 code flash memory array 0: shadow sector 0x0028_0000 0x002f_ffff 1536 reserved 0x0040_0000 0x0040_3fff 16 code flash memory array 0: test sector 0x0040_4000 0x007f_ffff 4078 reserved 0x0080_0000 0x0080_ffff 64 data flash memory array 0 0x0081_0000 0x00bf_ffff 4032 reserved 0x00c0_0000 0x00c7_ffff 16 data flash memory array 0: test sector 0x00c8_0000 0x00ff_ffff 3584 reserved 0x0100_0000 0x1fff_ffff 507904 emulation mapping 0xc3f8_8000 0xc3f8_bfff 16 code flas h memory array 0 configuration 0xc3f8_c000 0xc3f8_ffff 16 data flash memory array 0 configuration table 372. platform flash memory controller 32-bit memory map address offset register location 0x1c platform flash configuration register 0 (pfcr0) on page 28-708 0x20 platform flash configuration register 1 (pfcr1) on page 28-711 0x24 platform flash access protection register (pfapr) on page 28-713 RM0017 flash memory doc id 14629 rev 8 708/904 see the spc560bx and spc560cx data sheet for detailed settings for different values of frequency. register description this section details the individual register s of the platform flash memory controller. flash memory configuration registers must be written only with 32-bit write operations to avoid any issues associated with register ?inc oherency? caused by bits spanning smaller- size (8- or 16-bit) boundaries. platform flash configuration register 0 (pfcr0) this register defines the configuration associated with the code flash memory bank0. it includes fields that provide specific informat ion for up to two separate ahb ports (p0 and the optional p1). for the platform flash memory controller module, the fields associated with ahb port p1 are ignored. the register is described in figure 384 and ta bl e 3 7 3 . note: do not execute code from flash memory when you are programming pfcr0. if you wish to program pfcr0, execute your application code from ram. figure 384. pflash configuration register 0 (pfcr0) offset 0x01c access: read/write 0123456789101112131415 r bk0_apc bk0_wwsc bk0_rwsc bk0_rwwc w reset0001100011000111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r bk0_rwwc 0000000 bk0_rwwc b0_p0_bcfg b0_p0_dpfe b0_p0_ipfe b0_p0_pflm b0_p0_bfe w reset1000000011101101 flash memory RM0017 709/904 doc id 14629 rev 8 table 373. pfcr0 field descriptions field description bk0_apc bank0 address pipelining control this field is used to control the number of cycles between flash memory array access requests. this field must be set to a value appropriate to the operating frequency of the pflash. the required settings are documented in the device datasheet. higher operating frequencies require non-zero settings for this field for proper flash memory operation. 00000: accesses may be in itiated on consecutive (back-to-back) cycles 00001: access requests require one additional hold cycle 00010: access requests require two additional hold cycles ... 11110: access requests require 30 additional hold cycles 11111: access requests require 31 additional hold cycles note: bk0_wwsc bank0 write wait-state control this field is used to control the number of wait-states to be added to the flash memory array access time for writes. this field must be set to a value appropriate to the operating frequency of the pflash. the required settings are documented in the device datasheet. higher operating frequencies require non-zero settings for this field for proper flash memory operation. this field is set to an appropriate value by hardware reset. 00000: no additional wait-states are added 00001: one additional wait-state is added 00010: two additional wait-states are added ... 11111: 31 additional wait-states are added note: bk0_rwsc bank0 read wait-state control this field is used to control the number of wait-states to be added to the flash memory array access time for reads. this field must be set to a value corresponding to the operating frequency of the pflash and the actual read access time of the pfla sh. the required settings are documented in the device datasheet. 00000: no additional wait-states are added 00001: one additional wait-state is added 00010: two additional wait-states are added ... 11111: 31 additional wait-states are added RM0017 flash memory doc id 14629 rev 8 710/904 bk0_rwwc bank0 read-while-write control this 3-bit field defines the controller response to flash memory reads while the array is busy with a program (write) or erase operation. 0??: this state should be avoided. setting to this state can cause unpredictable operation. 111: generate a bus stall for a read while write/erase, disable the stall notification interrupt, disable the abort + abort notification interrupt 110: generate a bus stall for a read while write/erase, enable the stall notification interrupt, disable the abort + abort notification interrupt 101: generate a bus stall for a read while write/erase, enable the operation abort, disable the abort notification interrupt 100: generate a bus stall for a read while write/erase, enable the operation abort and the abort notification interrupt this field is set to 0b111 by hardware reset enabling the stall-while-write/erase and disabling the abort and notification interrupts. b0_p0_bcfg bank0, port 0 page buffer configuration this field controls the configuration of the four p age buffers in the pflash controller. the buffers can be organized as a ?pool? of available resources, or with a fixed partition between instruction and data buffers. if enabled, when a buffer miss occurs, it is alloca ted to the least-recently-used buffer within the group and the just-fetched entry then marked as mo st-recently-used. if the flash memory access is for the next-sequential line, the buffer is not ma rked as most-recently-used until the given address produces a buffer hit. 00: all four buffers are available for any flash memory access, that is, there is no partitioning of the buffers based on the access type. 01: reserved 10: the buffers are partitioned into two groups with buffers 0 and 1 allocated for instruction fetches and buffers 2 and 3 for data accesses. 11: the buffers are partitioned into two groups with buffers 0,1,2 allocated for instruction fetches and buffer 3 for data accesses. this field is set to 2b11 by hardware reset. b0_p0_dpfe bank0, port 0 data prefetch enable this field enables or disables prefetching initiated by a data read access. this field is cleared by hardware reset. prefetching can be enabled/di sabled on a per master basis at pfapr[mxpfd]. 0: no prefetching is triggered by a data read access 1: if page buffers are enabled (b0_p0_bfe = 1), prefetching is triggered by any data read access table 373. pfcr0 field descriptions (continued) field description flash memory RM0017 711/904 doc id 14629 rev 8 platform flash configuration register 1 (pfcr1) this register defines the configuration associated with flash memory bank1. this corresponds to the ?data flash memory?. it includes fields that provide specific information for up to two separate ahb ports (p0 and the optional p1). for the platform flash memory controller module, the fields associated with ahb port p1 are ignored. the register is described below in figure 385 and ta bl e 3 7 4 . note: do not execute code from flash memory when you are programming pfcr1. if you wish to program pfcr1, execute your application code from ram. b0_p0_ipfe bank0, port 0 instruction prefetch enable this field enables or disables prefetching initiated by an instruction fetch read access. this field is set by hardware reset. prefetching can be en abled/disabled on a per master basis at pfapr[mxpfd]. 0: no prefetching is triggered by an instruction fetch read access 1: if page buffers are enabled (b0_p0_bfe = 1), prefet ching is triggered by any instruction fetch read access b0_p0_pflm bank0, port 0 prefetch limit this field controls the prefetch algorithm used by the pflash controller. this field defines the prefetch behavior. in all situations when enabled, only a single prefetch is initiated on each buffer miss or hit. this field is set to 2b10 by hardware reset. 00: no prefetching is performed. 01: the referenced line is prefetched on a buffer miss, that is, prefetch on miss . 1?: the referenced line is prefetched on a buffer mi ss, or the next sequential page is prefetched on a buffer hit (if not already present), that is, prefetch on miss or hit . b0_p0_bfe bank0, port 0 buffer enable this bit enables or disables page buffer read hits. it is also used to invalidate the buffers. this bit is set by hardware reset. 0: the page buffers are disabled from satisfying read requests, and all buffer valid bits are cleared. 1: the page buffers are enabled to satisfy read requests on hits. buffer valid bits may be set when the buffers are successfully filled. table 373. pfcr0 field descriptions (continued) field description RM0017 flash memory doc id 14629 rev 8 712/904 figure 385. pflash configuration register 1 (pfcr1) offset 0x020 access: read/write 0123456789101112131415 r bk1_apc bk1_wwsc bk1_rwsc bk1_rwwc w reset0001100011000111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r bk1_rwwc 0000000 bk1_rwwc 000000 b1_p0_bfe w reset1000000010000001 table 374. pfcr1 field descriptions field description bk1_apc bank1 address pipelining control this field is used to control the number of cycles between flash memory array access requests. this field must be set to a value appropriate to the operating frequency of the pflash. the required settings are documented in the device datasheet. higher operating frequencies require non-zero settings for this field for proper flash memory operation. 00000: accesses may be in itiated on consecutive (back-to-back) cycles 00001: access requests require one additional hold cycle 00010: access requests require two additional hold cycles ... 11110: access requests require 30 additional hold cycles 11111: access requests require 31 additional hold cycles this field is ignored in single bank flash memory configurations. note: bk1_wwsc bank1 write wait-state control this field is used to control the number of wait-states to be added to the flash memory array access time for writes. this field must be set to a value appropriate to the operating frequency of the pflash. the required settings are documented in the device datasheet. higher operating frequencies require non-zero settings for this field for proper flash memory operation. this field is set to an appropriate value by hardware reset. 00000: no additional wait-states are added 00001: one additional wait-state is added 00010: two additional wait-states are added ... 11111: 31 additional wait-states are added this field is ignored in single bank flash memory configurations. flash memory RM0017 713/904 doc id 14629 rev 8 platform flash access protection register (pfapr) the pflash access protection register (pfapr) is used to control read and write accesses to the flash memory based on system master number. prefetching ca pabilities are defined on a per master basis. this register also defines the arbitration mode for controllers supporting two ahb ports. the register is described below in figure 386 and ta bl e 3 7 5 . the contents of the register are loaded from location 0x203e00 of the shadow region in the code flash memory (bank0) array at reset. to temporarily change the values of any of the bk1_rwsc bank1 read wait-state control this field is used to control the number of wait-states to be added to the flash memory array access time for reads. this field must be set to a value corresponding to the operating frequency of the pflash and the actual read access time of the pfla sh. the required settings are documented in the device datasheet. 00000: no additional wait-states are added 00001: one additional wait-state is added 00010: two additional wait-states are added ... 11111: 31 additional wait-states are added this field is ignored in single bank flash memory configurations. bk1_rwwc bank1 read-while-write control this 3-bit field defines the controller response to flash memory reads while the array is busy with a program (write) or erase operation. 0??: terminate any attempted read while write/erase with an error response 111: generate a bus stall for a read while write/erase, disable the stall notification interrupt, disable the abort + abort notification interrupt 110: generate a bus stall for a read while write/erase, enable the stall notification interrupt, disable the abort + abort notification interrupt 101: generate a bus stall for a read while write/erase, enable the operation abort, disable the abort notification interrupt 100: generate a bus stall for a read while write/erase, enable the operation abort and the abort notification interrupt this field is set to 0b111 by hardware reset enabling the stall-while-write/erase and disabling the abort and notification interrupts. this field is ignored in single bank flash memory configurations. b1_p0_pfe bank1, port 0 buffer enable this bit enables or disables read hits from the 1 28-bit holding register. it is also used to invalidate the contents of the holding register. this bit is se t by hardware reset, enabling the use of the holding register. 0: the holding register is disabled from satisfying read requests. 1: the holding register is enabled to satisfy read requests on hits. table 374. pfcr1 field descriptions (continued) field description RM0017 flash memory doc id 14629 rev 8 714/904 fields in the pfapr, a write to the ips-mapped register is performed. to change the values loaded into the pfapr at reset , the word location at address 0x203e00 of the shadow region in the flash memory array must be programmed using the normal sequence of operations. the reset value shown in ta bl e 3 8 6 reflects an erased or unprogrammed value from the shadow region. nonvolatile platform flash acce ss protection register (nvpfapr) the nvpfapr register has a related nonvolatile pfapr located in the shadow sector that contains the default reset value for pfapr. during the reset phase of the flash memory module, the nvpfapr register content is read and loaded into the pfapr. the nvpfapr register is a 64-bit register, of which the 32 most significant bits 63:32 are ?don?t care? and are used to manage ecc codes. figure 386. pflash access protection register (pfapr) offset 0x024 access: read/write 0123456789101112131415 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 m0pfd w reset defined by nvpfapr at cflash test sector address 0x203e00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 m0ap w reset defined by nvpfapr at cflash test sector address 0x203e00 table 375. pfapr field descriptions field description m0pfd e200z0 core master 0 prefetch disable this field controls whether prefetching may be triggered based on the master number of the requesting ahb master. this field is further qualified by the pfcr0[b0_px_dpfe, b0_px_ipfe, bx_py_bfe] bits. for master numbering, see table 125 . 0: prefetching may be triggered by this master 1: no prefetching may be triggered by this master m0ap e200z0 core master 0 access protection these fields control whether read and write accesses to the flash memory are allowed based on the master number of the initiating module. for master numbering, see table 125 . 00: no accesses may be performed by this master 01: only read accesses may be performed by this master 10: only write accesses may be performed by this master 11: both read and write accesses may be performed by this master flash memory RM0017 715/904 doc id 14629 rev 8 28.8 functional description the platform flash memory controller interfaces between the ahb system bus and the flash memory arrays. the platform flash memory controller generates read and write enables, the flash memory array address, write size, and write data as inputs to the flash memory array. the platform flash memory controller captures read data from the flash memory array interface and drives it onto the ahb. up to four pages of data (128-bit width) from bank0 are buffered by the platform flash memory controller. lines may be prefetched in advance of being requested by the ahb interface, allowing single-cycle (zero ahb wait-states) read data responses on buffer hits. several prefetch control algorithms are av ailable for controlling page read buffer fills. prefetch triggering may be restricted to instruction accesses only, data accesses only, or may be unrestricted. prefetch triggering may also be controlled on a per-master basis. buffers may also be selectively enabled or disabled for allocation by instruction and data prefetch; see section , platform flash configuration register 0 (pfcr0) , and section , platform flash configuration register 1 (pfcr1) . access protections may be applied on a per-m aster basis for both reads and writes to support security and privilege mechanisms; see section , platform flash access protection register (pfapr) . throughout this discussion, bkn_ is used as a prefix to refer to two signals, each for each bank: bk0_ and bk1_. also, the nomenclature bx_py_regname is used to reference a program-visible register field associated with bank ?x? and port ?y?. figure 387. nonvolatile platform flash access protection register (nvpfapr) offset: 0x203e00 access: read/write 0123456789101112131415 r 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 m0pfd w reset1111111111111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 m0ap w reset1111111111111111 table 376. nvpfapr field descriptions field description m0pfd see ta bl e 3 7 5 . m0ap see ta bl e 3 7 5 . RM0017 flash memory doc id 14629 rev 8 716/904 28.8.1 access protections the platform flash memory controller provides programmable configurable access protections for both read and write cycles from masters via the pflash access protection register (pfapr). it allows restriction of read and write requests on a per-master basis. this functionality is described in section , platform flash access protection register (pfapr) . detection of a protection violation results in an error response from the platform flash memory controller on the ahb transfer. 28.8.2 read cycles ? buffer miss read cycles from the flash memory array are initiated by the platform flash memory controller. the platform flash memory controller then waits for the programmed number of read wait-states before sampling the read data from the flash memory array. this data is normally stored in the least-recently updated page read buffer for bank0 in parallel with the requested data being forwarded to the ahb. for bank1, the data is captured in the page- wide temporary holding register as the requested data is forwarded to the ahb bus. if the flash memory access was the direct result of an ahb transaction, the page buffer is marked as most-recently-used as it is being loaded. if the flash memory access was the result of a speculative prefetch to the next sequential line, it is first loaded into the least- recently-used buffer. the status of this buffer is not changed to most-recently-used until a subsequent buffer hit occurs. 28.8.3 read cycles ? buffer hit single cycle read responses to the ahb are possible with the platform flash memory controller when the requested read access was previously loaded into one of the bank0 page buffers. in these ?buffer hit? cases, read data is returned to the ahb data phase with a zero wait-state response. likewise, the bank1 logic includes a single 128-bit temporary holding register and sequential accesses which ?hit? in this register are also serviced with a zero wait-state response. 28.8.4 write cycles write cycles are initiated by the platform flash memory controller. the platform flash memory controller then waits for the appropriate number of write wait-states before terminating the write operation. 28.8.5 error termination the first case that can cause an error response to the ahb is when an access is attempted by an ahb master whose corresponding read access control or write access control settings do not allow the access, thus causing a protection violation. in this case, the platform flash memory controller does not initiate a flash memory array access. the second case that can cause an error re sponse to the ahb is when an access is performed to the flash memory array and is terminated with a flash memory error response. see section 28.8.7, flash error response operation . this may occur for either a read or a write operation. a third case involves an attempted read access while the flash memory array is busy doing a write (program) or erase operation if the appropriate read-while-write control field is flash memory RM0017 717/904 doc id 14629 rev 8 programmed for this response. the 3-bit read-while-write control allows for immediate termination of an attempted read, or various stall-while-write/erase operations are occurring. 28.8.6 access pipelining the platform flash memory controller does not support access pipelining since this capability is not supported by the flash memory array. as a result, the apc (address pipelining control) field should typically be the same value as the rwsc (read wait-state control) field for best performance, that is, bkn_apc = bkn_rwsc. it cannot be less than the rwsc. 28.8.7 flash error response operation the flash memory array may signal an error response to terminate a requested access with an error. this may occur due to an uncorrectable ecc error, or because of improper sequencing during program/erase operations. when an error response is received, the platform flash memory controller does not update or validate a bank0 page read buffer nor the bank1 temporary holding register. an error response may be signaled on read or write operations. for additional information on the system registers which capture the faulting address, attributes, data and ecc information, see the chapter ?error correction status module (ecsm).? 28.8.8 bank0 page read buffe rs and prefetch operation the logic associated with bank0 of the platform flash memory controller contains four 128- bit page read buffers which are used to hold instructions and data read from the flash memory array. each buffer oper ates independently, and is f illed using a single array access. the buffers are used for both prefetch and normal demand fetches. for the general case, a page buffer is written at the completion of an error-free flash memory access and the valid bit asserted. subsequent flash memory accesses that ?hit? the buffer, that is, the current access address matches the address stored in the buffer, can be serviced in 0 ahb wait-states as the stored read data is routed from the given page buffer back to the requesting bus master. as noted in section 28.8.7, flash error response operation , a page buffer is not marked as valid if the flash memory array access terminated with any type of transfer error. however, the result is that flash memory array accesses that are tagged with a single-bit correctable ecc event are loaded into the page buffer and validated. for additional comments on this topic, see section , buffer invalidation . prefetch triggering is controllable on a per-master and access-type basis. bus masters may be enabled or disabled from triggering prefetches, and triggering may be further restricted based on whether a read access is for instruction or data. a read access to the platform flash memory controller may trigger a prefetch to the next sequential page of array data on the first idle cycle following the request. the access address is incremented to the next- higher 16-byte boundary, and a flash memory array prefetch is initiated if the data is not already resident in a page buffer. prefetched data is always loaded into the least-recently- used buffer. buffers may be in one of six states, listed here in order of priority: RM0017 flash memory doc id 14629 rev 8 718/904 1. invalid ? the buffer contains no valid data. 2. used ? the buffer contains valid data which has been provided to satisfy an ahb burst type read. 3. valid ? the buffer contains valid data which has been provided to satisfy an ahb single type read. 4. prefetched ? the buffer contains valid data which has been prefetched to satisfy a potential future ahb access. 5. busy ahb ? the buffer is currently being used to satisfy an ahb burst read. 6. busy fill ? the buffer has been allocated to receive data from the flash memory array, and the array access is still in progress. selection of a buffer to be loaded on a miss is based on the following replacement algorithm: 1. first, the buffers are examined to determine if there are any invalid buffers. if there are multiple invalid buffers, the one to be used is selected using a si mple numeric priority, where buffer 0 is selected first, then buffer 1, etc. 2. if there are no invalid buffers, the least-recently-used buffer is selected for replacement. once the candidate page buffer has been selected, the flash memory array is accessed and read data loaded into the buffer. if the buffer load was in response to a miss, the just-loaded buffer is immediately marked as most-recently-us ed. if the buffer load was in response to a speculative fetch to the next-sequential line address after a buffer hit, the recently-used status is not changed. rather, it is marked as most-recently-used only after a subsequent buffer hit. this policy maximizes performance based on reference patterns of flash memory accesses and allows for prefetched data to remain valid when non-prefetch enabled bus masters are granted flash memory access. several algorithms are available for prefetch control which trade off performance versus power. they are defined by the bx_py_pflm (prefetch limit) register field. more aggressive prefetching increases power slightly due to the number of wasted (discarded) prefetches, but may increase performance by lowering average read latency. in order for prefetching to occur, a number of control bits must be enabled. specifically, the global buffer enable (pfcrn[bx_py_bfe]) must be set, the prefetch limit (pfcrn[bx_py_pflm]) must be non-zero, either instruction prefetching (pfcrn[bx_py_ipfe]) or data prefetching (pfcrn[bx_py_dpfe]) enabled, and master access must be enabled (pfapr[mxpfd]). see section , register description , for a description of these control fields. instruction/data prefetch triggering prefetch triggering may be enabled for instruction reads via the bx_py_ipfe control field, while prefetching for data reads is enabled vi a the bx_py_dpfe control field. additionally, the bx_py_pflim field must be set to enable prefetching. prefetches are never triggered by write cycles. per-master prefetch triggering prefetch triggering may be also controlled for individual bus masters. see section , platform flash access protection register (pfapr) , for details on these controls. flash memory RM0017 719/904 doc id 14629 rev 8 buffer allocation allocation of the line read buffers is controlle d via page buffer configuration (bx_py_bcfg) field. this field defines the operating organization of the four page buffers. the buffers can be organized as a ?pool? of available resources (with all four buffers in the pool) or with a fixed partition between buffers allocated to instruction or data accesses. for the fixed partition, two configurations are supported. in one configuration, buffers 0 and 1 are allocated for instruction fetches and buffers 2 and 3 for data accesses. in the second configuration, buffers 0, 1 and 2 are allocated for instruction fetches and buffer 3 reserved for data accesses. buffer invalidation the page read buffers may be invalidated under hardware or software control. at the beginning of all program/erase operatio ns, the flash memory array will invalidate the page read buffers. buffer invalidation occurs at the next ahb non-sequential access boundary, but does not affect a burst from a page read buffer which is in progress. software may invalidate the buffers by clearing the bx_py_bfe bit, which also disables the buffers. software may then re-assert the bx_py_bfe bit to its previous state, and the buffers will have been invalidated. one special case needing software invalidation relates to page buffer ?hits? on flash memory data which was tagged with a single-bit ecc event on the original array access. recall that the page buffer structure includes an status bit signaling the array access detected and corrected a single-bit ecc error. on all subsequent buffer hits to this type of page data, a single-bit ecc event is signaled by the platform flash memory controller. depending on the specific hardware configuration, this reporting of a single-bit ecc event may generate an ecc alert interrupt. in order to prevent repeated ecc alert interrupts, the page buffers need to be invalidated by software after the first notification of the single-bit ecc event. finally, the buffers are invalidated by hardware on any non-sequential access with a non- zero value on haddr[28:24] to support wait-state emulation. 28.8.9 bank1 temporary holding register recall the bank1 logic within the platform flash memory controller includes a single 128-bit data register, used for capturing read data. since this bank does not support prefetching, the read data for the referenced address is bypassed directly back to the ahb data bus. the page is also loaded into the temporary data register and subsequent accesses to this page can hit from this register, if it is enabled (b1_p0_bfe). for the general case, a temporary holding register is written at the completion of an error- free flash memory access and the valid bit asserted. subsequent flash memory accesses that ?hit? the buffer, that is, the current access address matches the address stored in the temporary holding register, can be serviced in 0 ahb wait-states as the stored read data is routed from the temporary register back to the requesting bus master. the contents of the holding register are invalidated by the flash memory array at the beginning of all program/erase operations and on any non-sequential access with a non- zero value on haddr[28:24] (to support wait-state emulation) in the same manner as the bank0 page buffers. additionally, the b1_p0_bfe register bit can be cleared by software to invalidate the contents of the holding register. as noted in section 28.8.7, flash error response operation , the temporary holding register is not marked as valid if the flash memory array access terminated with any type of transfer RM0017 flash memory doc id 14629 rev 8 720/904 error. however, the result is that flash memory array accesses that are tagged with a single- bit correctable ecc event are loaded into the temporary holding register and validated. accordingly, one special case needing software invalidation relates to ho lding register ?hits? on flash memory data which was tagged with a single-bit ecc event. depending on the specific hardware configuration, the reporting of a single-bit ecc event may generate an ecc alert interrupt. in order to prevent repeated ecc alert interrupts, the page buffers need to be invalidated by software after the first notification of the single-bit ecc event. the bank1 temporary holding register effectively operates like a single page buffer. 28.8.10 read-while-write functionality the platform flash memory controller supports various programmable responses for read accesses while the flash memory is busy performing a write (program) or erase operation. for all situations, the platform flash memory controller uses the state of the flash memory array?s mcr[done] output to determine if it is busy performing some type of high voltage operation, namely, if mcr[done] = 0, the array is busy. specifically, two 3-bit read-while-write (bkn_rwwc) control register fields define the platform flash memory controller?s response to these types of access sequences. five unique responses are defined by the bkn_rwwc setting: one that immediately reports an error on an attempted read and four settings that support various stall-while-write capabilities. consider the details of these settings. bkn_rwwc = 0b0-- for this mode, any attempted flash memory read to a busy array is immediately terminated with an ahb error response and the read is blocked in the controller and not seen by the flash memory array. bkn_rwwc = 0b111 this defines the basic stall-while-write capability and represent s the default reset setting. for this mode, the platform flash memory controller module simply stalls any read reference until the flash memory has completed its program/erase operation. if a read access arrives while the array is busy or if mcr[done] goes low while a read is still in progress, the ahb data phase is sta lled and the read access address is saved. once the array has completed its program/erase operation, the platform flash memory controller uses the saved address and attribute information to create a pseudo address phase cycle to ?retry? the read reference and sends the registered information to the array. once the retried address phase is complete, the read is processed normally and once the data is valid, it is forwarded to the ahb bus to terminate the system bus transfer. bkn_rwwc = 0b110 this setting is similar to the basic st all-while-write capab ility provided when bkn_rwwc = 0b111 with the added ability to genera te a notification interrupt if a read arrives while the array is busy with a program/erase operation. there are two notification interrupts, one for each bank (see the intc chapter of this reference manual). bkn_rwwc = 0b101 again, this setting provides the basic sta ll-while-write capability wit h the added ability to abort any program/erase operation if a read access is initiated. for this setting, the read request is captured and retried as de scribed for the basic stall-while-write, plus flash memory RM0017 721/904 doc id 14629 rev 8 the program/erase operation is aborted by the platform flash memory controller. for this setting, no notification interrupts are generated. bkn_rwwc = 0b100 this setting provides the bas ic stall-while-write capability with the ability to abort any program/erase operation if a read access is initiated plus the generation of an abort notification interrupt. for this setting, the read request is captured and retried as described for the basic stall-while-write, the program/erase operation is aborted by the platform flash memory controller and an abort notification interrupt generated. there are two abort notification interrupts, one for each bank. as detailed above, a total of four interrupt requests are associated with the stall-while-write functionality. these interrupt requests are captured as part of ecsm?s interrupt register and logically summed together to form a single request to the interrupt controller. 28.8.11 wait-state emulation emulation of other memory array timings are supported by the platform flash memory controller on read cycles to the flash memory. this functionality may be useful to maintain the access timing for blocks of memory which were used to overlay flash memory blocks for the purpose of system calibration or tuning during code development. the platform flash memory controller inserts additional wait-states according to the values of haddr[28:24]. when these inputs are non-zero, additional cycles are added to ahb read cycles. write cycles are not affected. in addition, no page read buffer prefetches are initiated, and buffer hits are ignored. table 378 and table 379 show the relationship of haddr[28:24] to the number of additional primary wait-states. these wait-states are applied to the initial access of a burst fetch or to single-beat read accesses on the ahb system bus. note that the wait-state sp ecification consists of two components: haddr[28:26] and haddr[25:24] and effectively extends the flash memory read by (8 * haddr[25:24] + haddr[28:26]) cycles. table 377. platform flash memory c ontroller stall-while-write interrupts mir[n] interrupt description ecsm.mir[0] platform flash memory bank0 abort notification, mir[fb0ai] ecsm.mir[1] platform flash memory bank0 stall notification, mir[fb0si] ecsm.mir[2] platform flash memory bank1 abort notification, mir[fb1ai] ecsm.mir[3] platform flash memory bank1 stall notification, mir[fb1s1] table 378. additional wait-state encoding memory address haddr[28:26] additional wait-states 000 0 001 1 010 2 011 3 RM0017 flash memory doc id 14629 rev 8 722/904 table 379 shows the relationship of haddr[25:24] to the number of additional wait-states. these are applied in addition to those specified by haddr[28:26] and thus extend the total wait-state specification capability. 100 4 101 5 110 6 111 7 table 378. additional wait-state encoding memory address haddr[28:26] additional wait-states table 379. extended additional wait-state encoding memory address haddr[25:24] additional wait-states (added to those specified by haddr[28:26]) 00 0 01 8 10 16 11 24 register protection RM0017 723/904 doc id 14629 rev 8 29 register protection 29.1 introduction the register protection module offers a mechanism to protect defined memory-mapped address locations in a module under protection from being written. the address locations that can be protected are module-specific. the protection module is located between the module under protection and the peripheral bridge. this is shown in figure 388 . figure 388. register protection block diagram please see the ?registers under protection? appendix for the list of protected registers. 29.2 features the register protection includes these distinctive features: restrict write accesses for the module under protection to supervisor mode only lock registers for first 6 kb of memory-mapped address space address mirror automatically sets corresponding lock bit once configured lock bits can be protected from changes pbridge supervisor access / lock registers module under protection protection module write data address / access size uaa hlb gcr access allowed? peripheral enable other control signals peripheral enable RM0017 register protection doc id 14629 rev 8 724/904 29.3 modes of operation the register protection module is operable when the module under protection is operable. 29.4 external signal description there are no external signals. 29.5 memory map and register description this section provides a detailed description of the memory map of a module using the register protection. the original 16 kb module memory space is divided into five areas as shown in figure 389 . figure 389. register protection memory diagram area 1 spans 6 kb and holds the normal functional module registers and is transparent for all read/write operations. area 2 spans 2 kb starting at address 0x1800. it is a reserved area, which cannot be accessed. area 3 spans 6 kb, starting at address 0x2000 and is a mirror of area 1. a read/write access to a 0x2000+x address will reads/writes the register at address x. as a side effect, a write access to address 0x2000+x sets the optio nal soft lock bits for address x in the same module register space base + 0x0000 6kb 2 kb reserved mirror module register space 6kb 1.5 kb lock bits with user defined base + 0x1800 base + 0x2000 base + 0x3800 soft locking function 512 b configuration base + 0x3e00 base + 0x3fff area 1 area 2 area 3 area 4 area 5 register protection RM0017 725/904 doc id 14629 rev 8 cycle as the register at address x is written. not all registers in area 1 need to have protection defined by associated soft lock bits. for unprotected registers at address y, accesses to address 0x2000+y will be identical to accesses at a ddress y. only for registers implemented in area 1 and defined as protectable soft lock bits are available in area 4. area 4 is 1.5 kb and holds the soft lock bits, one bit per byte in area 1. the four soft lock bits associated with a module register word are arranged at byte boundaries in the memory map. the soft lock bit registers can be directly written using a bit mask. area 5 is 512 byte and holds the configuration bits of the protection mode. there is one configuration hard lock bit per module that prevents all further modifications to the soft lock bits and can only be cl eared by a system reset once set. the other bits, if set, will allow user access to the protected module. if any locked byte is accessed with a write trans action, a transfer error will be issued to the system and the write transaction will not be execut ed. this is true even if not all accessed bytes are locked. accessing unimplemented 32-bit registers in areas 4 and 5 results in a transfer error. 29.5.1 memory map table 380 gives an overview on the register protection registers implemented. note: reserved registers in area #2 will be handled according to the protec ted ip (module under protection). table 380. register protection memory map address offset register location 0x0000 module register 0 (mr0) on page 29-726 0x0001 module register 1 (mr1) on page 29-726 0x0002 module register 2 (mr2) on page 29-726 0x0003?0x17ff module register 3 (mr3) - module register 6143 (mr6143) on page 29-726 0x1800?0x1fff reserved ? 0x2000 module register 0 (mr0) + set soft lock bit 0 (lmr0) on page 29-726 0x2001 module register 1 (mr1) + set soft lock bit 1 (lmr1) on page 29-726 0x2002?0x37ff module register 2 (mr2) + set soft lock bit 2 (lmr2) ? module register 6143 (mr6143) + set soft lock bit 6143 (lmr6143) on page 29-726 0x3800 soft lock bit register 0 (slbr0): soft lock bits 0-3 on page 29-726 0x3801 soft lock bit register 1 (slbr1): soft lock bits 4-7 on page 29-726 0x3802?0x3dff soft lock bit register 2 (slbr2): soft lock bits 8-11 ? soft lock bit register 1535 (slbr1535): soft lock bits 6140-6143 on page 29-726 0x3e00?0x3ffb reserved ? 0x3ffc global configuration register (gcr) on page 29-727 RM0017 register protection doc id 14629 rev 8 726/904 29.5.2 register description module registers (mr0-6143) this is the lower 6 kb module memory space which holds all the functional registers of the module that is protected by the register protection module. module register and set soft lock bit (lmr0-6143) this is memory area #3 that provides mirrored access to the mr0-6143 registers with the side effect of setting soft lock bits in case of a write access to a mr that is defined as protectable by the locking mechanism. each mr is protectable by one associated bit in a slbr n .slb m , according to the mapping described in ta b l e 3 8 1 . soft lock bit register (slbr0-1535) these registers hold the soft lock bits for the protected registers in memory area #1. figure 382 gives some examples how slbr n .slb and mr n go together. figure 390. soft lock bit register (slbr n ) address 0x3800-0x3dff access: read always supervisor write 01234567 r0000 slb0 slb1 slb2 slb3 w we0 we1 we2 we3 reset00000000 table 381. slbr n field descriptions field description we0 we1 we2 we3 write enable bits for soft lock bits (slb): we0 enables writing to slb0 we1 enables writing to slb1 we2 enables writing to slb2 we3 enables writing to slb3 1 value is written to slb 0 slb is not modified slb0 slb1 slb2 slb3 soft lock bits for one mr n register: slb0 can block accesses to mr[ n *4 + 0] slb1 can block accesses to mr[ n *4 + 1] slb2 can block accesses to mr[ n *4 + 2] slb3 can block accesses to mr[ n *4 + 3] 1 associated mr n byte is locked against write accesses 0 associated mr n byte is unprotected and writeable register protection RM0017 727/904 doc id 14629 rev 8 global configuration register (gcr) this register is used to make global configurations related to register protection. table 382. soft lock bits vs. protected address soft lock bit protected address slbr0.slb0 mr0 slbr0.slb1 mr1 slbr0.slb2 mr2 slbr0.slb3 mr3 slbr1.slb0 mr4 slbr1.slb1 mr5 slbr1.slb2 mr6 slbr1.slb3 mr7 slbr2.slb0 mr8 ... ... figure 391. global configuration register (gcr) address 0x3ffc access: read always supervisor write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r hlb0000000 uaa 0 0 0 0 0 0 0 w reset 0000000000000 0 00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 000000 000000 0 00 w reset 0000000000000 0 00 RM0017 register protection doc id 14629 rev 8 728/904 note: the gcr.uaa bit has no effect on the allowed access modes for the registers in the register protection module. 29.6 functional description 29.6.1 general this module provides a generic register (address) write-protection mechanism. the protection size can be: 32-bit (address == multiples of 4) 16-bit (address == multiples of 2) 8-bit (address == multiples of 1) unprotected (address == multiples of 1) which addresses are protected and the protection size depend on the soc and/or module. therefore this section can just give examples for various protection configurations. for all addresses that are protected there are slbr n .slb m bits that specify whether the address is locked. when an address is locked it can be read but not written in any mode (supervisor/normal). if an address is unprotected the corresponding slbr n .slb m bit is always 0b0 no matter what software is writing to. 29.6.2 change lock settings to change the setting whether an address is locked or unlocked the corresponding slbr n .slb m bit needs to be changed. this can be done using the following methods: modify the slbr n .slb m directly by writing to area #4 set the slbr n .slb m bit(s) by writing to the mirror module space (area #3) both methods are explained in the following sections. table 383. gcr field descriptions field description hlb hard lock bit. this register can not be cleared once it is set by software. it can only be cleared by a system reset. 1 all slb bits are write prot ected and can not be modified 0 all slb bits are accessible and can be modified. uaa user access allowed. 1 the registers in the module under protection can be accessed in the mode defined for the module registers without any a dditional restrictions. 0 the registers in the module under protection can only be written in supervisor mode. all write accesses in non-supervisor mode are not executed and a transfer error is issued. this access restriction is in addition to any access restrictions imposed by the protected ip module. register protection RM0017 729/904 doc id 14629 rev 8 change lock settings directly via area #4 memory area #4 contains the lock bits. they can be modified by writing to them. each slbr n .slb m bit has a mask bit slbr n .we m, which protects it from being modified. this masking makes clear-modify-write operations unnecessary. figure 392 shows two modification examples. in the left example there is a write access to the slbr n register specifying a mask value wh ich allows modification of all slbr n .slb m bits. the example on the right specifies a mask which only allows modification of the bits slbr n .slb[3:1]. figure 392. change lock settings directly via area #4 figure 392 shows four registers that can be protected 8-bit wise. in figure 393 registers with 16-bit protection and in figure 394 registers with 32-bit protection are shown: figure 393. change lock settings for 16-bit protected addresses on the right side of figure 393 it is shown that the data written to slbr n .slb[0] is automatically written to slbr n .slb[1] also. this is done as the address reflected by slbr n .slb[0] is protected 16-bit wise. note th at in this case the write enable slbr n .we[0] must be set while slbr n .we[1] does not matter. as the enable bits slbr n .we[3:2] are cleared the lock bits slbr n .slb[3:2] remain unchanged. in the example on the left side of figure 393 the data written to slbr n .slb[0] is mirrored to slbr n .slb[1] and the data written to slbr n .slb[2] is mirrored to slbr n .slb[3] as for both registers the write enables are set. 1 slb3 slb2 slb1 slb0 slbr n .we[3:0] slbr n .slb[3:0] slb3 slb2 slb1 slb0 slbr n .slb[3:0] change allowed to slb3 write data to slb2 to slb1 to slb0 1 1 1 1slbr n .we[3:0] to slb3 write data to slb2 to slb1 to slb0 1 1 0 change allowed slb0 slb1 slb2 slb3 slbr update lock bits 1slbr n .we[3:0] to slb0 write data to slb1 to slb2 to slb3 x1x slb0 slb1 slb2 slb3 slbr update lock bits 1slbr n .we[3:0] to slb0 write data to slb1 to slb2 to slb3 x00 RM0017 register protection doc id 14629 rev 8 730/904 in figure 394 a 32-bit wise protected register is shown. when slbr n .we[0] is set the data written to slbr n .slb[0] is automatica lly written to slbr n .slb[3:1] also. otherwise slbr n .slb[3:0] remains unchanged. figure 394. change lock settings for 32-bit protected addresses in figure 395 an example is shown which has a mixed protection size configuration: figure 395. change lock settings for mixed protection the data written to slbr n .slb[0] is mirrored to slbr n .slb[1] as the corresponding register is 16-bit protected. the data written to slbr n .slb[2] is blocked as the corresponding register is unprotected. the data written to slbr n .slb[3] is written to slbr n .slb[3]. enable locking via mirror module space (area #3) it is possible to enable locking for a register after writing to it. to do so the mirrored module address space must be used. figure 396 shows one example: 1 slb0 slb1 slb2 slb3 slbr n .we[3:0] slbr.slb[3:0] update lock bits to slb0 write data to slb1 to slb2 to slb3 xxx slb0 slb1 0 slb3 slbr update lock bits 1slbr n .we[3:0] to slb0 write data to slb1 to slb2 to slb3 xx1 register protection RM0017 731/904 doc id 14629 rev 8 figure 396. enable locking via mirror module space (area #3) when writing to address 0x0008 the registers mr9 and mr8 in the protected module are updated. the corresponding lock bits remain unchanged (left part of figure 393 ). when writing to address 0x2008 the registers mr9 and mr8 in the protected module are updated. the corresponding lock bits slbr2.slb[1:0] are set while the lock bits slbr2.slb[3:2] remain unchanged (right part of figure 393 ). figure 397 shows an example where some addresses are protected and some are not: figure 397. enable locking for protected and unprotected addresses in the example in figure 397 addresses 0x0c and 0x0d are unprotected. therefore their corresponding lock bits slbr3.slb[1:0] are always 0b0 (shown in bold). when doing a 32- bit write access to address 0x200c only lo ck bits slbr3.slb[3:2] are set while bits slbr3.slb[1:0] stay 0b0. note: lock bits can only be set via writes to the mirror module space. reads from the mirror module space will not change the lock bits. write protection for locking bits changing the locking bits through any of the procedures mentioned in section , change lock settings directly via area #4 and section , enable locking via mirror module space (area #3) is only possible as long as the bit gcr.hlb is cleared. once this bit is set the locking bits can no longer be modified until there is a system reset. 29.6.3 access errors the protection module generates transfer errors under several circumstances. for the area definition refer to figure 389 . slbr 2 we[3:0] 00000000 slb[3:0] 16-bit write to address 0x0008 no change write to mr[9:8] slbr 2 we[3:0] 00001100 slb[3:0] 16-bit write to address 0x2008 set lock bits write to mr[9:8] slbr 3 we[3:0] 0000 00 00 slb[3:0] before write access slbr 3 we[3:0] 0000 00 11 slb[3:0] 32-bit write to address 0x200c set lock bits write to mr[15:12] after write access RM0017 register protection doc id 14629 rev 8 732/904 1. if accessing area #1 or area #3, the protection module transfers any access error from the underlying module under protection. 2. if user mode is not allowed, user write attempts to all areas will assert a transfer error and the writes will be blocked. 3. access attempts to the reserved area #2 cause a transfer error to be asserted. 4. access attempts to unimplemented 32-bit registers in area #4 or area #5 cause a transfer error to be asserted. 5. attempted writes to a register in area #1 or area #3 with soft lock bit set for any of the affected bytes causes a transfer error to be asserted and the write is blocked. the complete write operation to non-protected bytes in this word is ignored. 6. if writing to a soft lock register in area #4 with the hard lock bit being set a transfer error is asserted. 7. any write operation in any access mode to area #3 while gcr.hlb is set result in a error. 29.7 reset the reset state of each individual bit is shown within the register description section (see section 29.5.2, register description ). in summary, after reset, locking for all mr n registers is disabled. the registers can be accessed in supervisor mode only. 29.8 protected registers for spc560bx and spc560cx the register protection module protects the registers shown in table 384 . table 384. protected registers module register protected size (bits) module base address register offset protected bits code flash memory , 4 registers to protect code flash mcr 32 c3f88000 000 bits[0:31] code flash pfcr0 32 c3f88000 01c bits[0:31] code flash pfcr1 32 c3f88000 020 bits[0:31] code flash pfapr 32 c3f88000 024 bits[0:31] data flash memory, 1 register to protect data flash mcr 32 c3f8c000 000 bits[0:31] siu lite, 64 registers to protect siul irer 32 c3f90000 018 bits[0:31] siul ireer 32 c3f90000 028 bits[0:31] siul ifeer 32 c3f90000 02c bits[0:31] siul ifer 32 c3f90000 030 bits[0:31] register protection RM0017 733/904 doc id 14629 rev 8 siul pcr0 16 c3f90000 040 bits[0:15] siul pcr1 16 c3f90000 042 bits[0:15] siul pcr2 16 c3f90000 044 bits[0:15] siul pcr3 16 c3f90000 046 bits[0:15] siul pcr4 16 c3f90000 048 bits[0:15] siul pcr5 16 c3f90000 04a bits[0:15] siul pcr6 16 c3f90000 04c bits[0:15] siul pcr7 16 c3f90000 04e bits[0:15] siul pcr8 16 c3f90000 050 bits[0:15] siul pcr9 16 c3f90000 052 bits[0:15] siul pcr10 16 c3f90000 054 bits[0:15] siul pcr11 16 c3f90000 056 bits[0:15] siul pcr12 16 c3f90000 058 bits[0:15] siul pcr13 16 c3f90000 05a bits[0:15] siul pcr14 16 c3f90000 05c bits[0:15] siul pcr15 16 c3f90000 05e bits[0:15] siul pcr16 16 c3f90000 060 bits[0:15] siul pcr17 16 c3f90000 062 bits[0:15] siul pcr18 16 c3f90000 064 bits[0:15] siul pcr19 16 c3f90000 066 bits[0:15] siul pcr34 16 c3f90000 084 bits[0:15] siul pcr35 16 c3f90000 086 bits[0:15] siul pcr36 16 c3f90000 088 bits[0:15] siul pcr37 16 c3f90000 08a bits[0:15] siul pcr38 16 c3f90000 08c bits[0:15] siul pcr39 16 c3f90000 08e bits[0:15] siul pcr40 16 c3f90000 090 bits[0:15] siul pcr41 16 c3f90000 092 bits[0:15] siul pcr42 16 c3f90000 094 bits[0:15] siul pcr43 16 c3f90000 096 bits[0:15] siul pcr44 16 c3f90000 098 bits[0:15] siul pcr45 16 c3f90000 09a bits[0:15] table 384. protected registers (continued) module register protected size (bits) module base address register offset protected bits RM0017 register protection doc id 14629 rev 8 734/904 siul pcr46 16 c3f90000 09c bits[0:15] siul pcr47 16 c3f90000 09e bits[0:15] siul psmi0 8 c3f90000 500 bits[0:7] siul psmi4 8 c3f90000 504 bits[0:7] siul psmi8 8 c3f90000 508 bits[0:7] siul psmi12 8 c3f90000 50c bits[0:7] siul psmi16 8 c3f90000 510 bits[0:7] siul ifmc0 32 c3f90000 1000 bits[0:31] siul ifmc1 32 c3f90000 1004 bits[0:31] siul ifmc2 32 c3f90000 1008 bits[0:31] siul ifmc3 32 c3f90000 100c bits[0:31] siul ifmc4 32 c3f90000 1010 bits[0:31] siul ifmc5 32 c3f90000 1014 bits[0:31] siul ifmc6 32 c3f90000 1018 bits[0:31] siul ifmc7 32 c3f90000 101c bits[0:31] siul ifmc8 32 c3f90000 1020 bits[0:31] siul ifmc9 32 c3f90000 1024 bits[0:31] siul ifmc10 32 c3f90000 1028 bits[0:31] siul ifmc11 32 c3f90000 102c bits[0:31] siul ifmc12 32 c3f90000 1030 bits[0:31] siul ifmc13 32 c3f90000 1034 bits[0:31] siul ifmc14 32 c3f90000 1038 bits[0:31] siul ifmc15 32 c3f90000 103c bits[0:31] siul ifcpr 32 c3f90000 1080 bits[0:31] mode entry module, 41 registers to protect mc me me_me 32 c3fdc000 008 bits[0:31] mc me me_im 32 c3fdc000 010 bits[0:31] mc me me_test_mc 32 c3fdc000 024 bits[0:31] mc me me_safe_mc 32 c3fdc000 028 bits[0:31] mc me me_drun_mc 32 c3fdc000 02c bits[0:31] mc me me_run0_mc 32 c3fdc000 030 bits[0:31] mc me me_run1_mc 32 c3fdc000 034 bits[0:31] table 384. protected registers (continued) module register protected size (bits) module base address register offset protected bits register protection RM0017 735/904 doc id 14629 rev 8 mc me me_run2_mc 32 c3fdc000 038 bits[0:31] mc me me_run3_mc 32 c3fdc000 03c bits[0:31] mc me me_halt_mc 32 c3fdc000 040 bits[0:31] mc me me_stop_mc 32 c3fdc000 048 bits[0:31] mc me me_standby_mc 32 c3fdc000 054 bits[0:31] mc me me_run_pc0 32 c3fdc000 080 bits[0:31] mc me me_run_pc1 32 c3fdc000 084 bits[0:31] mc me me_run_pc2 32 c3fdc000 088 bits[0:31] mc me me_run_pc3 32 c3fdc000 08c bits[0:31] mc me me_run_pc4 32 c3fdc000 090 bits[0:31] mc me me_run_pc5 32 c3fdc000 094 bits[0:31] mc me me_run_pc6 32 c3fdc000 098 bits[0:31] mc me me_run_pc7 32 c3fdc000 09c bits[0:31] mc me me_lp_pc0 32 c3fdc000 0a0 bits[0:31] mc me me_lp_pc1 32 c3fdc000 0a4 bits[0:31] mc me me_lp_pc2 32 c3fdc000 0a8 bits[0:31] mc me me_lp_pc3 32 c3fdc000 0ac bits[0:31] mc me me_lp_pc4 32 c3fdc000 0b0 bits[0:31] mc me me_lp_pc5 32 c3fdc000 0b4 bits[0:31] mc me me_lp_pc6 32 c3fdc000 0b8 bits[0:31] mc me me_lp_pc7 32 c3fdc000 0bc bits[0:31] mc me me_pctl[4..7] 32 c3fdc000 0c4 bits[0:31] mc me me_pctl[16..19] 32 c3fdc000 0d0 bits[0:31] mc me me_pctl[20..23] 32 c3fdc000 0d4 bits[0:31] mc me me_pctl[32..35] 32 c3fdc000 0e0 bits[0:31] mc me me_pctl[44..47] 32 c3fdc000 0ec bits[0:31] mc me me_pctl[48..51] 32 c3fdc000 0f0 bits[0:31] mc me me_pctl[56..59] 32 c3fdc000 0f8 bits[0:31] mc me me_pctl[60..63] 32 c3fdc000 0fc bits[0:31] mc me me_pctl[68..71] 32 c3fdc000 104 bits[0:31] mc me me_pctl[72..75] 32 c3fdc000 108 bits[0:31] mc me me_pctl[88..91] 32 c3fdc000 118 bits[0:31] table 384. protected registers (continued) module register protected size (bits) module base address register offset protected bits RM0017 register protection doc id 14629 rev 8 736/904 mc me me_pctl[92..95] 32 c3fdc000 11c bits[0:31] mc me me_pctl[104..107] 32 c3fdc000 128 bits[0:31] clock generation module, 3 registers to protect mc cgm cgm_oc_en 8 c3fe0000 373 bits[0:7] mc cgm cgm_ocds_sc 8 c3fe0000 374 bits[0:7] mc cgm cgm_sc_dc[0..3] 32 c3fe0000 37c bits[0:31] cmu, 1 register to protect cmu cmu_csr 8 c3fe0100 000 bits[24:31] reset generation module, 7 registers to protect mc rgm rgm_ferd 16 c3fe4000 004 bits[0:15] mc rgm rgm_derd 16 c3fe4000 006 bits[0:15] mc rgm rgm_fear 16 c3fe4000 010 bits[0:15] mc rgm rgm_dear 16 c3fe4000 012 bits[0:15] mc rgm rgm_fess 16 c3fe4000 018 bits[0:15] mc rgm rgm_stdby 16 c3fe4000 01a bits[0:15] mc rgm rgm_fbre 16 c3fe4000 01c bits[0:15] power control unit, 1 registers to protect mc pcu pconf2 32 c3fe8000 008 bits[0:31] table 384. protected registers (continued) module register protected size (bits) module base address register offset protected bits software watchdog timer (swt) RM0017 737/904 doc id 14629 rev 8 30 software watchdog timer (swt) 30.1 overview the swt is a peripheral module that can prevent system lockup in situations such as software getting trapped in a loop or if a bus transaction fails to terminate. when enabled, the swt requires periodic execution of a watchdog servicing sequence. writing the sequence resets the timer to a specified time-out period. if this servicing action does not occur before the timer expires the swt generates an interrupt or hardware reset. the swt can be configured to generate a reset or interrupt on an initial time-out, a reset is always generated on a second consecutive time-out. the swt provides a window functionality. when this functionality is programmed, the servicing action should take place within the defined window. when occurring outside the defined period, the swt generates a reset. 30.2 features the swt has the following features: 32-bit time-out register to set the time-out period the unique swt counter clock is the undivided slow internal rc oscillator 128 khz (sirc), no other clock source can be selected programmable select ion of window mode or regular servicing programmable selection of reset or interrupt on an initial time-out master access protection hard and soft configuration lock bits the swt is started on exit of power-on phase (rgm phase 2) to monitor flash boot sequence phase. it is then reset during rgm phase3 and optionally enabled when platform reset is released depending on value of flash user option bit 31 (watchdog_en). 30.3 modes of operation the swt supports three device modes of operation: normal, debug and stop. when the swt is enabled in normal mode, its counter runs continuously. in debug mode, operation of the counter is controlled by the frz bit in the swt_cr. if the frz bit is set, the counter is stopped in debug mode, otherwise it continues to run. in stop mode, operation of the counter is controlled by the stp bit in the swt_cr. if the stp bit is set, the counter is stopped in stop mode, otherwise it continues to run. on exit from stop mode, the swt will continue from the state it wa s before entering this mode. the software watchdog is not available during standby. on exit from standby, the swt behaves in a usual ?out of reset? situation. 30.4 external signal description the swt module does not have any external interface signals. RM0017 software watchdog timer (swt) doc id 14629 rev 8 738/904 30.5 memory map and register description the swt programming model has six 32-bit registers. the programming model can only be accessed using 32-bit (word) accesses. references using a different size are invalid. other types of invalid accesses include: writes to read only registers, incorrect values written to the service register when enabled, accesses to reserved addresses an d accesses by masters without permission. a bus error is generated on invalid accesses. if the swt_cr[ria] bit is set, then the swt system reset is also generated. if either the hlk or slk bits in the swt_cr are set then the swt_cr, swt_to and swt_wn registers are read only. 30.5.1 memory map the swt memory map is shown in ta b l e 3 8 5 . the reset values of swt_cr, swt_to and swt_wn are device specific. these values are determined by swt inputs. 30.5.2 register description swt control register (swt_cr) the swt_cr contains fields for configuring a nd controlling the swt. th e reset value of this register is device specific. some devices can be configured to automatically clear the swt_cr.wen bit during the boot process. this register is read only if either the swt_cr.hlk or swt_cr.slk bits are set. table 385. swt memory map base address: 0xfff3_8000 address offset register location 0x0000 swt control register (swt_cr) on page 30-738 0x0004 swt interrupt register (swt_ir) on page 30-740 0x0008 swt time-out register (swt_to) on page 30-741 0x000c swt window register (swt_wn) on page 30-741 0x0010 swt service register (swt_sr) on page 30-742 0x0014 swt counter output register (swt_co) on page 30-742 software watchdog timer (swt) RM0017 739/904 doc id 14629 rev 8 default value for swt_cr_rst is 0x4000_011b, corresponding to map1 = 1 (only data bus access allowed), ria = 1 (reset on invalid swt access), slk = 1 (soft lock), csl = 1 (irc clock source for counter), frz = 1 (freeze on debug), wen = 1 (watchdog enable). this last bit is cleared when exiting me r eset mode in case flash user option bit 31 (watchdog_en) is ?0?. figure 398. swt control register (swt_cr) offset 0x0000 access: read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r map 0 map 1 map 2 map 3 map 4 map 5 map 6 map 7 00000 0 00 w reset (1) 1. the reset value for the swt_cr is device specific. 0100000000000 0 00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 00000 key ria wnd itr hlk slk csl stp frz wen w reset (1) 0000000100011 0 11 table 386. swt_cr field descriptions field description mapn master access protection for master n. the platfo rm bus master assignments are device specific. 0 = access for the master is not enabled 1 = access for the master is enabled key keyed service mode. 0 = fixed service sequence, the fixed sequence 0xa602, 0xb480 is used to service the watchdog 1 = keyed service mode, two pseudorandom ke y value are used to service the watchdog ria reset on invalid access. 0 = invalid access to the swt generates a bus error 1 = invalid access to the swt c auses a system reset if wen=1 wnd window mode. 0 = regular mode, service sequence can be done at any time 1 = windowed mode, the service sequence is only valid when the down counter is less than the value in the swt_wn register. itr interrupt then reset. 0 = generate a reset on a time-out 1 = generate an interrupt on an initial time -out, reset on a second consecutive time-out hlk hard lock. this bit is only cleared at reset. 0 = swt_cr, swt_to and swt_wn are read/write registers if slk=0 1 = swt_cr, swt_to and swt_wn are read only registers slk soft lock. this bit is cleared by writing the unlock sequence to the service register. 0 = swt_cr, swt_to and swt_wn are read/write registers if hlk=0 1 = swt_cr, swt_to and swt_wn are read only registers RM0017 software watchdog timer (swt) doc id 14629 rev 8 740/904 swt interrupt register (swt_ir) the swt_ir contains the time-out interrupt flag. csl clock selection. selects the sirc oscillator clock that drives the internal timer. csl bit can be written.the status of the bit has no effect on counter clock selection on spc560bx and spc560cx device. 0 = system clock (not applicable in spc560bx and spc560cx) 1 = oscillator clock stp stop mode control. allows the watchdog timer to be stopped when the device enters stop mode. 0 = swt counter continues to run in stop mode 1 = swt counter is stopped in stop mode frz debug mode control. allows the watchdog timer to be stopped when the device enters debug mode. 0 = swt counter continues to run in debug mode 1 = swt counter is stopped in debug mode wen watchdog enabled. 0 = swt is disabled 1 = swt is enabled table 386. swt_cr field descriptions (continued) field description figure 399. swt interrupt register (swt_ir) offset 0x0004 access: read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0000000000000 0 00 w reset 000 00 00 00 00 00 000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0000000 00 000 0 0 tif w reset 000 0 000 00 00 00 000 table 387. swt_ir field descriptions field description tif time-out interrupt flag. the flag and interrupt are clea red by writing a 1 to this bit. writing a 0 has no effect. 0 = no interrupt request 1 = interrupt request due to an initial time-out software watchdog timer (swt) RM0017 741/904 doc id 14629 rev 8 swt time-out register (swt_to) the swt time-out (swt_to) register contains the 32-bit time-out period. the reset value for this register is device specific. this regi ster is read only if either the swt_cr.hlk or swt_cr.slk bits are set. default counter value (swt_to_rst) is 1280 (0x00000500 hexadecimal) which correspond to around 10 ms with a 128 khz clock. swt window register (swt_wn) the swt window (swt_wn) register contains the 32-bit window start value. this register is cleared on reset. this register is read only if either the swt_cr.hlk or swt_cr.slk bits are set. figure 400. swt time-out register (swt_to) offset 0x008 access: read/write 0 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425262728293031 r wto w reset (1) 1. the reset value of the swt_to register is device specific. 00000000000000000000010100000000 table 388. swt_to register field descriptions field description wto watchdog time-out period in clock cycles. an internal 32-bit down counter is loaded with this value or 0x100 which ever is greater when the service s equence is written or when the swt is enabled. figure 401. swt window register (swt_wn) offset 0x00c access: read/write 012345678910111213141516171819202122232425262728293031 r wst w reset 00000000000000000000000000000000 table 389. swt_wn register field descriptions field description wst window start value. when window mode is enabled, the service sequence can only be written when the internal down counter is less than this value. RM0017 software watchdog timer (swt) doc id 14629 rev 8 742/904 swt service register (swt_sr) the swt time-out (swt_sr) service register is the target for service sequence writes used to reset the watchdog timer. swt counter output register (swt_co) the swt counter output (swt_co) register is a read only register that shows the value of the internal down counter when the swt is disabled. figure 402. swt service register (swt_sr) offset 0x010 access: read/write 0 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425262728293031 r 0 0 0 0 0 0000000000000 00000000 00 0 0 00 w wsc reset 00000000000000000000000000000000 table 390. swt_sr field descriptions field description wsc watchdog service code.this field is used to service the watchdog and to clear the soft lock bit (swt_cr.slk). to service the watchdog, the value 0xa602 followed by 0xb480 is written to the wsc field. to clear the soft lock bit (swt _cr.slkswt_cr.), the value 0xc520 followed by 0xd928 is written to the wsc field. figure 403. swt counter output register (swt_co) offset 0x014 access: read only 012345678910111213141516171819202122232425262728293031 r cnt w reset 00000000000000000000000000000000 table 391. swt_co field descriptions field description cnt watchdog count. when the watchdog is disabled (swt_cr.wenswt_cr.=0) this field shows the value of the internal down counter. when the watchdog is enabled the value of this field is 0x0000_0000. values in this field can lag behind the internal counter value for up to six system plus eight counter clock cycles. therefore, the value re ad from this field immediately after disabling the watchdog may be higher than the actual value of the internal counter. software watchdog timer (swt) RM0017 743/904 doc id 14629 rev 8 30.6 functional description the swt is a 32-bit timer designed to enable the system to recover in situations such as software getting trapped in a loop or if a bus transaction fails to terminate. it includes a a control register (swt_cr), an interrupt register (swt_ir), time-out register (swt_to), a window register (swt_wn), a service register (swt_sr) and a counter output register (swt_co). the swt_cr includes bits to enable the timer, set configuration options and lock configuration of the module. the watchdog is enabled by setting the swt_cr.wen bit. the reset value of the swt_ cr.wen bit is device specific1 (enab led). this last bit is cleared when exiting me reset mode in case flash us er option bit 31 (watchdog_en) is ?0?. if the reset value of this bit is 1, the watchdog starts operation automatically after reset is released. some devices can be configured to clear this bit automatically during the boot process. the swt_to register holds the watchdog time-out period in clock cycles unless the value is less than 0x100 in which case the time-out peri od is set to 0x100. this time-out period is loaded into an internal 32-bit down counter when the swt is enabled and each time a valid service sequence is written. the swt_cr.csl bi t selects which clock ( system or oscillator) is used to drive the down counter. the reset va lue of the swt_to register is device-specific as described previously. the configuration of the swt can be locked through use of either a soft lock or a hard lock. in either case, when locked the swt_cr, swt_to and swt_wn registers are read only. the hard lock is enabled by setting the swt_cr.hlk bit which can only be cleared by a reset. the soft lock is enabled by setting the swt_cr.slk bit and is cleared by writing the unlock sequence to the service register. the unlock sequence is a write of 0xc520 followed by a write of 0xd928 to the swt_sr.wsc fi eld. there is no timing requirement between the two writes. the unlock sequence logic ignores service sequence writes and recognizes the 0xc520, 0xd928 sequence regardless of previous writes. the unlock sequence can be written at any time and does not require the swt_cr.wen bit to be set. when enabled, the swt requires periodic exec ution of the watchdog servicing sequence. the service sequence is a write of 0xa602 followed by a write of 0xb480 to the swt_sr.wsc field. writing the service sequence loads the internal down counter with the time-out period. there is no timing requirement between the two writes. the service sequence logic ignores unlock sequence writes and recognizes the 0xa602, 0xb480 sequence regardless of previous writes. accesses to swt registers occur with no peripheral bus wait states. (the peripheral bus bridge may add one or more system wait states.) however, due to synchronization logic in the swt design, recognition of the service sequence or configuration changes may require up to three system plus seven counter clock cycles. if window mode is enabled (swt_cr.wnd bit is set), the service sequence must be performed in the last part of the time-out period defined by the window register. the window is open when the down counter is less than the value in the swt_wn register. outside of this window, service sequence writes are invalid accesses and generate a bus error or reset depending on the value of the swt_cr.ria bit. for example, if the swt_to register is set to 5000 and swt_wn register is set to 1000 then the service sequence must be performed in the last 20% of the time-out period. there is a short lag in the time it takes for the window to open due to synchronization logic in the watchdog design. this delay could be up to three system plus four counter clock cycles. RM0017 software watchdog timer (swt) doc id 14629 rev 8 744/904 the interrupt then reset bit (swt_cr.itr) controls the action taken when a time-out occurs. if the swt_cr.itr bit is not set, a reset is generated immediately on a time-out. if the swt_cr.itr bit is set, an initial time-out causes the swt to generate an interrupt and load the down counter with the time-out period. if the service sequence is not written before the second consecutive time-out, the swt generates a system reset. the interrupt is indicated by the time-out interrupt flag (swt_ir.tif). the interrupt request is cleared by writing a one to the swt_ir.tif bit. the swt_co register shows the value of the down counter when the watchdog is disabled. when the watchdog is enabled this register is cleared. the value shown in this register can lag behind the value in the internal counter fo r up to six system plus eight counter clock cycles. the swt_co can be used during a software self test of the swt. for example, the swt can be enabled and not serviced for a fixed period of time less than the time-out value. then the swt can be disabled (swt_cr.wen cleared) and the value of the swt_co read to determine if the internal down counter is working properly. note: watchdog is disabled at the start of bam execution. in the case of an unexpected issue during bam execution, the cpu may be stalled and an external reset needs to be generated to recover. error correction status module (ecsm) RM0017 745/904 doc id 14629 rev 8 31 error correction status module (ecsm) 31.1 introduction the error correction status module (ecsm) provides a myriad of miscellaneous control functions for the device including program-visible information about configuration and revision levels, a reset status register, and information on memory errors reported by error- correcting codes. 31.2 overview the error correction status module is mapped into the ips space and supports a number of miscellaneous control functions for the device. 31.3 features the ecsm includes these features: program-visible information on the device configuration and revision registers for capturing information on memory errors due to error-correction codes registers to specify the generation of single- and double-bit memory data inversions for test purposes to check ecc protection configuration for additional sram ws for system frequency above 64 + 4% mhz 31.4 memory map and register description this section details the programming model for the error correction status module. this is a 128-byte space mapped to the region serviced by an ips bus controller. 31.4.1 memory map the error correction status module does no t include any logic which provides access control. rather, this function is supported using the standard access control logic provided by the ips controller. table 392 shows the ecsm?s memory map. table 392. ecsm memory map base address: 0xfff4_0000 address offset register location 0x00 processor core type register (pct) on page 31-747 0x02 soc-defined platform revision register (rev) on page 31-747 0x04 reserved 0x08 ips on-platform module configuration register (iopmc) on page 31-747 0x0c?0x12 reserved RM0017 error correction status module (ecsm) doc id 14629 rev 8 746/904 31.4.2 register description attempted accesses to reserved addresses result in an error termination, while attempted writes to read-only registers are ignored and do not terminate with an error. unless noted otherwise, writes to the programming model must match the size of the register, e.g., an n- bit register only supports n-bit writes, etc. attempted writes of a different size than the register width produce an error termination of the bus cycle and no change to the targeted register. 0x13 miscellaneous wakeup control register (mwcr) on page 31-748 0x14?0x1e reserved 0x1f miscellaneous interrupt register (mir) on page 31-750 0x20?0x23 reserved 0x24 miscellaneous user-defined control register (mudcr) on page 31-751 0x28?0x42 reserved 0x43 ecc configuration register (ecr) on page 31-752 0x44?0x46 reserved 0x47 ecc status register (esr) on page 31-754 0x48?0x49 reserved 0x4a ecc error generation register (eegr) on page 31-756 0x4c?0x4f reserved 0x50 platform flash ecc address register (pfear) on page 31-758 0x54?0x55 reserved 0x56 platform flash ecc master number register (pfemr) on page 31-760 0x57 platform flash ecc attributes register (pfeat) on page 31-760 0x58?0x5b reserved 0x5c platform flash ecc data register (pfedr) on page 31-761 0x60 platform ram ecc address register (prear) on page 31-762 0x64 reserved 0x65 platform ram ecc syndrome register (presr) on page 31-762 0x66 platform ram ecc master number register (premr) on page 31-764 0x67 platform ram ecc attributes register (preat) on page 31-765 0x68?0x6b reserved 0x6c platform ram ecc data register (predr) on page 31-766 table 392. ecsm memory map (continued) base address: 0xfff4_0000 address offset register location error correction status module (ecsm) RM0017 747/904 doc id 14629 rev 8 processor core type register (pct) the pct is a 16-bit read-only register specifying the architecture of the processor core in the device. the state of this register is defined by a module input signal; it can only be read from the ips programming model. any attempted write is ignored. soc-defined platform revision register (rev) the rev is a 16-bit read-only register specif ying a revision number. the state of this register is defined by an input signal; it can only be read from the ips programming model. any attempted write is ignored. ips on-platform module configuration register (iopmc) the iopmc is a 32-bit read-only register identifying the presence/absence of the 32 low- order ips peripheral modules connected to the primary ipi slave bus controller. the state of this register is defined by a module input signal; it can only be read from the ips programming model. any attempted write is ignored. figure 404. processor core type register (pct) offset: 0x00 access: read 0123456789101112131415 rpct w reset1000000000010010 table 393. pct field descriptions field description pct processor core type figure 405. soc-defined platform revision register (rev) offset: 0x02 access: read 0123456789101112131415 rrev w reset0000000000000000 table 394. rev field descriptions field description rev revision the rev field is specified by an input signal to define a software-visible revision number. RM0017 error correction status module (ecsm) doc id 14629 rev 8 748/904 miscellaneous wakeup control register (mwcr) implementation of low-power sleep modes and exit from these modes via an interrupt require communication between the ecsm, the interrupt controller and off-platform external logic typically associated with phase-locked loop clock generation circuitry. the miscellaneous wakeup control regi ster (mwcr) provides an 8- bit register controlling entry into these types of low-power modes as well as definition of the interrupt level needed to exit the mode. the following sequence of operations is generally needed to enable this functionality. note that the exact details are likely to be system-specific. 1. the processor core loads the appropriate data value into the mwcr, setting the enbwcr bit and the desired interrupt priority level. 2. at the appropriate time, the processor ceas es execution. the exact mechanism varies by processor core. in some cases, a processor-is-stopped status is signaled to the ecsm and off-platform external logic. this assertion, if properly enabled by mwcr[enbwcr], causes the ecsm output signal ?enter_low_power_mode? to be set. this, in turn, causes the selected off-platform external, low-power mode, as specified by mwcr[lpmd], to be entered, and the appropriate clock signals disabled. in most implementations, there are multiple low-power modes, where the exact clocks to be disabled vary across the different modes. 3. after entering the low-power mode, the interrupt controller enables a special combinational logic path which evaluates all unmasked interrupt requests. the device figure 406. ips on-platform module configuration register (iopmc) offset: 0x08 access: read 0123456789101112131415 r mc[31:16] w reset:0000000000000011 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rmc[15:0] w reset:0000000010000101 table 395. iopmc field descriptions field description mc ips module configuration mc[n] = 0 if an ips module connection to decoded slot ?n? is absent mc[n] = 1 if an ips module connection to decoded slot ?n? is present error correction status module (ecsm) RM0017 749/904 doc id 14629 rev 8 remains in this mode until an event which generates an unmasked interrupt request with a priority level greater than the value programmed in the mwcr[prilvl] occurs. 4. once the appropriately-high interrupt request level arrives, the interrupt controller signals its presence, and the ecsm responds by asserting an ?exit_low_power_mode? signal. 5. the off-platform external logic senses the assertion of the ?exit? signal, and re-enables the appropriate clock signals. 6. with the processor core clocks enabled, the core handles the pending interrupt request. figure 407. miscellaneous w akeup control (mwcr) register offset: 0x13 access: read/write 01234567 r enbwcr 000 prilvl w reset:00000000 table 396. mwcr field descriptions field description enbwcr enable wcr 0 mwcr is disabled. 1 mwcr is enabled. prilvl interrupt priority level the interrupt priority level is a core-specific definition. it specifies the interrupt priority level needed to exit the low-power mode. specifically, an unmasked interrupt request of a priority level greater than the prilvl value is required to exit the mode. certain interrupt controller implementations include logic associated with this priority level that restricts the data value contained in this field to a [0, maximum - 1] range. see the specific interrupt controller module for details. RM0017 error correction status module (ecsm) doc id 14629 rev 8 750/904 miscellaneous interrupt register (mir) all interrupt requests associated with ecsm are collected in the mir. this includes the processor core system bus fault interrupt. during the appropriate interrupt service routine handling these requests, the interrupt source contained in the mir must be explicitly cleared. see figure 408 and ta bl e 3 9 7 . figure 408. miscellaneous interrupt (mir) register offset: 0x1f access: special 01234567 r fb0ai fb0si fb1ai fb1si 0 0 0 0 w1111 reset:00000000 table 397. mir field descriptions field description fb0ai flash bank 0 abort interrupt 0 a flash bank 0 abort has not occurred. 1 a flash bank 0 abort has occurred. the interrupt request is negated by writing a 1 to this bit. writing a 0 has no effect. fb0si flash bank 0 stall interrupt 0 a flash bank 0 stall has not occurred. 1 a flash bank 0 stall has occurred. the interrupt requ est is negated by writing a 1 to this bit. writing a 0 has no effect. fb1ai flash bank 1 abort interrupt 0 a flash bank 1 abort has not occurred. 1 a flash bank 1 abort has occurred. the interrupt request is negated by writing a 1 to this bit. writing a 0 has no effect. fb1si flash bank 1 stall interrupt 0 a flash bank 1 stall has not occurred. 1 a flash bank 1 stall has occurred. the interrupt requ est is negated by writing a 1 to this bit. writing a 0 has no effect. error correction status module (ecsm) RM0017 751/904 doc id 14629 rev 8 miscellaneous user-defined control register (mudcr) the mudcr provides a program-visible register for user-defined control functions. it typically is used as configuration control fo r miscellaneous soc-level modules. the contents of this register is simply output from the ecsm to other modules where the user-defined control functions are implemented. figure 409. miscellaneous user-defined control (mudcr) register offset: 0x24 access: read/write 0123456789101112131415 r mudcr[31] 000000000000000 w reset:0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000000000000 w reset:0000000000000000 table 398. mudcr field descriptions field description mudcr[31] xbar force_round_robin bit this bit is used to drive the force_round_robin bit of the xbar. this will force the slaves into round robin mode of arbitration rather than fi xed mode (unless a master is using priority elevation, which forces the design back into fi xed mode regardless of this bit). by setting the hardware definition to enable_round_robin_reset, this bit will reset to 1. 1 xbar is in round robin mode 0 xbar is in fixed priority mode RM0017 error correction status module (ecsm) doc id 14629 rev 8 752/904 ecc registers for designs including error-correcting code (ecc) implementations to improve the quality and reliability of memories, ther e are a number of program-visible registers for the sole purpose of reporting and logging of memory failures. these registers include: ecc configuration register (ecr) ecc status register (esr) ecc error generation register (eegr) platform flash ecc address register (pfear) platform flash ecc master number register (pfemr) platform flash ecc attributes register (pfeat) platform flash ecc data register (pfedr) platform ram ecc address register (prear) platform ram ecc syndrome register (presr) platform ram ecc master number register (premr) platform ram ecc attributes register (preat) platform ram ecc data register (predr) the details on the ecc registers are provided in the subsequent sections. ecc configuration register (ecr) the ecc configuration register is an 8-bit control register for specifying which types of memory errors are reported. in all systems with ecc, the occurrence of a non-correctable error causes the current access to be terminated with an error condition. in many cases, this error termination is reported directly by the initiating bus master. however, there are certain situations where the occurrence of this type of non-correctable error is not reported by the master. examples include speculative instruction fetches which are discarded due to a change-of-flow operation, and buffered operand writes. the ecc reporting logic in the ecsm provides an optional error interrupt mechanism to signal all non-correctable memory errors. in addition to the interrupt generation, the ecsm captures specific information (memory address, attributes and data, bus master number, etc.) which may be useful for subsequent failure analysis. figure 410. ecc configuration (ecr) register offset: 0x43 access: read/write 01234567 r0 0 er1br ef1br 00 erncr efncr w reset:00000000 error correction status module (ecsm) RM0017 753/904 doc id 14629 rev 8 table 399. ecr field descriptions field description er1br enable sram 1-bit reporting the occurrence of a single-bit sram correction generates a ecsm ecc interrupt request as signalled by the assertion of esr[r1 bc]. the address, attributes and data are also captured in the prear, presr, premr, preat and predr registers. 0 reporting of single-bit sram corrections is disabled. 1 reporting of single-bit sram corrections is enabled. ef1br enable flash 1-bit reporting the occurrence of a single-bit flash correction generates a ecsm ecc interrupt request as signalled by the assertion of esr[f1bc]. the address, attributes and data are also captured in the pfear, pfemr, pfeat and pfedr registers. 0 reporting of single-bit flash corrections is disabled. 1 reporting of single-bit flash corrections is enabled. erncr enable sram non-correctable reporting the occurrence of a non-correctable multi-bi t sram error generates a ecsm ecc interrupt request as signalled by the assertion of esr[rnce ]. the faulting address, attributes and data are also captured in the prear, presr , premr, preat and predr registers. 0 reporting of non-correctable sram errors is disabled. 1 reporting of non-correctable sram errors is enabled. efncr enable flash non-correctable reporting the occurrence of a non-correctable multi-bit flash error generates a ecsm ecc interrupt request as signalled by the assertion of esr[fnce]. the faulting address, attributes and data are also captured in the pfear, pfemr, pfeat and pfedr registers. 0 reporting of non-correctable flash errors is disabled. 1 reporting of non-correctable flash errors is enabled. RM0017 error correction status module (ecsm) doc id 14629 rev 8 754/904 ecc status register (esr) the ecc status register is an 8-bit control register for signaling which types of properly- enabled ecc events have been detected. the esr signals the last, properly-enabled memory event to be detected. ecc interrupt generation is separated into single-bit error detection/correction, uncorrectable error detection and the combination of the two as defined by the following boolean equations: ecsm_ecc1bit_irq = ecr[er1br] & esr[r1bc]// ram, 1-bit correction | ecr[ef1br] & esr[f1bc]// flash, 1-bit correction ecsm_eccrncr_irq = ecr[erncr] & esr[rn ce]// ram, noncorrectable error ecsm_eccfncr_irq = ecr[efncr] & esr[fnce]// flash, noncorrectable error ecsm_ecc2bit_irq = ecsm_eccrncr_irq// ram, noncorrectable error | ecsm_eccfncr_irq// flash, noncorrectable error ecsm_ecc_irq = ecsm_ecc1bit_irq // 1-bit correction | ecsm_ecc2bit_irq// noncorrectable error where the combination of a properly-enabled category in the ecr and the detection of the corresponding condition in the esr produces the interrupt request. the ecsm allows a maximum of one bit of the esr to be asserted at any given time. this preserves the association between the esr and the corresponding address and attribute registers, which are loaded on each occurrence of an properly-enabled ecc event. if there is a pending ecc interrupt and another properly-enabled ecc event occurs, the ecsm hardware automatically handles the esr reporting, clearing the previous data and loading the new state and thus guaranteeing that only a single flag is asserted. to maintain the coherent software view of the reported event, the following sequence in the ecsm error interrupt service routine is suggested: 1. read the esr and save it. 2. read and save all the address and attribute reporting registers. 3. re-read the esr and verify the current contents matches the original contents. if the two values are different, go back to step 1 and repeat. 4. when the values are identical, write a 1 to the asserted esr flag to negate the interrupt request. error correction status module (ecsm) RM0017 755/904 doc id 14629 rev 8 in the event that multiple status flags are signaled simultaneously, ecsm records the event with the r1bc as highest priority, then f1bc, then rnce, and finally fnce. figure 411. ecc status register (esr) offset: 0x47 access: read/write 01234567 r0 0 r1bc f1bc 00 rnce fnce w reset:00000000 table 400. esr field descriptions field description r1bc sram 1-bit correction this bit can only be set if ecr[epr1br] is asse rted. the occurrence of a properly-enabled single- bit sram correction generates a ecsm ecc interr upt request. the address, attributes and data are also captured in the prear, presr, premr, preat and predr registers. to clear this interrupt flag, write a 1 to this bit. writing a 0 has no effect. 0 no reportable single-bit sram correction has been detected. 1 a reportable single-bit sram correction has been detected. f1bc flash memory 1-bit correction this bit can only be set if ecr[epf1br] is asse rted. the occurrence of a properly-enabled single- bit flash memory correction generates a ecsm ecc interrupt request. the address, attributes and data are also captured in the pfear, pfemr, pfeat and pfedr registers. to clear this interrupt flag, write a 1 to this bit. writing a 0 has no effect. 0 no reportable single-bit flash memory correction has been detected. 1 a reportable single-bit flash memory correction has been detected. rnce sram non-correctable error the occurrence of a properly-enabled non-correctable sram error generates a ecsm ecc interrupt request. the faulting address, attrib utes and data are also captured in the prear, presr, premr, preat and predr registers. to cl ear this interrupt flag, write a 1 to this bit. writing a 0 has no effect. 0 no reportable non-correctable sram error has been detected. 1 a reportable non-correctable sram error has been detected. fnce flash memory non-correctable error the occurrence of a properly-enabled non-correct able flash memory error generates a ecsm ecc interrupt request. the faulting address, attribut es and data are also captured in the pfear, pfemr, pfeat and pfedr registers. to clear this interrupt flag, write a 1 to this bit. writing a 0 has no effect. 0 no reportable non-correctable flash memory error has been detected. 1 a reportable non-correctable flash memory error has been detected. RM0017 error correction status module (ecsm) doc id 14629 rev 8 756/904 ecc error generation register (eegr) the ecc error generation register is a 16-bit control register used to force the generation of single- and double-bit data inversions in the memories with ecc, most notably the sram. this capability is provided for two purposes: it provides a software-controlled mechanism for ?injecting? errors into the memories during data writes to verify the integrity of the ecc logic. it provides a mechanism to allow testing of the software service routines associated with memory error logging. it should be noted that while the eegr is associated with the sr am, similar capabilities exist for the flash, that is, the ability to program the non-volatile memory with single- or double-bit errors is supported for the same two reasons previously identified. for both types of memories (sram and flash), the intent is to generate errors during data write cycles, such that subsequent reads of the corrupted address locations generate ecc events, either single-bit corrections or double-bit non-correctable errors that are terminated with an error response. figure 412. ecc error generation register (eegr) offset: 0x4a access: read/write 0123456789101112131415 r0 0 frc1bi fr11bi 00 frcnci fr1nci 0 errbit w reset:0000000000000000 error correction status module (ecsm) RM0017 757/904 doc id 14629 rev 8 table 401. eegr field descriptions field description frc1bi force sram continuous 1-bit data inversions the assertion of this bit forces the sram controller to create 1-bit data inversions, as defined by the bit position specified in errbit[6:0], continuously on every write operation. the normal ecc generation takes place in the sram controller, but then the polarity of the bit position defined by errbit is inverted to introduce a 1-bit ecc event in the sram. after this bit has been enabled to generate anothe r continuous 1-bit data inversion, it must be cleared before being set again to properly re-enable the error generation logic. this bit can only be set if the same soc configurable input enable signal (as that used to enable single-bit correction reporting) is asserted. 0 no sram continuous 1-bit data inversions are generated. 1 1-bit data inversions in the sram are continuously generated. fr11bi force sram one 1-bit data inversion the assertion of this bit forces the sram controller to create one 1-bit data inversion, as defined by the bit position specified in errbit[6:0], on the first write operation after this bit is set. the normal ecc generation takes place in the sram controller, but then the polarity of the bit position defined by errbit is inverted to introduce a 1-bit ecc event in the sram. after this bit has been enabled to generate a single 1-bit data inversion, it must be cleared before being set again to properly re-enable the error generation logic. this bit can only be set if the same soc configurable input enable signal (as that used to enable single-bit correction reporting) is asserted. 0 no sram single 1-bit data inversion is generated. 1 one 1-bit data inversion in the sram is generated. frcnci force sram continuous non-correctable data inversions the assertion of this bit forces the sram controller to create 2-bit data inversions, as defined by the bit position specified in errbit[6:0] and the overall odd parity bit, continuously on every write operation. after this bit has been enabled to generate another continuous non-correctable data inversion, it must be cleared before being set again to properly re-enable the error generation logic. the normal ecc generation takes place in the sram controller, but then the polarity of the bit position defined by errbit and the overall odd parity bit are inverted to introduce a 2-bit ecc error in the sram. 0 no sram continuous 2-bit data inversions are generated. 1 2-bit data inversions in the sram are continuously generated. RM0017 error correction status module (ecsm) doc id 14629 rev 8 758/904 if an attempt to force a non-correctable inversion (by asserting eegr[frcnci] or eegr[frc1nci]) and eegr[errbit] equals 64, th en no data inversion will be generated. the only allowable values for the 4 control bit enables {fr11bi, frc1bi, frcnci, fr1nci} are {0,0,0,0}, {1,0,0,0}, {0,1,0,0}, {0,0,1,0} and {0,0,0,1}. all other values result in undefined behavior. platform flash ecc address register (pfear) the pfear is a 32-bit register for capturing the address of the last, properly-enabled ecc event in the flash memory. depending on the state of the ecc configuration register, an fr1nci force sram one non-correctable data inversions the assertion of this bit forces the sram controller to create one 2-bit data inversion, as defined by the bit position specified in errbit[6:0] and the ov erall odd parity bit, on the first write operation after this bit is set. the normal ecc generation takes place in the sram controller, but then the polarity of the bit position defined by errbit and the overall odd parity bit are inverted to introduce a 2-bit ecc error in the sram. after this bit has been enabled to generate a single 2-bit error, it must be cleared before being set again to properly re-enable the error generation logic. 0 no sram single 2-bit data inversions are generated. 1 one 2-bit data inversion in the sram is generated. errbit error bit position the vector defines the bit position which is comple mented to create the data inversion on the write operation. for the creation of 2-bit data inversions, the bit specified by this field plus the odd parity bit of the ecc code are inverted. the sram controller follows a vector bit ordering scheme where lsb = 0. errors in the ecc syndrome bits can be generated by setting this field to a value greater than the sram width. for example, consider a 32-bit sram implementation. the 32-bit ecc approach requires 7 code bits for a 32-bit word. for pram data width of 32 bits, the actual sram (32b data + 7b for ecc) = 39 bits. the following association between the errbit field and the corrupted memory bit is defined: if errbit = 0, then sram[0] of the odd bank is inverted if errbit = 1, then sram[1] of the odd bank is inverted ... if errbit = 31, then sram[31] of the odd bank is inverted if errbit = 64, then ecc parity[0] of the odd bank is inverted if errbit = 65, then ecc parity[1] of the odd bank is inverted ... if errbit = 70, then ecc parity[6] of the odd bank is inverted for errbit values of 32 to 63 and great er than 70, no bit position is inverted. table 401. eegr field descriptions (continued) field description error correction status module (ecsm) RM0017 759/904 doc id 14629 rev 8 ecc event in the flash causes the address, attributes and data associated with the access to be loaded into the pfear, pfemr, pfeat and pfedr registers, and the appropriate flag (f1bc or fnce) in the ecc status register to be asserted. this register can only be read from the ips programming model; any attempted write is ignored. figure 413. platform flash ec c address register (pfear) offset: 0x50 access: read 0123456789101112131415 r fear[31:16] w reset:???????????????? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r fear[15:0] w reset:???????????????? table 402. pfear field descriptions field description fear flash ecc address register this 32-bit register contains the faulting acce ss address of the last, properly-enabled flash ecc event. RM0017 error correction status module (ecsm) doc id 14629 rev 8 760/904 platform flash ecc master number register (pfemr) the pfemr is a 4-bit register for capturing the xbar bus master number of the last, properly-enabled ecc event in the flash memory. depending on the state of the ecc configuration register, an ecc event in the flash causes the address, attributes and data associated with the access to be loaded into the pfear, pfemr, pfeat and pfedr registers, and the appropriate flag (f1bc or fnce) in the ecc status register to be asserted. this register can only be read from the ips programming model; any attempted write is ignored. . platform flash ecc attributes register (pfeat) the pfeat is an 8-bit register for capturing the xbar bus mast er attributes of the last, properly-enabled ecc event in the flash memory. depending on the state of the ecc configuration register, an ecc event in the flash causes the address, attributes and data associated with the access to be loaded into the pfear, pfemr, pfeat and pfedr registers, and the appropriate flag (f1bc or fnce) in the ecc status register to be asserted. this register can only be read from the ips programming model; any attempted write is ignored. figure 414. platform flash ecc master number register (pfemr) offset: 0x56 access: read 01234567 r0000 femr w reset:0000???? table 403. pfemr field descriptions field description femr flash ecc master number register this 4-bit register contains the xbar bus master number of the faulting access of the last, properly-enabled flash ecc event. figure 415. platform flash ecc attributes register (pfeat) offset: 0x57 access: read 01234567 r write size protection w reset:???????? error correction status module (ecsm) RM0017 761/904 doc id 14629 rev 8 platform flash ecc data register (pfedr) the pfedr is a 32-bit register for capturing the data associated with the last, properly- enabled ecc event in the flash memory. depending on the state of the ecc configuration register, an ecc event in the flash causes the address, attributes and data associated with the access to be loaded into the pfear, pfemr, pfeat and pfedr registers, and the appropriate flag (f1bc or fnce) in the ecc status register to be asserted. the data captured on a multi-bit non-correctable ecc error is undefined. this register can only be read from the ips programming model; any attempted write is ignored. table 404. pfeat field descriptions field description write amba-ahb hwrite 0 amba-ahb read access 1 amba-ahb write access size amba-ahb hsize[2:0] 000 8-bit amba-ahb access 001 16-bit amba-ahb access 010 32-bit amba-ahb access 1xx reserved protection amba-ahb hprot[3:0] protection[3]: cacheable 0 = non-cacheable, 1 = cacheable protection[2]: bufferable 0 = non-bufferable, 1 = bufferable protection[1]: mode 0 = user mode, 1 = supervisor mode protection[0]: type 0 = i-fetch, 1 = data figure 416. platform flash ecc data register (pfedr) offset: 0x5c access: read 0123456789101112131415 r fedr[31:16] w reset:???????????????? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r fedr[15:0] w reset:???????????????? RM0017 error correction status module (ecsm) doc id 14629 rev 8 762/904 platform ram ecc address register (prear) the prear is a 32-bit register for capturing the address of the last, properly-enabled ecc event in the sram memory. depending on the state of the ecc configuration register, an ecc event in the sram causes the address, attributes and data associated with the access to be loaded into the prear, presr, prem r, preat and predr registers, and the appropriate flag (r1bc or rnce) in the ecc status register to be asserted. this register can only be read from the ips programming model; any attempted write is ignored. platform ram ecc syndrome register (presr) the presr is an 8-bit register for capturing the error syndrome of the last, properly- enabled ecc event in the sram memory. depending on the state of the ecc configuration register, an ecc event in the sram causes the address, attributes and data associated with the access to be loaded into th e prear, presr, premr, preat and predr registers, and the appropriate flag (r1bc or rnce) in the ecc status register to be asserted. table 405. pfedr field descriptions field description fedr flash ecc data register this 32-bit register contains the data associated with the faulting access of the last, properly- enabled flash ecc event. the register contains th e data value taken directly from the data bus. figure 417. platform ram ec c address register (prear) offset: 0x60 access: read 0123456789101112131415 r rear[31:16] w reset:???????????????? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rear[15:0] w reset:???????????????? table 406. prear field descriptions field description rear sram ecc address register this 32-bit register contains the faulting acce ss address of the last, properly-enabled sram ecc event. error correction status module (ecsm) RM0017 763/904 doc id 14629 rev 8 this register can only be read from the ips programming model; any attempted write is ignored. table 408 associates the upper 7 bits of the ecc syndrome with the exact data bit in error for single-bit correctable codewords. this table follows the bit vectoring notation where the lsb = 0. note that the syndrome value of 0x01 implies no error condition but this value is not readable when the presr is read for the no error case. figure 418. platform ram ecc syndrome register (presr) offset: 0x65 access: read 01234567 r resr w reset:???????? table 407. presr field descriptions field description resr sram ecc syndrome register this 8-bit syndrome field includes 6 bits of hamming decoded parity plus an odd-parity bit for the entire 39-bit (32-bit data + 7 ecc) code word. the upper 7 bits of the syndrome specify the exact bit position in error for single-bit correctable c odewords, and the combination of a non-zero 7-bit syndrome plus overall incorrect parity bit signal a multi-bit, non-correctable error. for correctable single-bit errors, the mapping shown in table 408 associates the upper 7 bits of the syndrome with the data bit in error. table 408. ram syndrome mapping for single-bit correctable errors presr[resr] data bit in error 0x00 ecc odd[0] 0x01 no error 0x02 ecc odd[1] 0x04 ecc odd[2] 0x06 data odd bank[31] 0x08 ecc odd[3] 0x0a data odd bank[30] 0x0c data odd bank[29] 0x0e data odd bank[28] 0x10 ecc odd[4] 0x12 data odd bank[27] 0x14 data odd bank[26] 0x16 data odd bank[25] RM0017 error correction status module (ecsm) doc id 14629 rev 8 764/904 platform ram ecc master number register (premr) the premr is a 4-bit register for capturin g the xbar bus master number of the last, properly-enabled ecc event in the sram memory. depending on the state of the ecc configuration register, an ecc event in the sram causes the address, attributes and data associated with the access to be loaded into the prear, presr, premr, preat and 0x18 data odd bank[24] 0x1a data odd bank[23] 0x1c data odd bank[22] 0x50 data odd bank[21] 0x20 ecc odd[5] 0x22 data odd bank[20] 0x24 data odd bank[19] 0x26 data odd bank[18] 0x28 data odd bank[17] 0x2a data odd bank[16 0x2c data odd bank[15] 0x58 data odd bank[14] 0x30 data odd bank[13] 0x32 data odd bank[12] 0x34 data odd bank[11] 0x64 data odd bank[10] 0x38 data odd bank[9] 0x62 data odd bank[8] 0x70 data odd bank[7] 0x60 data odd bank[6] 0x40 ecc odd[6] 0x42 data odd bank[5] 0x44 data odd bank[4] 0x46 data odd bank[3] 0x48 data odd bank[2] 0x4a data odd bank[1] 0x4c data odd bank[0] 0x03,0x05........0x4d multiple bit error > 0x4d multiple bit error table 408. ram syndrome ma pping for single-bit correctable errors (continued) presr[resr] data bit in error error correction status module (ecsm) RM0017 765/904 doc id 14629 rev 8 predr registers, and t he appropriate flag (r1bc or rnce) in the ecc status register to be asserted. see the xbar chapte r of this reference manual for a listing of xbar bu s master numbers. this register can only be read from the ips programming model; any attempted write is ignored. platform ram ecc attributes register (preat) the preat is an 8-bit register for capturing the xbar bus master attributes of the last, properly-enabled ecc event in the sram memory. depending on the state of the ecc configuration register, an ecc event in the sram causes the address, attributes and data associated with the access to be loaded into the prear, presr, premr, preat and predr registers, and t he appropriate flag (r1bc or rnce) in the ecc status register to be asserted. figure 419. platform ram ecc master number register (premr) offset: 0x66 access: read 01234567 r0000 remr w reset:0000???? table 409. premr field descriptions field description remr sram ecc master number register this 4-bit register contains the xbar bus master number of the faulting access of the last, properly-enabled sram ecc event. see the xbar chapter of this reference manu al for a listing of xbar bus master numbers. figure 420. platform ram ecc attributes register (preat) offset: 0x67 access: read 01234567 r write size protection w reset:???????? RM0017 error correction status module (ecsm) doc id 14629 rev 8 766/904 platform ram ecc data register (predr) the predr is a 32-bit register for capturing the data associated with the last, properly- enabled ecc event in the sram memory. depending on the state of the ecc configuration register, an ecc event in the sram causes the address, attributes and data associated with the access to be loaded into th e prear, presr, premr, preat and predr registers, and the appropriate flag (r1bc or rnce) in the ecc status register to be asserted. the data captured on a multi-bit non-correctable ecc error is undefined. table 410. preat field descriptions field description write xbar hwrite 0 xbar read access 1 xbar write access size xbar hsize[2:0] 000 8-bit xbar access 001 16-bit xbar access 010 32-bit xbar access 1xx reserved protection xbar hprot[3:0] protection[3]: cacheable 0 = non-cacheable, 1 = cacheable protection[2]: bufferable 0 = non-bufferable,1 = bufferable protection[1]: mode 0 = user mode, 1 = supervisor mode protection[0]: type 0 = i-fetch, 1 = data figure 421. platform ram ecc data register (predr) offset: 0x6c access: read 0123456789101112131415 r redr[31:16] w reset:???????????????? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r redr[15:0] w reset:???????????????? table 411. predr field descriptions field description redr sram ecc data register this 32-bit register contains the data associated with the faulting access of the last, properly- enabled sram ecc event. the register contains the data value taken directly from the data bus. error correction status module (ecsm) RM0017 767/904 doc id 14629 rev 8 31.4.3 register protection logic exists which restricts accesses to intc, ecsm, mpu, stm and swt to supervisor mode only. accesses in user mode are not possible. RM0017 ieee 1149.1 test access port controller (jtagc) doc id 14629 rev 8 768/904 32 ieee 1149.1 test access port controller (jtagc) 32.1 introduction the jtag port of the device consists of three inputs and one output. these pins include test data input (tdi), test data output (tdo), test mode select (tms), and test clock input (tck). tdi, tdo, tms and tck are co mpliant with the ieee 1149.1-2 001 standard and are shared with the ndi through the test access port (tap) interface. support of ieee 1149.7 (cjtagc) is planned but not actually supported on this device. for more information, please contact your sales representative. 32.2 block diagram figure 422 is a block diagram of the jtag controller (jtagc) block. figure 422. jtag controller block diagram 32.3 overview the jtagc provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode. testing is performed via a boundary scan technique, as defined in the ieee 1149.1-2001 standard. in addition, instructions can be executed that allow the test access port (tap) to be shared with other modules on the mcu. all data input to and output from the jtagc is communicated in serial format. tck tms tdi test access port (tap) tdo 32-bit device identification register boundary scan register . . controller 1-bit bypass register . 5-bit tap instruction decoder 5-bit tap instruction register . . . power-on reset ieee 1149.1 test access port contro ller (jtagc) RM0017 769/904 doc id 14629 rev 8 32.4 features the jtagc is compliant with the ieee 1149.1- 2001 standard, and supports the following features: ieee 1149.1-2001 test access port (tap) interface 4 pins (tdi, tms, tck, and tdo)?refer to section 32.6 external signal description a 5-bit instruction register that supports several ieee 1149.1-2001 defined instructions, as well as several public and private mcu specific instructions 2 test data registers: ? bypass register ? device identification register a tap controller state machine that controls the operation of the data registers, instruction register and associated circuitry 32.5 modes of operation the jtagc uses a power-on reset indication as its primary reset signals. several ieee 1149.1-2001 defined test modes are supported, as well as a bypass mode. 32.5.1 reset the jtagc is placed in reset when the tap controller state machine is in the test-logic- reset state. the test-logic-r eset state is en tered upon the assertion of the power-on reset signal, or through tap controller state machine transitions controlled by tms. asserting power-on reset results in asynchronous entry into the reset state. while in reset, the following actions occur: the tap controller is forced into the test-logic-reset state, thereby disabling the test logic and allowing normal operation of the on -chip system logic to continue unhindered. the instruction register is lo aded with the idcode instruction. in addition, execution of certain instructions can result in assertion of the internal system reset. these instructions include extest. 32.5.2 ieee 1149.1-2001 de fined test modes the jtagc supports several ieee 1149.1-200 1 defined test modes. the test mode is selected by loading the appropriate instruction into the instruction register while the jtagc is enabled. supported test instructions include extest, sample and sample/preload. each instruction defines the set of data registers that can operate and interact with the on- chip system logic while the instruction is current. only one test data register path is enabled to shift data between tdi and tdo for each instruction. the boundary scan register is external to jtagc but can be accessed by jtagc tap through extest,sample,sample/preload instructions. the functionality of each test mode is explained in more detail in section 32.8.4 jtagc instructions . bypass mode when no test operation is required, the bypass instruction can be loaded to place the jtagc into bypass mode. while in bypass mode, the single-bit bypass shift register is used to provide a minimum-length serial path to shift data between tdi and tdo. RM0017 ieee 1149.1 test access port controller (jtagc) doc id 14629 rev 8 770/904 tap sharing mode there are three selectable aux iliary tap controllers that share the tap with the jtagc. selectable tap controllers include the nexu s port controller (npc) and platform. the instructions required to grant ownership of the tap to the auxiliary tap controllers are access_aux_tap_npc, access_aux_tap_once, access_aux_tap_tcu. instruction opcodes for each instruction are shown in ta bl e 4 1 4 . when the access instruction for an auxiliary t ap is loaded, control of the jtag pins is transferred to the selected tap controller. any data input via tdi and tms is passed to the selected tap controller, and any tdo output from the selected tap controller is sent back to the jtagc to be output on the pins. the jtagc regains control of the jtag port during the update-dr state if the pause-dr state was ente red. auxiliary tap controllers are held in run-test/idle while they are inactive. for more information on the tap controllers refer to the nexus port controller chapter of the reference manual. 32.6 external signal description the jtagc consists of four signals that connect to off-chip development tools and allow access to test support functions. the jtagc signals are outlined in ta b l e 4 1 2 : the jtagc pins are shared with gpio. tdo at reset is a input pad and output direction control from jtagc. once tap enters shift-ir or shift-dr then output direction control from jtagc which allows the value to see on pad. it is up to the user to configure them as gpios accordingly, in this case spc560bx and spc560cx get in compliance with ieee 1149.1- 2001. 32.7 memory map and register description this section provides a detailed description of the jtagc registers accessible through the tap interface, including data registers and the instruction register. individual bit-level descriptions and reset states of each register are included. these registers are not memory- mapped and can only be accessed through the tap. 32.7.1 instruction register the jtagc uses a 5-bit instruction register as shown in table 423 . the instruction register allows instructions to be loaded into the module to select the test to be performed or the test data register to be accessed or both. instructions are shifted in through tdi while the tap controller is in the shift-ir st ate, and latched on the falling edge of tck in the update-ir table 412. jtag signal properties name i/o function reset state tck i test clock pull up tdi i test data in pull up tdo o test data out high z tms i test mode select pull up ieee 1149.1 test access port contro ller (jtagc) RM0017 771/904 doc id 14629 rev 8 state. the latched instruction value can only be changed in the update-ir and test-logic- reset tap controller states. synchronous entry into the test-logic-reset state results in the idcode instruction being loaded on the falling edge of tck. asynchronous entry into the test-logic-reset state results in asynchronous loading of the idcode instruction. during the capture-ir tap controller state, the instruction shift register is loaded with the value 0b10101, making this value the register?s read value when the tap controller is sequenced into the shift-ir state. 32.7.2 bypass register the bypass register is a single-bit shift register path selected for serial data transfer between tdi and tdo when the bypass, or reserve instructions are active. after entry into the capture-dr state, the single-bit shift register is set to a logic 0. therefore, the first bit shifted out after selecting the bypass register is always a logic 0. 32.7.3 device identification register the device identification register, shown in table 424 , allows the part revision number, design center, part identification number, and manufacturer identity code to be determined through the tap. the device identification register is selected for serial data transfer between tdi and tdo when the idcode instru ction is active. entry into the capture-dr state while the device identification register is selected loads the idcode into the shift register to be shifted out on tdo in the shift-dr state. no action occurs in the update-dr state. figure 423. 5-bit instruction register 43210 r1 0 1 01 w instruction code reset00001 figure 424. device identification register ir[4:0]: 0_0001 (idcode) access: r/o 0 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425262728293031 r prn dc pin mic id w reset 00001010111001000001000001000001 table 413. device identificati on register field descriptions field description 0?3 prn part revision number. contains the revision number of the device. this field changes with each revision of the device or module. 4?9 dc design center. for the spc560bx and spc560cx this value is 0x2b. 10?19 pin part identification number. contains the part numb er of the device. for the spc560bx and spc560cx, this value is 0x241. RM0017 ieee 1149.1 test access port controller (jtagc) doc id 14629 rev 8 772/904 32.7.4 boundary scan register the boundary scan register is connected between tdi and tdo when the extest, sample or sample/preload instru ctions are active. it is used to capture input pin data, force fixed values on output pins, and select a logic value and direction for bidirectional pins. each bit of the boundary scan register represents a separate boundary scan register cell, as described in the ieee 1149.1-200 1 standard and discussed in section 32.8.5 boundary scan . the size of the boundary scan register is 464 bits. 32.8 functional description 32.8.1 jtagc reset configuration while in reset, the tap controller is forced into the test-logic-reset state, thus disabling the test logic and allowing normal operation of the on-chip system logic. in addition, the instruction register is loaded with the idcode instruction. 32.8.2 ieee 1149.1-2001 (jta g) test access port the jtagc uses the ieee 1149. 1-2001 tap for accessing regi sters. this port can be shared with other tap controllers on the mcu. for more detail on tap sharing via jtagc instructions refer to section access_aux_tap_x instructions . data is shifted between tdi and tdo though the selected register starting with the least significant bit, as illustrated in figure 425 . this applies for the instruction register, test data registers, and the bypass register. figure 425. shifting data through a register 32.8.3 tap controller state machine the tap controller is a synchronous state machine that interprets the sequence of logical values on the tms pin. figure 426 shows the machine?s states. the value shown next to each state is the value of the tms signal sampled on the rising edge of the tck signal. as figure 426 shows, holding tms at logic 1 while clocking tck through a sufficient number of rising edges also causes the state machine to enter the test-logic-reset state. 20?30 mic manufacturer identity code. contains the reduced joint electron device engineering council (jedec) id for stmicroelectronics, 0x20. 31 id idcode register id. identifies this register as the device identification re gister and not the bypass register. always set to 1. table 413. device identification re gister field descriptions (continued) field description selected register msb lsb tdi tdo ieee 1149.1 test access port contro ller (jtagc) RM0017 773/904 doc id 14629 rev 8 figure 426. ieee 1149.1-2001 tap controller finite state machine selecting an ieee 1149.1-2001 register access to the jtagc data registers is done by loading the instruction register with any of the jtagc instructions while the jtagc is enable d. instructions are shifted in via the select- ir-scan path and loaded in the update-ir state. at this point, all data register access is performed via the select-dr-scan path. test logic reset run-test/idle select-dr-scan select-ir-scan capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir 1 0 1 1 1 00 0 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 note: the value shown adjacent to each state transition in this figure represents the value of tms at the time of a rising edge of tck. RM0017 ieee 1149.1 test access port controller (jtagc) doc id 14629 rev 8 774/904 the select-dr-scan path is used to read or write the register data by shifting in the data (lsb first) during the shift-dr state. when reading a register, the register value is loaded into the ieee 1149.1- 2001 shifter during the capture-dr state. when writing a register, the value is loaded from the ieee 1149.1-2001 shifter to the register duri ng the update-dr state. when reading a register, there is no requirement to shift out the entire register contents. shifting can be terminated after fetching the required number of bits. 32.8.4 jtagc instructions this section gives an overview of each instruction, refer to the ieee 1149.1 -2001 st andard for more details. the jtagc implements th e ieee 1149.1-2001 defined instructions listed in table 414 . bypass instruction bypass selects the bypass regist er, creating a single-bit shif t register path between tdi and tdo. bypass enhances test efficiency by redu cing the overall shift path when no test operation of the mcu is required. this allows more rapid movement of test data to and from other components on a board that are required to perform test functions. while the bypass instruction is active the system logic operates normally. access_aux_tap_ x instructions the access_aux_tap_ x instructions allow the nexu s modules on the mcu to take control of the tap. when this instruction is loaded, control of the tap pins is transferred to the selected auxiliary tap cont roller. any data input via tdi and tms is passed to the table 414. jtag instructions instruction code[4:0] instruction summary idcode 00001 selects device iden tification register for shift sample/preload 00010 selects boundary scan register for shifting, sampling, and preloading without disturbing functional operation sample 00011 selects boundary scan register for shifting and sampling without disturbing functional operation extest 00100 selects boundary scan register while applying preloaded values to output pins and asserting functional reset access_aux_tap_tcu 11011 grants the tcu ownership of the tap access_aux_tap_once 10001 grants the platform ownership of the tap access_aux_tap_npc 10000 grants the nexus port controller (npc) ownership of the tap reserved 10010 ? bypass 11111 selects bypass register for data operations factory debug reserved (1) 1. intended for factory debug, and not customer use 00101 00110 01010 intended for factory debug only reserved (2) 2. stmicroelectronics reserves the right to ch ange the decoding of reserved instruction codes all other codes decoded to select bypass register ieee 1149.1 test access port contro ller (jtagc) RM0017 775/904 doc id 14629 rev 8 selected tap controller, and any tdo output from the selected tap controller is sent back to the jtagc to be output on the pins. the jtagc regains control of the jtag port during the update-dr state if the pause-dr state was ente red. auxiliary tap controllers are held in run-test/idle while they are inactive. extest ? external test instruction extest selects the boundary scan register as the shift path between tdi and tdo. it allows testing of off-chip circuitry and board-level interconnections by driving preloaded data contained in the boundary scan register onto the system output pins. typically, the preloaded data is loaded into the boundary scan register using the sample/preload instruction before the select ion of extest. extest asserts th e internal system reset for the mcu to force a predictable internal state while performing external boundary scan operations. idcode instruction idcode selects the 32-bit device identification register as the shift path between tdi and tdo. this instruction allows interrogation of the mcu to determine its version number and other part identification data. idcode is the instruction placed into the instruction register when the jtagc is reset. sample instruction the sample instruction obtains a sample of the system data an d control signals present at the mcu input pins and just before the boundary scan register cells at the output pins. this sampling occurs on the rising edge of tck in the capture-dr state when the sample instruction is active. the sampled data is viewed by shifting it through the boundary scan register to the tdo output during the shift-dr state. there is no defined action in the update-dr state. both the data capture and the shift operation are transparent to system operation. during the sample instruction, the following pad status is enforced: weak pull is disabled (independent from pcrx[wpe]) analog switch is disabled (independent of pcrx[apc]) slew rate control is forced to the slowest configuration (independent from pcrx[src[1]]) sample/preload instruction the sample/preload instru ction has two functions: the sample part of the instruction samples the system data and control signals on the mcu input pins and just before the boundary scan register cells at the output pins. this sampling occurs on the rising-edge of tck in the capture-dr state when the sample/preload instruction is active. the sampled data is viewed by shifting it through the boundary scan register to the tdo output during the shift-dr state. both the data capture and the shift operation are transparent to system operation. the preload part of the instruction initializes the boundary scan register cells before selecting the extest instructions to perform boundary scan tests. this is achieved by shifting in initialization data to the boundary scan register during the shift-dr state. the initialization data is transferred to the parallel outputs of the boundary scan register cells on the falling edge of tck in the upda te-dr state. the data is applied to the external output pins by the extest instruction. system operation is not affected. RM0017 ieee 1149.1 test access port controller (jtagc) doc id 14629 rev 8 776/904 during the sample/preload instruction, the following pad status is enforced: weak pull is disabled (independent from pcrx[wpe]) analog switch is disabled (independent of pcrx[apc]) slew rate control is forced to the slowest configuration (independent from pcrx[src[1]]) 32.8.5 boundary scan the boundary scan technique allows signals at component boundaries to be controlled and observed through the shift-register stage associated with each pad. each stage is part of a larger boundary scan register cell, and cells for each pad are interconnected serially to form a shift-register chain around the border of the design. the boundary scan register consists of this shift-register chain, and is connected between tdi and tdo when the extest, sample, or sample/preload instructions are loaded. the shift-register chain contains a serial input and serial output, as well as clock and control signals. 32.9 e200z0 once controller the e200z0 core once controller supports a complete set of nexus 1 debug features, as well as providing access to the nexus2+ conf iguration registers. a complete discussion of the e200z0 once debug features is available in the e200z0 reference manual . 32.9.1 e200z0 once controller block diagram figure 427 is a block diagram of the e200z0 once block. ieee 1149.1 test access port contro ller (jtagc) RM0017 777/904 doc id 14629 rev 8 figure 427. e200z0 once block diagram 32.9.2 e200z0 once controller functional description the functional description for the e200z0 once controller is the same as for the jtagc, with the differences described below. enabling the tap controller to access the e200z0 once controller, the proper jtagc instruction needs to be loaded in the jtagc instruction register, as discussed in section tap sharing mode . 32.9.3 e200z0 once controller register description most e200z0 once debug registers are fully documented in the e200z0 reference manual . once command register (ocmd) the once command register (ocmd) is a 10-bit shift register that receives its serial data from the tdi pin and serves as the instruction register (ir). it holds the 10-bit commands to be used as input for the e200z0 once decoder. the ocmd is shown in table 428 . the ocmd is updated when the tap controller enters the update-ir state. it contains fields for controlling access to a resource, as well as c ontrolling single-step opera tion and exit from once mode. although the ocmd is updated during the update-ir tap controller state, the corresponding resource is accessed in the dr scan sequence of the tap controller, and as such, the tck e200z0_tms tdi test access port (tap) e200z0_tdo bypass register external data register . . controller tap instruction register . once mapped debug registers auxiliary data register . . . e200z0_trst (once ocmd) tdo mux control { from jtagc (to jtagc) RM0017 ieee 1149.1 test access port controller (jtagc) doc id 14629 rev 8 778/904 update-dr state must be transitioned through in order for an access to occur. in addition, the update-dr state must also be transitioned through in order for the single-step and/or exit functionality to be performed, even though the command appears to have no data resource requirement associated with it. figure 428. once command register (ocmd) 0123456789 r r/w go ex rs[0:6] w reset:0000011011 table 415. e200z0 once register addressing rs[0:6] register selected 000 0000 000 0001 reserved 000 0010 jtag id (read-only) 000 0011 ? 000 1111 reserved 001 0000 cpu scan register (cpuscr) 001 0001 no register selected (bypass) 001 0010 once control register (ocr) 001 0011 ? 001 1111 reserved 010 0000 instruction ad dress compare 1 (iac1) 010 0001 instruction ad dress compare 2 (iac2) 010 0010 instruction ad dress compare 3 (iac3) 010 0011 instruction ad dress compare 4 (iac4) 010 0100 data address compare 1 (dac1) 010 0101 data address compare 2 (dac2) 010 0110 data value compare 1 (dvc1) 010 0111 data value compare 2 (dvc2) 010 1000 ? 010 1111 reserved 011 0000 debug status register (dbsr) 011 0001 debug control register 0 (dbcr0) 011 0010 debug control register 1 (dbcr1) 011 0011 debug control register 2 (dbcr2) 011 0100 ? 101 1111 reserved (do not access) 110 1111 shared nexus control register (snc) (only available on the e200z0 core) 111 0000 ? 111 1001 general purpose register selects [0:9] 111 1010 ? 111 1011 reserved 111 1100 nexus2+ access ieee 1149.1 test access port contro ller (jtagc) RM0017 779/904 doc id 14629 rev 8 32.10 initialization/app lication information the test logic is a static logic design, and tck can be stopped in either a high or low state without loss of data. however, the system clock is not synchronized to tck internally. any mixed operation using both the test logic and the system functional logic requires external synchronization. to initialize the jtagc module and enable access to registers, the following sequence is required: 1. place the jtagc in reset through tap controller state machine transitions controlled by tms 2. load the appropriate instruction for the test or action to be performed. 111 1101 lsrl select (factory test use only) 111 1110 enable_once 111 1111 bypass table 415. e200z0 once regi ster addressing (continued) rs[0:6] register selected RM0017 nexus development interface (ndi) doc id 14629 rev 8 780/904 33 nexus development interface (ndi) 33.1 introduction the nexus development interface (ndi) block provides real-time development support capabilities for the spc560bx and spc560cx mcu in compliance with the ieee-isto 5001-2003 standard. this development support is supplied for mcus without requiring external address and data pi ns for internal visibility. the ndi block is an integration of several individual nexus blocks that are selected to provide the development support interface for spc560bx and spc560cx. the ndi block interfaces to the e200z0, and internal buses to provide development support as per the ieee-isto 5001-2003 standard. the development support provided includes program trace, watchpoint messaging, ownership trace, watchpoint triggering, processor overrun control, run-time access to the mcu?s internal memory map, and access to the e200z0 internal registers during halt, via the jtag port. 33.2 block diagram figure 429 shows a functional block diagram of the ndi. a simplified block diagram of the ndi illustrate s the functionality a nd interdependence of major blocks (see figure 430 ) and how the individual nexus blocks are combined to form the ndi. figure 429. ndi functional block diagram power-on tck evto mseo mdo reset message queue program trace ownership trace watchpoint trace cpu snoop message formatter arbiter divided system clock e200z1 trace information e200z0 trace information mcko input ta p controller control registers to trace blocks tdo tdi tms evti reset control nexus development interface (ndi) RM0017 781/904 doc id 14629 rev 8 figure 430. ndi implementation block diagram 33.3 features the ndi module of the spc560bx and spc560c x is compliant with class 2 of the ieee- isto 5001-2003 standard, with additional class 3 and class 4 features available.the following features are implemented: program trace via branch trace messaging (btm). branch trace messaging displays program flow discontinuities (direct and indirect branches, exceptions, etc.), allowing the development tool to interpolate what transpires between the discontinuities. thus static code may be traced. ownership trace via ownership trace messaging (otm). otm facilitates ownership trace by providing visibility of which proce ss id or operating system task is activated. tdo cross-bar power-on mcko evto mdo[3:0] mseo cpu reset bp/wp control once/ nexus1 ta p program/ ownership register control read/write access message fifo message transmitter nexus2+ interface auxiliary port arbitration/ muxing reset control ta p register control clock control e200z0 nexus port controller tdo muxing jtag controller tdi evti tms nexus development interface z0_tdo z0_tms z0_tdi tclk trace tdi ta p npc_tms z0_tdo z0_tms npc_tdo access auxiliary ta p npc_tdo npc_tms tdi, tclk tck RM0017 nexus development interface (ndi) doc id 14629 rev 8 782/904 an ownership trace message is transmitted when a new process/task is activated, allowing the development tool to trace ownership flow. watchpoint messaging via the auxiliary pins watchpoint trigger enable of program trace messaging auxiliary interface for hi gher data input/output ? 4 message data out pins ? 1 message start/end out pins (mseo) ? 1 watchpoint event pin (evto) ? 1 event-in pin (evti) ? 1 message clock out pin (mcko) ? 4-pin jtag port (tdi, tdo, tms, and tck) registers for program trace, ownership trace, and watchpoint trigger. all features controllable and configurable via the jtag port. run-time access to the on-chip memory map via the nexus read/write access protocol. this allows for enhanced download/upload capabilities. all features are indep endently configurable and contro llable via the ieee 1149.1 i/o port. the ndi block reset is controlled with power-on reset, and the tap state machine. all these sources are independent of system reset. support for internal censorship mode to prevent external access to flash memory contents when censorship is enabled. note: if the e200z0 cores has executed a wait instruction, then the nexus2+ controller clocks are gated off. while the core is in this state, it is not be possible to perform nexus read/write operations. 33.4 modes of operation the ndi block is in reset when the tap cont roller state machine is in the test-logic- reset state. the test-logic-r eset state is entered on the assertion of the power-on reset signal or through state machine transitions controlled by tms. ownership of the tap is achieved by loading the appropriate enable instruction for the desired nexus client in the jtagc controller (jtagc) block. the nexus port controller (npc) transitions out of the reset state immediately following negation of power-on reset. 33.4.1 nexus reset in nexus reset mode, the following actions occur: register values default back to their reset values. the message queues are marked as empty. the auxiliary output port pins are n egated if the ndi co ntrols the pads. the tdo output buffer is disabled if the ndi has control of the tap. the tdi, tms, and tck inputs are ignored. the ndi block indicates to the mcu that it is not using t he auxiliary output port. this indication can be used to three-state the outp ut pins or use them for another function. nexus development interface (ndi) RM0017 783/904 doc id 14629 rev 8 33.4.2 operating mode in full-port mode, all available mdo pins are used to transmit messages. all trace features are enabled or can be enabled by writing the configuration registers via the jtag port. four mdo pins are available in full-port mode. disabled-port mode in disabled-port mode, message transmission is disabled. any debug feature that generates messages can not be used. the primary features available are class 1 features and read/write access. censored mode the ndi supports internal flash censorship mode by preventing the transmission of trace messages and nexus access to memory-mapped resources when censorship is enabled. stop mode stop mode logic is implemented in the npc. when a request is made to enter stop mode, the ndi block completes monitoring of any pending bus transaction, transmits all messages already queued, and acknowledges the stop request. after the acknowledgment, the system clock input are shut off by the clock driver on the device. while the clocks are shut off, the development tool cannot access ndi registers via the jtag port. 33.5 external signal description all the signals are available in the 208bga without any multiplexing scheme. refer to chapter 4 signal description for details. 33.5.1 nexus signal reset states 33.6 memory map and register description the ndi block contains no memory-mapped registers. nexus registers are accessed by a development tool via the jtag port using a client-select value and a register index. once registers are accessed by loading the appropriate value in the rs[0:6] field of the once command register (ocmd) via the jtag port. table 416. ndi signal reset state name function nexus reset state pull evti event-in pin ? up evto event-out pin 0b1 ? mcko message clock out pin 0b0 ? mdo[3:0] message data out pins 0 ? mseo message start/end out pin 0b1 ? RM0017 nexus development interface (ndi) doc id 14629 rev 8 784/904 33.6.1 nexus debug interface registers table 417 shows the ndi registers by client select and index values. once register addressing is documented in the jtagc chapter of this reference manual. table 417. nexus debug interface registers client select index register location client-independent registers 0bxxxx 0 nexus device id (did) register (1) 1. implemented in npc block. all other re gisters implemented in e200z0 nexus2+ block. on page 33-785 0bxxxx 127 port configuration register (pcr) (1) on page 33-786 e200z0 control/status registers 0b0000 2 development control register 1 (dc1) on page 33-788 0b0000 3 development control register 2 (dc2) on page 33-788 0b0000 4 development status (ds) register on page 33-790 0b0000 7 read/write access control/status (rwcs) register on page 33-792 0b0000 9 read/write access address (rwa) register on page 33-793 0b0000 10 read/write access data (rwd) register on page 33-794 0b0000 11 watchpoint trigger (wt) register on page 33-794 nexus development interface (ndi) RM0017 785/904 doc id 14629 rev 8 33.6.2 register description this section lists the ndi registers and describes the registers and their bit fields. nexus device id (did) register the npc device identification register, shown in figure 431 , allows the part revision number, design center, part identification number, and manufacturer identity code of the device to be determined throug h the auxiliary output port, and serially through tdo. this register is read-only. figure 431. nexus device id (did) register reg index: 0 access: user read only 0123456789101112131415 r part revision number design center part identification number w reset (1) 1. part revision number default value is 0x0 for the devic e?s initial mask set and changes for each mask set revision. * * * *100000010001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r part identification number ( continued ) manufacturer identity code 1 w reset0110000001000001 table 418. did field descriptions field description 0?3 prn part revision number contains the revision number of the part. this fi eld changes with each revision of the device or module. 4?9 dc design center 10?19 pin part identification number contains the part number of the device. 20?30 mic manufacturer identity code contains the reduced joint electron device engi neering council (jedec) idfor stmicroelectronics, 0x20. 31 fixed per jtag 1149.1 always set to 1. RM0017 nexus development interface (ndi) doc id 14629 rev 8 786/904 port configuration register (pcr) the pcr is used to select the npc mode of operation, enable mcko and select the mcko frequency, and enable or disable mcko gating. this register should be configured as soon as the ndi is enabled. the pcr register may be rewritten by the debug tool subsequent to the enabling of the npc for low power debug support. in this case, the debug tool may set and clear the lp_dbg_en, sleep_sync, and stop_sync bits, but must preserve the original state of the remaining bits in the register. note: the mode or clock division must not be modified after mcko has been enabled. changing the mode or clock division while mcko is enabled can produce unpredictable results. figure 432. port configuration register (pcr) reg index: 127 access: user read/write 0123456789101112131415 r fpm mcko _gt mcko _en mcko_div evt _en 000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rlp_ dbg_ en 00000 sleep _sync stop_ sync 0000000 pstat _en w reset0000000000000000 table 419. pcr field descriptions field description 0 fpm full port mode the value of the fpm bit determines if the auxiliary output port uses the full mdo port or a reduced mdo port to transmit messages. 0 a subset of mdo pins are used to transmit messages. 1 all mdo pins are used to transmit messages. 1 mcko_gt mcko clock gating control this bit is used to enable or disable mcko clock gating. if clock gating is enabled, the mcko clock is gated when the npc is in enabled mode but no t actively transmitting messages on the auxiliary output port. when clock gating is disabled, mcko is allowed to run even if no auxiliary output port messages are being transmitted. 0 mcko gating is disabled. 1 mcko gating is enabled. 2 mcko_en mcko enable this bit enables the mcko clock to run. when enabled, the frequency of mcko is determined by the mcko_div field. 0 mcko clock is driven to zero. 1 mcko clock is enabled. nexus development interface (ndi) RM0017 787/904 doc id 14629 rev 8 3?5 mcko_div [2:0] mcko division factor the value of this signal determines the frequency of mcko relati ve to the system clock frequency when mcko_en is asserted. sys_clk r epresents the system clock frequency: note: mcko_div value and associated mcko frequency should be configured taking into account the frequency limitation of the associat ed mcko pad. please refer to datasheet io section. 6 evt_en evto/evti enable this bit enables the evto/evti port functions. 0 evto/evti port disabled 1 evto/evti port enabled 7?15 reserved 16 lp_dbg_en low power debug enable the lp_dbg_en bit enables debug functionality to support entry and exit from low power sleep and stop modes. 0 low power debug disabled 1 low power debug enabled 17?21 reserved 22 sleep_sync sleep mode synchronization the sleep_sync bit is used to synchronize the entry into sleep mode between the device and debug tool. the device sets this bit before a pending entry into sleep mode. after reading sleep_sync as set, the debug tool then clears sleep_sync to acknowledge to the device that it may enter into sleep mode. 0 sleep mode entry acknowledge 1 sleep mode entry pending 23 stop_sync stop mode synchronization the stop_sync bit is used to synchronize the entry into stop mode between the device and debug tool. the device sets this bit before a pending entry into stop mode. after reading stop_sync as set, the debug tool then clears stop_sync to acknowledge to the device that it may enter into stop mode. 0 stop mode entry acknowledge 1 stop mode entry pending 24?30 reserved 31 pstat_en processor status mode enable table 419. pcr field descriptions (continued) field description table 0-1 value mcko frequency 0b000 sys_clk 0b001 sys_clk 2 (default value if a reserved encoding is programmed) 0b010 reserved 0b011 sys_clk 4 RM0017 nexus development interface (ndi) doc id 14629 rev 8 788/904 development control register 1, 2 (dc1, dc2) the development control registers are used to control the basic development features of the nexus module. figure 433 shows development control register 1 and table 420 describes the register?s fields. figure 433. development control register 1 (dc1) nexus reg: 0x0002 access: user read/write 0123456789101112131415 r opc mck_div eoc 0 ptm wen 00000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ovc eic tm w reset0000000000000000 table 420. dc1 field descriptions field description 0 opc (1) output port mode control 0 reduced-port mode configuration (2 mdo pins) 1 full-port mode configuration (4 mdo pins) 1?2 mck_div[1:0] (1) mcko clock divide ratio (see note below) 00 mcko is 1x processor clock freq. 01 mcko is 1/2x processor clock freq. 10 mcko is 1/4x processor clock freq. 11 mcko is 1/8x processor clock freq. 3?4 eoc[1:0] evto control 00 evto upon occurrence of watchpoints (configured in dc2) 01 evto upon entry into debug mode 10 evto upon timestamping event 11 reserved 5 reserved 6 ptm program trace method 0 program trace uses traditional branch messages. 1 program trace uses branch history messages. 7 wen watchpoint trace enable 0 watchpoint messaging disabled 1 watchpoint messaging enabled 8?23 reserved nexus development interface (ndi) RM0017 789/904 doc id 14629 rev 8 development control register 2 is shown in figure 434 and its fields are described in table 421 . 24?26 ovc[2:0] overrun control 000 generate overrun messages. 001?010 reserved 011 delay processor for btm / dtm / otm overruns. 1xx reserved 27?28 eic[1:0] evti control 00 evti is used for synchronization (program trace/ data trace) 01 evti is used for debug request 1x reserved 29?31 tm[2:0] trace mode any or all of the tm bits may set, enabling one or more traces. 000 no trace 1xx program trace enabled x1x data trace enabled (not supported mode) xx1 ownership trace enabled 1. the output port mode control bit (opc) and mcko divide bits (mck_div) are show n for clarity. these functions are controlled globally by the npc port contro l register (pcr). these bits are writ able in the pcr but have no effect. table 420. dc1 field d escriptions (continued) field description figure 434. development control register 2 (dc2) nexus reg: 0x0003 access: user read/write 0123456789101112131415 r ewc 00000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 RM0017 nexus development interface (ndi) doc id 14629 rev 8 790/904 note: the eoc bits in dc1 must be programmed to trigger evto on watchpoint occurrence for the ewc bits to have any effect. development status (ds) register the development status register is used to report system debug status. when debug mode is entered or exited, or a core-defined low-power mode is entered, a debug status message is transmitted with ds[31:24]. the external t ool can read this register at any time. table 421. dc2 field descriptions field description 0?7 ewc[7:0] evto watchpoint configuration any or all of the bits in ewc may be set to configure the evto watchpoint. 00000000no watchpoints trigger evto 1xxxxxxxwatchpoint #0 (iac1 from nexus1) triggers evto. x1xxxxxxwatchpoint #1 (iac2 from nexus1) triggers evto. xx1xxxxxwatchpoint #2 (iac3 from nexus1) triggers evto. xxx1xxxxwatchpoint #3 (iac4 from nexus1) triggers evto. xxxx1xxxwatchpoint #4 (dac1 from nexus1) triggers evto. xxxxx1xxwatchpoint #5 (dac2 from nexus1) triggers evto. xxxxxx1xwatchpoint #6 (dcnt1 from nexus1) triggers evto. xxxxxxx1watchpoint #7 (dcnt2 from nexus1) triggers evto. 8?31 reserved figure 435. development status (ds) register nexus reg: 0x0004 access: user read only 0123456789101112131415 r dbg000 lpc chk000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 table 422. ds field descriptions field description 0 dbg cpu debug mode status 0 cpu not in debug mode 1 cpu in debug mode 1?3 reserved nexus development interface (ndi) RM0017 791/904 doc id 14629 rev 8 4?5 lpc[1:0] cpu low-power mode status 00 normal (run) mode 01 cpu in halted state 10 cpu in stopped state 11 reserved 6 chk cpu checkstop status 0 cpu not in checkstop state 1 cpu in checkstop state 7?31 reserved table 422. ds field descriptions (continued) field description RM0017 nexus development interface (ndi) doc id 14629 rev 8 792/904 read/write access control/status (rwcs) register the read write access control/status regist er provides control for read/write access. read/write access provides dma-like access to memory-mapped resources on the system bus while the processor is halted or during runtime. the rwcs register also provides read/write access status information as shown in ta b l e 4 2 4 . figure 436. read/write access control/status (rwcs) register nexus reg: 0x0007 access: user read/write 0123456789101112131415 r ac rw sz map pr bst 00000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cnt err dv w reset0000000000000000 table 423. rwcs field descriptions field description 0 ac access control 0 end access. 1 start access. 1 rw read/write select 0 read access 1 write access 2?4 sz[2:0] word size 000 8-bit (byte) 001 16-bit (halfword) 010 32-bit (word) 011 64-bit (doubleword?only in burst mode) 100?111 reserved (default to word) 5?7 map[2:0] map select 000 primary memory map 001?111 reserved 8?9 pr[1:0] read/write access priority 00 lowest access priority 01 reserved (default to lowest priority) 10 reserved (default to lowest priority) 11 highest access priority 10 bst burst control 0 module accesses are single bus cycle at a time. 1 module accesses are performed as burst operation. 11?15 reserved nexus development interface (ndi) RM0017 793/904 doc id 14629 rev 8 table 424 details the status bit encodings. read/write access address (rwa) register the read/write access address register prov ides the system bus address to be accessed when initiating a read or a write access. 16?31 cnt[13:0] access control count number of accesses of word size sz 30 err read/write access error see ta bl e 4 2 4 . 31 dv read/write access data valid see ta bl e 4 2 4 . table 423. rwcs field descriptions (continued) field description table 424. read/write access status bit encoding read action write action err dv read access has not completed write access completed without error 0 0 read access error has occurred w rite access error has occurred 1 0 read access completed without erro r write access has not completed 0 1 not allowed not allowed 1 1 figure 437. read/write access address (rwa) register nexus reg: 0x0009 access: user read/write 0123456789101112131415 r rwa[0-15] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rwa[16-31] w reset0000000000000000 RM0017 nexus development interface (ndi) doc id 14629 rev 8 794/904 read/write access data (rwd) register the read/write access data register provides the data to/from system bus memory-mapped locations when initiating a read or a write access. watchpoint trigger (wt) register the watchpoint trigger register allows the watchpoints defined within the nexus1 logic to trigger actions. these watchpoints can control program and/or data trace enable and disable. the wt bits can be used to produce an address-related window for triggering trace messages. table 425 details the watchpoint trigger register fields. figure 438. read/write access data (rwd) register nexus reg: 0x000a access: user read/write 0123456789101112131415 r rwd[0-15] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rwd[16-31] w reset0000000000000000 figure 439. watchpoint trigger (wt) register nexus reg: 0x000b access: user read/write 0123456789101112131415 r pts pte 0000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 nexus development interface (ndi) RM0017 795/904 doc id 14629 rev 8 33.7 functional description the ndi block is implemented by integrating the following blocks on the spc560bx and spc560cx: nexus e200z0 development interface (once and nexus2p subblocks) nexus port controller (npc) block npc_hndshk module 33.7.1 npc_hndshk module this module enables debug entry/exit acro ss low power modes (stop, halt, standby). the npc_hndshk supports: setting and clearing of the npc pcr sync bit on low-power mode entry and exit putting the core into debug mode on low-power mode exit generating a falling edge on the jtag tdo pad on low-power mode exit on halt, stop, or standby mode entry, the mc_me asserts the lp_mode_entry_req input after the clock disable process has completed and before the processor enters its halted or stopped state. the mode transition will then not proceed until the lp_mode_entry_ack output has been asserted. the notification to the debugger of a low- power mode entry consists of setting the low-power mode handshake bit in the port control register (read by the debugger) via the lp_sync_in output. the debugger acknowledges that the transition into a low-power mode may proceed by clearing the low-power mode handshake bit in the port control register (written by the debugger), which results in the deassertion of the lp_sync_out input. in anticipation of the low-power mode exit notification, the tdo pad is driven to `1'. table 425. wt field descriptions field description 0?2 pts[2:0] program trace start control 000 trigger disabled 001 use watchpoint #0 (iac1 from nexus1). 010 use watchpoint #1 (iac2 from nexus1). 011 use watchpoint #2 (iac3 from nexus1). 100 use watchpoint #3 (iac4 from nexus1). 101 use watchpoint #4 (dac1 from nexus1). 110 use watchpoint #5 (dac2 from nexus1). 111 use watchpoint #6 or #7 (dcnt1 or dcnt2 from nexus1). 3?5 pte[2:0] program trace end control 000 trigger disabled 001 use watchpoint #0 (iac1 from nexus1). 010 use watchpoint #1 (iac2 from nexus1). 011 use watchpoint #2 (iac3 from nexus1). 100 use watchpoint #3 (iac4 from nexus1). 101 use watchpoint #4 (dac1 from nexus1). 110 use watchpoint #5 (dac2 from nexus1). 111 use watchpoint #6 or #7 (dcnt1 or dcnt2 from nexus1). 12?31 reserved RM0017 nexus development interface (ndi) doc id 14629 rev 8 796/904 on halt or stop mode exit, the mc_me asserts the lp_mode_exit_req input after ensuring that the regulator and memories are in normal mode and before the processor exits its halted or stopped state. the mode transition will then not proceed until the lp_mode_exit_ack output has been asserted. the mc_rgm asserts the exit_from_standby input when executing a rese t sequence due to a standby exit. the reset sequence will then not complete until the lp_mode_exit_ack output has been asserted. the notification to the debugger of a low-power mode exit consists of driving the tdo pad to `0'. the debugger acknowledges that the transition from a low-power mode can continue by setting the low-power mode sync bit in the port control register (written by debugger), which results in the assertion of the lp_sync_out input. note: the debugger clock multiplexer may not guarantee glitch free switching. therefore, tck should be disabled from when the debugger clears the sync bit in entry_clr until the debugger senses the falling edge of tdo in tdo_set. 33.7.2 enabling nexus cl ients for tap access after the conditions have been met to bring the ndi out of the reset state, the loading of a specific instruction in the jtag controller (jtagc) block is required to grant the ndi ownership of the tap. each nexus client has its own jtagc instruction opcode for ownership of the tap, granting that client the means to read/write its registers. the jtagc instruction opcode for each nexus client is shown in ta bl e 4 2 6 . after the jtagc opcode for a client has been loaded, the client is enab led by loading its nexu s-enable instruction. the nexus-enable instruction opcode for each nexus client is listed in ta b l e 4 2 7 . opcodes for all other instructions supported by nexus clients can be found in the relevant sections of this chapter. 33.7.3 configuring the nd i for nexus messaging the ndi is placed in disabled mode upon exit of reset. if message transmission via the auxiliary port is desired, a write to the port configuration register (p cr) located in the npc table 426. jtagc instruction opcodes to enable nexus clients jtagc instruction opcode description access_aux_tap_npc 10000 enables access to the npc tap controller access_aux_tap_once 10001 enables a ccess to the e200z0 tap controller table 427. nexus client jtag instructions instruction description opcode npc jtag instruction opcodes nexus_enable opcode for npc nexu s enable instruction (4-bits) 0x0 bypass opcode for the npc byp ass instruction (4-bits) 0xf e200z0 once jtag instruction opcodes (1) 1. refer to the e200z0 reference manual for a comp lete list of available once instructions. nexus2_access opcode for e200z0 once nexu s enable instruction (10-bits) 0x7c bypass opcode for the e200z0 once bypass instruction (10-bits) 0x7f nexus development interface (ndi) RM0017 797/904 doc id 14629 rev 8 is then required to enable the ndi and select the mode of operation. asserting mcko_en in the pcr places the ndi in enabled mode and enables mcko. the frequency of mcko is selected by writing the mcko_div field. asserting or negating the fpm bit selects full-port or reduced-port mode, respectively. when writing to the pcr, the pcr lsb must be written to a logic zero. setting the lsb of the pcr enables factory debug mode and prevents the transmission of nexus messages. table 428 describes the ndi configuration options. 33.7.4 programmable mcko frequency mcko is an output clock to the development tools used for the timing of mseo and mdo pin functions. mcko is derived from the system clock, and its frequency is determined by the value of the mcko_div field in the port configuration register (pcr) located in the npc. possible operating frequencies include one-quarter and one-eighth system clock speed. refer to the mcko_div [2:0] field description in ta b l e 4 1 9 for the mcko_div encodings, where sys_clk represents the sy stem clock frequency. the de fault value selected if a reserved encoding is programmed is sys_clk 2. 33.7.5 nexus messaging most of the messages transmitted by the ndi include an src field. this field is used to identify which source generated the message. ta bl e 4 2 9 shows the values used for the src field by the different clients on the spc560bx and spc560cx. these values are specific to the spc560bx and spc560cx. the size of the s rc field in transmitted messages is 4 bits. this value is also specific to the spc560bx and spc560cx. 33.7.6 evto sharing the npc block controls sharing of the evto output between all nexus clients that generate an evto signal. the sharing mechanism is a logical and of all incoming evto signals from nexus blocks, thereby asserting evto whenever any block drives its evto. when there is no active mcko, such as in disabled mode, the npc drives evto for two system clock periods. evto sharing is active as long as the ndi is not in reset. table 428. ndi configuration options mcko_en bit of pcr fpm bit of pcr configuration 0xdisabled 1 1 full-port mode 1 0 reduced port mode table 429. src packet encodings src[3:0] spc560bx and spc560cx client 0b0000 e200z0 all other combinations reserved RM0017 nexus development interface (ndi) doc id 14629 rev 8 798/904 33.7.7 debug mode control on spc560bx and spc560cx, program breaks can be requested either by using the evti pin as a break request, or when a nexus event is triggered. evti generated break request to use the evti pin as a debug request, the eic field in the e200z0 nexus2+ development control register 1 (dc1[4:3]) must be set to configure the evti input as a debug request. 33.7.8 ownership trace overview ownership trace provides a macroscopic view , such as task flow reconstruction, when debugging software written in a high level (or object-oriented) language. it offers the highest level of abstraction for tracking operating system software execution. this is especially useful when the developer is not intere sted in debugging at lower levels. ownership trace messaging (otm) ownership trace information is messaged via t he auxiliary port using an ownership trace message (otm). the e200z0h processor contains a power architecture platform defined process id register within the cpu. the process id register is updated by the operating system software to provide task/process id information. the contents of this register are replicated on the pins of the processor and connected to nexus. the process id register value can be accessed using the mfspr / mtspr instructions. there is one condition wh ich will cause an ownership trace message: when new information is updated in the otr register or process id register by the e200z0h processor, the data is latched within nexus, and is messaged out via the auxiliary port, allowing development tools to trace ownership flow. ownership trace information is messaged out in the following format: figure 440. ownership trace message format otm error messages an error message occurs when a new message cannot be queued due to the message queue being full. the fifo will discard incoming messages until it has completely emptied the queue. once emptied, an error message will be queued. the er ror encoding will indicate which types of messages attempted to be queued while the fifo was being emptied. if only an otm message attempts to enter the queue while it is being emptied, the error message will incorporate the otm only error enco ding (00000). if both otm and either btm or dtm messages attemp t to enter the queue, the erro r message will incorporate the otm process msb lsb 1 2 src tcode (000010) 3 6 bits 4 bits 32 bits fixed length = 42 bits nexus development interface (ndi) RM0017 799/904 doc id 14629 rev 8 and (program or data) trace error encoding (00111). if a watchpoint also attempts to be queued while the fifo is be ing emptied, then the error message will incorporate error encoding (01000). note: the ovc bits within the dc1 register can be set to delay the cpu in order to alleviate (but not eliminate) potential overrun situations. error information is messaged out in the following format (see ta bl e 4 3 0 ) figure 441. error message format otm flow ownership trace messages are generated when the operating system writes to the e200z0h process id register or the memory mapped ownership trace register. the following flow describes the otm process: 1. the process id register is a system control register. it is internal to the e200z0h processor and can be accessed by using ppc instructions mtspr and mfspr . the table 430. error code encoding (tcode = 8) error code (ecode) description 00000 ownership trace overrun 00001 program trace overrun 00010 data trace overrun 00011 read/write access error 00101 invalid access opcode (nexus register unimplemented) 00110 watchpoint overrun 00111 (program trace or data trace) and ownership trace overrun 01000 (program trace or data trace or ow nership trace) and watchpoint overrun 01001?0111 reserved 11000 btm lost due to collision w/ higher priority message 11001?11111 reserved ecode (00000 / 00111 / 01000) msb lsb 1 2 src tcode (001000) 3 6 bits 4 bits 5 bits fixed length = 15 bits RM0017 nexus development interface (ndi) doc id 14629 rev 8 800/904 contents of this register are replicated on the pins of the proces sor and connected to nexus. 2. otr/process id register reads do not cause ownership trace messages to be transmitted by the nz0h module. 3. if the periodic otm message counter expires (after 255 queued messages without an otm), an otm is sent using the latched data from the previous otm or process id register write. register map RM0017 801/904 doc id 14629 rev 8 appendix a register map table 431. module base addresses module name base addresses page code flash a configuration 0xc3f8_8000 on page a-802 data flash a configuration 0xc3f8_c000 on page a-802 system integration unit lite (siul) 0xc3f9_0000 on page a-803 wakeup unit 0xc3f9_4000 on page a-803 emios_0 0xc3fa_0000 on page a-811 emios_1 0xc3fa_4000 on page a-816 system status and configurati on module (sscm) 0xc3fd_8000 on page a-822 mode entry module (mc_me) 0xc3fd_c000 on page a-822 fxosc 0xc3fe_0000 on page a-825 sxosc 0xc3fe_0040 on page a-825 firc 0xc3fe_0060 on page a-825 sirc 0xc3fe_0080 on page a-825 fmpll 0xc3fe_00a0 on page a-825 cmu 0xc3fe_0100 on page a-825 clock generation module (mc_cgm) 0xc3fe_0370 on page a-825 reset generation module (mc_rgm) 0xc3fe_4000 on page a-826 power control unit (mc_pcu) 0xc3fe_8000 on page a-826 real time counter (rtc/api) 0xc3fe_c000 on page a-826 periodic interrupt timer (pit) 0xc3ff_0000 on page a-827 adc 0xffe0_0000 on page a-827 i2c 0xffe3_0000 on page a-831 linflex_0 0xffe4_0000 on page a-831 linflex_1 0xffe4_4000 on page a-832 linflex_2 0xffe4_8000 on page a-833 linflex_3 0xffe4_c000 on page a-833 ctu 0xffe6_4000 on page a-834 can sampler 0xffe7_0000 on page a-836 mpu 0xfff1_0000 on page a-836 swt 0xfff3_8000 on page a-837 stm 0xfff3_c000 on page a-837 ecsm 0xfff4_0000 on page a-838 intc 0xfff4_8000 on page a-839 RM0017 register map doc id 14629 rev 8 802/904 dspi_0 0xfff9_0000 on page a-841 dspi_1 0xfff9_4000 on page a-842 dspi_2 0xfff9_8000 on page a-843 flexcan_0 (can0) 0xfffc_0000 on page a-844 flexcan_1 (can1) 0xfffc_4000 on page a-850 flexcan_2 (can2) 0xfffc_8000 on page a-855 flexcan_3 (can3) 0xfffc_c000 on page a-861 flexcan_4 (can4) 0xfffd_0000 on page a-866 flexcan_5 (can5) 0xfffd_4000 on page a-872 table 432. detailed register map register description register name used size address code flash a configuration 0xc3f8_8000 module configuration register cflash_mcr 32-bit base + 0x0000 low/mid address space block locking register cflash_lml 32-bit base + 0x0004 high address space block locking register cflash_hbl 32-bit base + 0x0008 secondary low/mid address space block locking register cflash_sll 32-bit base + 0x000c low/mid address space block select register cflash_lms 32-bit base + 0x0010 high address space block select register cflash_hbs 32-bit base + 0x0014 address register cflash_adr 32-bit base + 0x0018 bus interface unit register 0 cflash_biu0 32-bit base + 0x001c bus interface unit register 1 cflash_biu1 32-bit base + 0x0020 bus interface unit register 2 cflash_biu2 32-bit base + 0x0024 reserved ? ? (base + 0x0028) ? (base + 0x003b) user test register 0 cflash_ut0 32-bit base + 0x003c user test register 1 cflash_ut1 32-bit base + 0x0040 user test register 2 cflash_ut2 32-bit base + 0x0044 user multiple input signature register 0 cflash_umisr0 32-bit base + 0x0048 user multiple input signature register 1 cflash_umisr1 32-bit base + 0x004c user multiple input signature register 2 cflash_umisr2 32-bit base + 0x0050 user multiple input signature register 3 cflash_umisr3 32-bit base + 0x0054 user multiple input signature register 4 cflash_umisr4 32-bit base + 0x0058 data flash a configuration 0xc3f8_c000 table 431. module base addresses (continued) module name base addresses page register map RM0017 803/904 doc id 14629 rev 8 module configuration register dflash_mcr 32-bit base + 0x0000 low/mid address space block locking register dflash_lml 32-bit base + 0x0004 high address space block locking register dflash_hbl 32-bit base + 0x0008 secondary low/mid address space block locking register dflash_sll 32-bit base + 0x000c low/mid address space block select register dflash_lms 32-bit base + 0x0010 high address space block select register dflash_hbs 32-bit base + 0x0014 address register dflash_adr 32-bit base + 0x0018 reserved ? ? (base + 0x001c) ? (base + 0x003b) user test register 0 dflash_ut0 32-bit base + 0x003c user test register 1 dflash_ut1 32-bit base + 0x0040 user test register 2 dflash_ut2 32-bit base + 0x0044 user multiple input signature register 0 dflash_umisr0 32-bit base + 0x0048 user multiple input signature register 1 dflash_umisr1 32-bit base + 0x004c user multiple input signature register 2 dflash_umisr2 32-bit base + 0x0050 user multiple input signature register 3 dflash_umisr3 32-bit base + 0x0054 user multiple input signature register 4 dflash_umisr4 32-bit base + 0x0058 system integration unit lite (siu l) 0xc3f9_0000 reserved ? ? base + (0x0000 ? 0x0003) mcu id register 1 midr1 32-bit base + 0x0004 mcu id register 2 midr2 32-bit base + 0x0008 reserved ? ? base + (0x000c ? 0x0013) interrupt status flag register isr 32-bit base + 0x0014 interrupt request enable register irer 32-bit base + 0x0018 reserved ? ? base + (0x001c ? 0x0027) interrupt rising edge event enable ireer 32-bit base + 0x0028 interrupt falling-edge event enable ifeer 32-bit base + 0x002c ifer interrupt filter enable register ifer 32-bit base + 0x0030 reserved ? ? base + (0x0034 ? 0x003f) pad configuration register 0 pcr0 16-bit base + 0x0040 pad configuration register 1 pcr1 16-bit base + 0x0042 pad configuration register 2 pcr2 16-bit base + 0x0044 table 432. detailed register map (continued) register description register name used size address RM0017 register map doc id 14629 rev 8 804/904 pad configuration register 3 pcr3 16-bit base + 0x0046 pad configuration register 4 pcr4 16-bit base + 0x0048 pad configuration register 5 pcr5 16-bit base + 0x004a pad configuration register 6 pcr6 16-bit base + 0x004c pad configuration register 7 pcr7 16-bit base + 0x004e pad configuration register 8 pcr8 16-bit base + 0x0050 pad configuration register 9 pcr9 16-bit base + 0x0052 pad configuration register 10 pcr10 16-bit base + 0x0054 pad configuration register 11 pcr11 16-bit base + 0x0056 pad configuration register 12 pcr12 16-bit base + 0x0058 pad configuration register 13 pcr13 16-bit base + 0x005a pad configuration register 14 pcr14 16-bit base + 0x005c pad configuration register 15 pcr15 16-bit base + 0x005e pad configuration register 16 pcr16 16-bit base + 0x0060 pad configuration register 17 pcr17 16-bit base + 0x0062 pad configuration register 18 pcr18 16-bit base + 0x0064 pad configuration register 19 pcr19 16-bit base + 0x0066 pad configuration register 20 pcr20 16-bit base + 0x0068 pad configuration register 21 pcr21 16-bit base + 0x006a pad configuration register 22 pcr22 16-bit base + 0x006c pad configuration register 23 pcr23 16-bit base + 0x006e pad configuration register 24 pcr24 16-bit base + 0x0070 pad configuration register 25 pcr25 16-bit base + 0x0072 pad configuration register 26 pcr26 16-bit base + 0x0074 pad configuration register 27 pcr27 16-bit base + 0x0076 pad configuration register 28 pcr28 16-bit base + 0x0078 pad configuration register 29 pcr29 16-bit base + 0x007a pad configuration register 30 pcr30 16-bit base + 0x007c pad configuration register 31 pcr31 16-bit base + 0x007e pad configuration register 32 pcr32 16-bit base + 0x0080 pad configuration register 33 pcr33 16-bit base + 0x0082 pad configuration register 34 pcr34 16-bit base + 0x0084 pad configuration register 35 pcr35 16-bit base + 0x0086 pad configuration register 36 pcr36 16-bit base + 0x0088 table 432. detailed register map (continued) register description register name used size address register map RM0017 805/904 doc id 14629 rev 8 pad configuration register 37 pcr37 16-bit base + 0x008a pad configuration register 38 pcr38 16-bit base + 0x008c pad configuration register 39 pcr39 16-bit base + 0x008e pad configuration register 40 pcr40 16-bit base + 0x0090 pad configuration register 41 pcr41 16-bit base + 0x0092 pad configuration register 42 pcr42 16-bit base + 0x0094 pad configuration register 43 pcr43 16-bit base + 0x0096 pad configuration register 44 pcr44 16-bit base + 0x0098 pad configuration register 45 pcr45 16-bit base + 0x009a pad configuration register 46 pcr46 16-bit base + 0x009c pad configuration register 47 pcr47 16-bit base + 0x009e pad configuration register 48 pcr48 16-bit base + 0x00a0 pad configuration register 49 pcr49 16-bit base + 0x00a2 pad configuration register 50 pcr50 16-bit base + 0x00a4 pad configuration register 51 pcr51 16-bit base + 0x00a6 pad configuration register 52 pcr52 16-bit base + 0x00a8 pad configuration register 53 pcr53 16-bit base + 0x00aa pad configuration register 54 pcr54 16-bit base + 0x00ac pad configuration register 55 pcr55 16-bit base + 0x00ae pad configuration register 56 pcr56 16-bit base + 0x00b0 pad configuration register 57 pcr57 16-bit base + 0x00b2 pad configuration register 58 pcr58 16-bit base + 0x00b4 pad configuration register 59 pcr59 16-bit base + 0x00b6 pad configuration register 60 pcr60 16-bit base + 0x00b8 pad configuration register 61 pcr61 16-bit base + 0x00ba pad configuration register 62 pcr62 16-bit base + 0x00bc pad configuration register 63 pcr63 16-bit base + 0x00be pad configuration register 64 pcr64 16-bit base + 0x00c0 pad configuration register 65 pcr65 16-bit base + 0x00c2 pad configuration register 66 pcr66 16-bit base + 0x00c4 pad configuration register 67 pcr67 16-bit base + 0x00c6 pad configuration register 68 pcr68 16-bit base + 0x00c8 pad configuration register 69 pcr69 16-bit base + 0x00ca pad configuration register 70 pcr70 16-bit base + 0x00cc table 432. detailed register map (continued) register description register name used size address RM0017 register map doc id 14629 rev 8 806/904 pad configuration register 71 pcr71 16-bit base + 0x00ce pad configuration register 72 pcr72 16-bit base + 0x00d0 pad configuration register 73 pcr73 16-bit base + 0x00d2 pad configuration register 74 pcr74 16-bit base + 0x00d4 pad configuration register 75 pcr75 16-bit base + 0x00d6 pad configuration register 76 pcr76 16-bit base + 0x00d8 pad configuration register 77 pcr77 16-bit base + 0x00da pad configuration register 78 pcr78 16-bit base + 0x00dc pad configuration register 79 pcr79 16-bit base + 0x00de pad configuration register 80 pcr80 16-bit base + 0x00e0 pad configuration register 81 pcr81 16-bit base + 0x00e2 pad configuration register 82 pcr82 16-bit base + 0x00e4 pad configuration register 83 pcr83 16-bit base + 0x00e6 pad configuration register 84 pcr84 16-bit base + 0x00e8 pad configuration register 85 pcr85 16-bit base + 0x00ea pad configuration register 86 pcr86 16-bit base + 0x00ec pad configuration register 87 pcr87 16-bit base + 0x00ee pad configuration register 88 pcr88 16-bit base + 0x00f0 pad configuration register 89 pcr89 16-bit base + 0x00f2 pad configuration register 90 pcr90 16-bit base + 0x00f4 pad configuration register 91 pcr91 16-bit base + 0x00f6 pad configuration register 92 pcr92 16-bit base + 0x00f8 pad configuration register 93 pcr93 16-bit base + 0x00fa pad configuration register 94 pcr94 16-bit base + 0x00fc pad configuration register 95 pcr95 16-bit base + 0x00fe pad configuration register 96 pcr96 16-bit base + 0x0100 pad configuration register 97 pcr97 16-bit base + 0x0102 pad configuration register 98 pcr98 16-bit base + 0x0104 pad configuration register 99 pcr99 16-bit base + 0x0106 pad configuration register 100 pcr100 16-bit base + 0x0108 pad configuration register 101 pcr101 16-bit base + 0x010a pad configuration register 102 pcr102 16-bit base + 0x010c pad configuration register 103 pcr103 16-bit base + 0x010e pad configuration register 104 pcr104 16-bit base + 0x0110 table 432. detailed register map (continued) register description register name used size address register map RM0017 807/904 doc id 14629 rev 8 pad configuration register 105 pcr105 16-bit base + 0x0112 pad configuration register 106 pcr106 16-bit base + 0x0114 pad configuration register 107 pcr107 16-bit base + 0x0116 pad configuration register 108 pcr108 16-bit base + 0x0118 pad configuration register 109 pcr109 16-bit base + 0x011a pad configuration register 110 pcr110 16-bit base + 0x011c pad configuration register 111 pcr111 16-bit base + 0x011e pad configuration register 112 pcr112 16-bit base + 0x0120 pad configuration register 113 pcr113 16-bit base + 0x0122 pad configuration register 114 pcr114 16-bit base + 0x0124 pad configuration register 115 pcr115 16-bit base + 0x0126 pad configuration register 116 pcr116 16-bit base + 0x0128 pad configuration register 117 pcr117 16-bit base + 0x012a pad configuration register 118 pcr118 16-bit base + 0x012c pad configuration register 119 pcr119 16-bit base + 0x012e pad configuration register 120 pcr120 16-bit base + 0x0130 pad configuration register 121 pcr121 16-bit base + 0x0132 pad configuration register 122 pcr122 16-bit base + 0x0134 reserved ? ? base + (0x0136 ? 0x04ff) pad selection for multiplexed i nputs psmi0_3 32-bit base + 0x0500 pad selection for multiplexed i nputs psmi4_7 32-bit base + 0x0504 pad selection for multiplexed inputs psmi8_11 32-bit base + 0x0508 pad selection for multiplexed inputs psmi12_15 32-bit base + 0x050c pad selection for multiplexed inputs psmi16_19 32-bit base + 0x0510 pad selection for multiplexed inputs psmi20_23 32-bit base + 0x0514 pad selection for multiplexed inputs psmi24_27 32-bit base + 0x0518 pad selection for multiplexed inputs psmi28_31 32-bit base + 0x051c reserved ? ? base + (0x0520 ? 0x05ff) gpio pad data output register gpdo0_3 32-bit base + 0x0600 gpio pad data output register gpdo4_7 32-bit base + 0x0604 gpio pad data output register gpdo8_11 32-bit base + 0x0608 gpio pad data output register gpdo12_15 32-bit base + 0x060c gpio pad data output register gpdo16_19 32-bit base + 0x0610 table 432. detailed register map (continued) register description register name used size address RM0017 register map doc id 14629 rev 8 808/904 gpio pad data output register gpdo20_23 32-bit base + 0x0614 gpio pad data output register gpdo24_27 32-bit base + 0x0618 gpio pad data output register gpdo28_31 32-bit base + 0x061c gpio pad data output register gpdo32_35 32-bit base + 0x0620 gpio pad data output register gpdo36_39 32-bit base + 0x0624 gpio pad data output register gpdo40_43 32-bit base + 0x0628 gpio pad data output register gpdo44_47 32-bit base + 0x062c gpio pad data output register gpdo48_51 32-bit base + 0x0630 gpio pad data output register gpdo52_55 32-bit base + 0x0634 gpio pad data output register gpdo56_59 32-bit base + 0x0638 gpio pad data output register gpdo60_63 32-bit base + 0x063c gpio pad data output register gpdo64_67 32-bit base + 0x0640 gpio pad data output register gpdo68_71 32-bit base + 0x0644 gpio pad data output register gpdo72_75 32-bit base + 0x0648 gpio pad data output register gpdo76_79 32-bit base + 0x064c gpio pad data output register gpdo80_83 32-bit base + 0x0650 gpio pad data output register gpdo84_87 32-bit base + 0x0654 gpio pad data output register gpdo88_91 32-bit base + 0x0658 gpio pad data output register gpdo92_95 32-bit base + 0x065c gpio pad data output register gpdo96_99 32-bit base + 0x0660 gpio pad data output register gpdo100_103 32-bit base + 0x0664 gpio pad data output register gpdo104_107 32-bit base + 0x0668 gpio pad data output register gpdo108_111 32-bit base + 0x066c gpio pad data output register gpdo112_115 32-bit base + 0x0670 gpio pad data output register gpdo116_119 32-bit base + 0x0674 gpio pad data output register gpdo120_123 32-bit base + 0x0678 reserved ? ? base + (0x067c ? 0x07ff) gpio pad data input regist er gpdi0_3 32-bit base + 0x0800 gpio pad data input regist er gpdi4_7 32-bit base + 0x0804 gpio pad data input register gpdi8_11 32-bit base + 0x0808 gpio pad data input register gpdi12_15 32-bit base + 0x080c gpio pad data input register gpdi16_19 32-bit base + 0x0810 gpio pad data input register gpdi20_23 32-bit base + 0x0814 table 432. detailed register map (continued) register description register name used size address register map RM0017 809/904 doc id 14629 rev 8 gpio pad data input register gpdi24_27 32-bit base + 0x0818 gpio pad data input register gpdi28_31 32-bit base + 0x081c gpio pad data input register gpdi32_35 32-bit base + 0x0820 gpio pad data input register gpdi36_39 32-bit base + 0x0824 gpio pad data input register gpdi40_43 32-bit base + 0x0828 gpio pad data input register gpdi44_47 32-bit base + 0x082c gpio pad data input register gpdi48_51 32-bit base + 0x0830 gpio pad data input register gpdi52_55 32-bit base + 0x0834 gpio pad data input register gpdi56_59 32-bit base + 0x0838 gpio pad data input register gpdi60_63 32-bit base + 0x083c gpio pad data input register gpdi64_67 32-bit base + 0x0840 gpio pad data input register gpdi68_71 32-bit base + 0x0844 gpio pad data input register gpdi72_75 32-bit base + 0x0848 gpio pad data input register gpdi76_79 32-bit base + 0x084c gpio pad data input register gpdi80_83 32-bit base + 0x0850 gpio pad data input register gpdi84_87 32-bit base + 0x0854 gpio pad data input register gpdi88_91 32-bit base + 0x0858 gpio pad data input register gpdi92_95 32-bit base + 0x085c gpio pad data input register gpdi96_99 32-bit base + 0x0860 gpio pad data input register gpdi100_103 32-bit base + 0x0864 gpio pad data input register gpdi104_107 32-bit base + 0x0868 gpio pad data input register gpdi108_111 32-bit base + 0x086c gpio pad data input register gpdi112_115 32-bit base + 0x0870 gpio pad data input register gpdi116_119 32-bit base + 0x0874 gpio pad data input register gpdi120_123 32-bit base + 0x0878 reserved ? ? base + (0x087c ? 0x0bff) parallel gpio pad data out register pgpdo0 32-bit base + 0x0c00 parallel gpio pad data out register pgpdo1 32-bit base + 0x0c04 parallel gpio pad data out register pgpdo2 32-bit base + 0x0c08 parallel gpio pad data out register pgpdo3 32-bit base + 0x0c0c reserved ? ? (base + 0x0c10) ? (base + 0x0c3f) parallel gpio pad data in register pgpdi0 32-bit base + 0x0c40 parallel gpio pad data in register pgpdi1 32-bit base + 0x0c44 table 432. detailed register map (continued) register description register name used size address RM0017 register map doc id 14629 rev 8 810/904 parallel gpio pad data in register pgpdi2 32-bit base + 0x0c48 parallel gpio pad data in register pgpdi3 32-bit base + 0x0c4c reserved ? ? (base + 0x0c50) ? (base + 0x0c7f) masked parallel gpio pad data out register mpgpdo0 32-bit base + 0x0c80 masked parallel gpio pad data out register mpgpdo1 32-bit base + 0x0c84 masked parallel gpio pad data out register mpgpdo2 32-bit base + 0x0c88 masked parallel gpio pad data out register mpgpdo3 32-bit base + 0x0c8c masked parallel gpio pad data out register mpgpdo4 32-bit base + 0x0c90 masked parallel gpio pad data out register mpgpdo5 32-bit base + 0x0c94 masked parallel gpio pad data out register mpgpdo6 32-bit base + 0x0c98 masked parallel gpio pad data out register mpgpdo7 32-bit base + 0x0c9c reserved ? ? base + (0x0ca0 ? 0x0fff) interrupt filter maximum counter register ifmc0 32-bit base + 0x1000 interrupt filter maximum counter register ifmc1 32-bit base + 0x1004 interrupt filter maximum counter register ifmc2 32-bit base + 0x1008 interrupt filter maximum counter register ifmc3 32-bit base + 0x100c interrupt filter maximum counter register ifmc4 32-bit base + 0x1010 interrupt filter maximum counter register fmc5 32-bit base + 0x1014 interrupt filter maximum counter register ifmc6 32-bit base + 0x1018 interrupt filter maximum counter register ifmc7 32-bit base + 0x101c interrupt filter maximum counter register ifmc8 32-bit base + 0x1020 interrupt filter maximum counter register ifmc9 32-bit base + 0x1024 interrupt filter maximum counter register ifmc10 32-bit base + 0x1028 interrupt filter maximum counter register ifmc11 32-bit base + 0x102c interrupt filter maximum counter register ifmc12 32-bit base + 0x1030 interrupt filter maximum counter register ifmc13 32-bit base + 0x1034 interrupt filter maximum counter register ifmc14 32-bit base + 0x1038 interrupt filter maximum counter register ifmc15 32-bit base + 0x103c reserved ? ? (base + 0x1044 ? 0x107c) inerrupt filter clock prescaler register ifcp 32-bit base + 0x1080 reserved ? ? base + (0x1084 ? 0x3fff) table 432. detailed register map (continued) register description register name used size address register map RM0017 811/904 doc id 14629 rev 8 wakeup unit 0xc3f9_4000 nmi status flag register wkpu_nsr 32-bit base + 0x0000 reserved ? ? (base + 0x0004) ? (base + 0x0007) nmi configuration register wkpu_ncr 32-bit base + 0x0008 reserved ? ? (base + 0x000c) ? (base + 0x0013) wakeup/interrupt status flag re gister wkpu_wisr 32-bit base + 0x0014 interrupt request enable register wkpu_irer 32-bit base + 0x0018 wakeup request enable register wkpu_wrer 32-bit base + 0x001c reserved ? ? (base + 0x0020) ? (base + 0x0027) wakeup/interrupt rising-edge event enable register wkpu_wireer 32-bit base + 0x0028 wakeup/interrupt falling-edge event enable register wkpu_wifeer 32-bit base + 0x002c wakeup/interrupt filter enable r egister wkpu_wifer 32-bit base + 0x0030 wakeup/interrupt pullup enable register wkpu_wipuer 32-bit base + 0x0034 reserved ? ? (base + 0x0038) ? (base + 0xffff) emios_0 0xc3fa_0000 emios module configuration register emios0_mcr 32-bit base + 0x0000 emios global flag register emios0_gflag 32-bit base + 0x0004 emios output update disable register emios0_oudis 32-bit base + 0x0008 emios disable channel register emios0_ucdis 32-bit base + 0x000c reserved ? ? (base + 0x0010) ? (base + 0x001f) emios_0 uc0 a register emios0_uc0_a 32-bit base + 0x0020 emios_0 uc0 b register emios0_uc0_b 32-bit base + 0x0024 emios_0 uc0 cnt emios0_uc0_cnt 32-bit base + 0x0028 emios_0 uc0 control register emios0_uc0_sc 32-bit base + 0x002c emios_0 uc0 status register emios0_uc0_ss 32-bit base + 0x0030 reserved ? ? base + 0x0034 ? base + 0x003f emios_0 uc1 a register emios0_uc1_a 32-bit base + 0x0040 emios_0 uc1 b register emios0_uc1_b 32-bit base + 0x0044 reserved ? ? base + 0x0048 -? base + 0x004b emios_0 uc1 control register emios0_uc1_sc 32-bit base + 0x004c table 432. detailed register map (continued) register description register name used size address RM0017 register map doc id 14629 rev 8 812/904 emios_0 uc1 status register emios0_uc1_ss 32-bit base + 0x0050 reserved ? ? base + 0x0054 ? base + 0x005f emios_0 uc2 a register emios0_uc2_a 32-bit base + 0x0060 emios_0 uc2 b register emios0_uc2_b 32-bit base + 0x0064 reserved ? ? base + 0x0068 ? base + 0x006b emios_0 uc2 control register emios0_uc2_sc 32-bit base + 0x006c emios_0 uc2 status register emios0_uc2_ss 32-bit base + 0x0070 reserved ? ? base + 0x0074 ? base + 0x007f emios_0 uc3 a register emios0_uc3_a 32-bit base + 0x0080 emios_0 uc3 b register emios0_uc3_b 32-bit base + 0x0084 reserved ? ? base + 0x0088 ? base + 0x008b emios_0 uc3 control register emios0_uc3_sc 32-bit base + 0x008c emios_0 uc3 status register emios0_uc3_ss 32-bit base + 0x0090 reserved ? ? base + 0x0094 ? base + 0x009f emios_0 uc4 a register emios0_uc4_a 32-bit base + 0x00a0 emios_0 uc4 b register emios0_uc4_b 32-bit base + 0x00a4 reserved ? ? base + 0x00a8 ? base + 0x00ab emios_0 uc4 control register emios0_uc4_sc 32-bit base + 0x00ac emios_0 uc4 status register emios0_uc4_ss 32-bit base + 0x00b0 reserved ? ? base + 0x00b4 ? base + 0x00bf emios_0 uc5 a register emios0_uc5_a 32-bit base + 0x00c0 emios_0 uc5 b register emios0_uc5_b 32-bit base + 0x00c4 reserved ? ? base + 0x00c8 ? base + 0x00cb emios_0 uc5 control register emios0_uc5_sc 32-bit base + 0x00cc emios_0 uc5 status register emios0_uc5_ss 32-bit base + 0x00d0 reserved ? ? base + 0x00d4 ? base + 0x00df emios_0 uc6 a register emios0_uc6_a 32-bit base + 0x00e0 emios_0 uc6 b register emios0_uc6_b 32-bit base + 0x00e4 table 432. detailed register map (continued) register description register name used size address register map RM0017 813/904 doc id 14629 rev 8 reserved ? ? base + 0x00e8 ? base + 0x00eb emios_0 uc6 control register emios0_uc6_sc 32-bit base + 0x00ec emios_0 uc6 status register emios0_uc6_ss 32-bit base + 0x00f0 reserved ? ? base + 0x00f4 ? base + 0x00ff emios_0 uc7 a register emios0_uc7_a 32-bit base + 0x0100 emios_0 uc7 b register emios0_uc7_b 32-bit base + 0x0104 reserved ? ? base + 0x0108 ? base + 0x010b emios_0 uc7 control register emios0_uc7_sc 32-bit base + 0x010c emios_0 uc7 status register emios0_uc7_ss 32-bit base + 0x0110 reserved ? ? base + 0x0114 ? base + 0x011f emios_0 uc8 a register emios0_uc8_a 32-bit base + 0x0120 emios_0 uc8 b register emios0_uc8_b 32-bit base + 0x0124 emios_0 uc8 cnt emios0_uc8_cnt 32-bit base + 0x0128 emios_0 uc8 control register emios0_uc8_sc 32-bit base + 0x012c emios_0 uc8 status register emios0_uc8_ss 32-bit base + 0x0130 reserved ? ? base + 0x0134 ? base + 0x013f emios_0 uc9 a register emios0_uc9_a 32-bit base + 0x0140 emios_0 uc9 b register emios0_uc9_b 32-bit base + 0x0144 reserved ? ? base + 0x0148 ? base + 0x014b emios_0 uc9 control register emios0_uc9_sc 32-bit base + 0x014c emios_0 uc9 status register emios0_uc9_ss 32-bit base + 0x0150 reserved ? ? base + 0x0154 ? base + 0x015f emios_0 uc10 a register emios0_uc10_a 32-bit base + 0x0160 emios_0 uc10 b register emios0_uc10_b 32-bit base + 0x0164 reserved ? ? base + 0x0168 ? base + 0x016b emios_0 uc10 control register emios0_uc10_sc 32-bit base + 0x016c emios_0 uc10 status register em ios0_uc10_ss 32-bit base + 0x0170 reserved ? ? base + 0x0174 ? base + 0x017f table 432. detailed register map (continued) register description register name used size address RM0017 register map doc id 14629 rev 8 814/904 emios_0 uc11 a register emios0_uc11_a 32-bit base + 0x0180 emios_0 uc11 b register emios0_uc11_b 32-bit base + 0x0184 reserved ? ? base + 0x0188 ? base + 0x018b emios_0 uc11 control register emios0_uc11_sc 32-bit base + 0x018c emios_0 uc11 status register em ios0_uc11_ss 32-bit base + 0x0190 reserved ? ? base + 0x0194 ? base + 0x019f emios_0 uc12 a register emios0_uc12_a 32-bit base + 0x01a0 emios_0 uc12 b register emios0_uc12_b 32-bit base + 0x01a4 reserved ? ? base + 0x01a8 ? base + 0x01ab emios_0 uc12 control register emios0_uc12_sc 32-bit base + 0x01ac emios_0 uc12 status register em ios0_uc12_ss 32-bit base + 0x01b0 reserved ? ? base + 0x01b4 ? base + 0x01bf emios_0 uc13 a register emios0_uc13_a 32-bit base + 0x01c0 emios_0 uc13 b register emios0_uc13_b 32-bit base + 0x01c4 reserved ? ? base + 0x01c8 ? base + 0x01cb emios_0 uc13 control register emios0_uc13_sc 32-bit base + 0x01cc emios_0 uc13 status register em ios0_uc13_ss 32-bit base + 0x01d0 reserved ? ? base + 0x01d4 ? base + 0x01df emios_0 uc14 a register emios0_uc14_a 32-bit base + 0x01e0 emios_0 uc14 b register emios0_uc14_b 32-bit base + 0x01e4 reserved ? ? base + 0x01e8 ? base + 0x01eb emios_0 uc14 control register emios0_uc14_sc 32-bit base + 0x01ec emios_0 uc14 status register em ios0_uc14_ss 32-bit base + 0x01f0 reserved ? ? base + 0x01f4 ? base + 0x01ff emios_0 uc15 a register emios0_uc15_a 32-bit base + 0x0200 emios_0 uc15 b register emios0_uc15_b 32-bit base + 0x0204 reserved ? ? base + 0x0208 ? base + 0x020b emios_0 uc15 control register emios0_uc15_sc 32-bit base + 0x020c table 432. detailed register map (continued) register description register name used size address register map RM0017 815/904 doc id 14629 rev 8 emios_0 uc15 status register em ios0_uc15_ss 32-bit base + 0x0210 reserved ? ? base + 0x0214 ? base + 0x021f emios_0 uc16 a register emios0_uc16_a 32-bit base + 0x0220 emios_0 uc16 b register emios0_uc16_b 32-bit base + 0x0224 emios_0 uc16 cnt emios0_uc16_cnt 32-bit base + 0x0228 emios_0 uc16 control register emios0_uc16_sc 32-bit base + 0x022c emios_0 uc16 status register em ios0_uc16_ss 32-bit base + 0x0230 reserved ? ? base + 0x0234 ? base + 0x023f emios_0 uc17 a register emios0_uc17_a 32-bit base + 0x0240 emios_0 uc17 b register emios0_uc17_b 32-bit base + 0x0244 reserved ? ? base + 0x0248 ? base + 0x024b emios_0 uc17 control register emios0_uc17_sc 32-bit base + 0x024c emios_0 uc17 status register em ios0_uc17_ss 32-bit base + 0x0250 reserved ? ? base + 0x0254 ? base + 0x025f emios_0 uc18 a register emios0_uc18_a 32-bit base + 0x0260 emios_0 uc18 b register emios0_uc18_b 32-bit base + 0x0264 reserved ? ? base + 0x0268 ? base + 0x026b emios_0 uc18 control register emios0_uc18_sc 32-bit base + 0x026c emios_0 uc18 status register em ios0_uc18_ss 32-bit base + 0x0270 reserved ? ? base + 0x0274 ? base + 0x027f emios_0 uc19 a register emios0_uc19_a 32-bit base + 0x0280 emios_0 uc19 b register emios0_uc19_b 32-bit base + 0x0284 reserved ? ? base + 0x0288 ? base + 0x028b emios_0 uc19 control register emios0_uc19_sc 32-bit base + 0x028c emios_0 uc19 status register em ios0_uc19_ss 32-bit base + 0x0290 reserved ? ? base + 0x0294 ? base + 0x029f emios_0 uc20 a register emios0_uc20_a 32-bit base + 0x02a0 emios_0 uc20 b register emios0_uc20_b 32-bit base + 0x02a4 table 432. detailed register map (continued) register description register name used size address RM0017 register map doc id 14629 rev 8 816/904 reserved ? ? base + 0x02a8 ? base + 0x02ab emios_0 uc20 control register emios0_uc20_sc 32-bit base + 0x02ac emios_0 uc20 status register em ios0_uc20_ss 32-bit base + 0x02b0 reserved ? ? base + 0x02b4 ? base + 0x02bf emios_0 uc21 a register emios0_uc21_a 32-bit base + 0x02c0 emios_0 uc21 b register emios0_uc21_b 32-bit base + 0x02c4 reserved ? ? base + 0x02c8 ? base + 0x02cb emios_0 uc21 control register emios0_uc21_sc 32-bit base + 0x02cc emios_0 uc21 status register em ios0_uc21_ss 32-bit base + 0x02d0 reserved ? ? base + 0x02d4 ? base + 0x02df emios_0 uc22 a register emios0_uc22_a 32-bit base + 0x02e0 emios_0 uc22 b register emios0_uc22_b 32-bit base + 0x02e4 reserved ? ? base + 0x02e8 ? base + 0x02eb emios_0 uc22 control register emios0_uc22_sc 32-bit base + 0x02ec emios_0 uc22 status register em ios0_uc22_ss 32-bit base + 0x02f0 reserved ? ? base + 0x02f4 ? base + 0x02ff emios_0 uc23 a register emios0_uc23_a 32-bit base + 0x0300 emios_0 uc23 b register emios0_uc23_b 32-bit base + 0x0304 emios_0 uc23 cnt emios0_uc23_cnt 32-bit base + 0x0308 emios_0 uc23 control register emios0_uc23_sc 32-bit base + 0x030c emios_0 uc23 status register em ios0_uc23_ss 32-bit base + 0x0310 reserved ? ? base + 0x0314 ? base + 0x031f emios_1 0xc3fa_4000 emios module configuration regist er emios1_mcr 32-bit base + 0x0000 emios global flag register em ios1_gflag 32-bit base + 0x0004 emios output update disable register emios1_oudis 32-bit base + 0x0008 emios disable channel register emios1_ucdis 32-bit base + 0x000c reserved - - (base + 0x001c) ? (base + 0x001f) emios_1 uc0 a register emios1_uc0_a 32-bit base + 0x0020 table 432. detailed register map (continued) register description register name used size address register map RM0017 817/904 doc id 14629 rev 8 emios_1 uc0 b register emios1_uc0_b 32-bit base + 0x0024 emios_1 uc0 cnt emios1_uc0_cnt 32-bit base + 0x0028 emios_1 uc0 control register emios1_uc0_sc 32-bit base + 0x002c emios_1 uc0 status register emios1_uc0_ss 32-bit base + 0x0030 reserved ? ? base + 0x0034 ? base + 0x003f emios_1 uc1 a register emios1_uc1_a 32-bit base + 0x0040 emios_1 uc1 b register emios1_uc1_b 32-bit base + 0x0044 reserved ? ? base + 0x0048 ? base + 0x004b emios_1 uc1 control register emios1_uc1_sc 32-bit base + 0x004c emios_1 uc1 status register emios1_uc1_ss 32-bit base + 0x0050 reserved ? ? base + 0x0054 ? base + 0x005f emios_1 uc2 a register emios1_uc2_a 32-bit base + 0x0060 emios_1 uc2 b register emios1_uc2_b 32-bit base + 0x0064 reserved ? ? base + 0x0068 ? base + 0x006b emios_1 uc2 control register emios1_uc2_sc 32-bit base + 0x006c emios_1 uc2 status register emios1_uc2_ss 32-bit base + 0x0070 reserved ? ? base + 0x0074 ? base + 0x007f emios_1 uc3 a register emios1_uc3_a 32-bit base + 0x0080 emios_1 uc3 b register emios1_uc3_b 32-bit base + 0x0084 reserved ? ? base + 0x0088 ? base + 0x008b emios_1 uc3 control register emios1_uc3_sc 32-bit base + 0x008c emios_1 uc3 status register emios1_uc3_ss 32-bit base + 0x0090 reserved ? ? base + 0x0094 ? base + 0x009f emios_1 uc4 a register emios1_uc4_a 32-bit base + 0x00a0 emios_1 uc4 b register emios1_uc4_b 32-bit base + 0x00a4 reserved ? ? base + 0x00a8 ? base + 0x00ab emios_1 uc4 control register emios1_uc4_sc 32-bit base + 0x00ac emios_1 uc4 status register emios1_uc4_ss 32-bit base + 0x00b0 table 432. detailed register map (continued) register description register name used size address RM0017 register map doc id 14629 rev 8 818/904 reserved ? ? base + 0x00b4 ? base + 0x00bf emios_1 uc5 a register emios1_uc5_a 32-bit base + 0x00c0 emios_1 uc5 b register emios1_uc5_b 32-bit base + 0x00c4 reserved ? ? base + 0x00c8 ? base + 0x00cb emios_1 uc5 control register emios1_uc5_sc 32-bit base + 0x00cc emios_1 uc5 status register emios1_uc5_ss 32-bit base + 0x00d0 reserved ? ? base + 0x00d4 ? base + 0x00df emios_1 uc6 a register emios1_uc6_a 32-bit base + 0x00e0 emios_1 uc6 b register emios1_uc6_b 32-bit base + 0x00e4 reserved ? ? base + 0x00e8 ? base + 0x00eb emios_1 uc6 control register emios1_uc6_sc 32-bit base + 0x00ec emios_1 uc6 status register emios1_uc6_ss 32-bit base + 0x00f0 reserved ? ? base + 0x00f4 ? base + 0x00ff emios_1 uc7 a register emios1_uc7_a 32-bit base + 0x0100 emios_1 uc7 b register emios1_uc7_b 32-bit base + 0x0104 reserved ? ? base + 0x0108 ? base + 0x010b emios_1 uc7 control register emios1_uc7_sc 32-bit base + 0x010c emios_1 uc7 status register emios1_uc7_ss 32-bit base + 0x0110 reserved ? ? base + 0x0114 ? base + 0x011f emios_1 uc8 a register emios1_uc8_a 32-bit base + 0x0120 emios_1 uc8 b register emios1_uc8_b 32-bit base + 0x0124 emios_1 uc8 cnt emios1_uc8_cnt 32-bit base + 0x0128 emios_1 uc8 control register emios1_uc8_sc 32-bit base + 0x012c emios_1 uc8 status register emios1_uc8_ss 32-bit base + 0x0130 reserved ? ? base + 0x0134 ? base + 0x013f emios_1 uc9 a register emios1_uc9_a 32-bit base + 0x0140 emios_1 uc9 b register emios1_uc9_b 32-bit base + 0x0144 reserved ? ? base + 0x0148 ? base + 0x014b table 432. detailed register map (continued) register description register name used size address register map RM0017 819/904 doc id 14629 rev 8 emios_1 uc9 control register emios1_uc9_sc 32-bit base + 0x014c emios_1 uc9 status register emios1_uc9_ss 32-bit base + 0x0150 reserved ? ? base + 0x0154 ? base + 0x015f emios_1 uc10 a register emios1_uc10_a 32-bit base + 0x0160 emios_1 uc10 b register emios1_uc10_b 32-bit base + 0x0164 reserved ? ? base + 0x0168 ? base + 0x016b emios_1 uc10 control register emios1_uc10_sc 32-bit base + 0x016c emios_1 uc10 status register emios1_uc10_ss 32-bit base + 0x0170 reserved ? ? base + 0x0174 ? base + 0x017f emios_1 uc11 a register emios1_uc11_a 32-bit base + 0x0180 emios_1 uc11 b register emios1_uc11_b 32-bit base + 0x0184 reserved ? ? base + 0x0188 ? base + 0x018b emios_1 uc11 control register emios1_uc11_sc 32-bit base + 0x018c emios_1 uc11 status register emios1_uc11_ss 32-bit base + 0x0190 reserved ? ? base + 0x0194 ? base + 0x019f emios_1 uc12 a register emios1_uc12_a 32-bit base + 0x01a0 emios_1 uc12 b register emios1_uc12_b 32-bit base + 0x01a4 reserved ? ? base + 0x01a8 ? base + 0x01ab emios_1 uc12 control register emios1_uc12_sc 32-bit base + 0x01ac emios_1 uc12 status register emios1_uc12_ss 32-bit base + 0x01b0 reserved ? ? base + 0x01b4 ? base + 0x01bf emios_1 uc13 a register emios1_uc13_a 32-bit base + 0x01c0 emios_1 uc13 b register emios1_uc13_b 32-bit base + 0x01c4 reserved ? ? base + 0x01c8 ? base + 0x01cb emios_1 uc13 control register emios1_uc13_sc 32-bit base + 0x01cc emios_1 uc13 status register emios1_uc13_ss 32-bit base + 0x01d0 reserved ? ? base + 0x01d4 ? base + 0x01df emios_1 uc14 a register emios1_uc14_a 32-bit base + 0x01e0 table 432. detailed register map (continued) register description register name used size address RM0017 register map doc id 14629 rev 8 820/904 emios_1 uc14 b register emios1_uc14_b 32-bit base + 0x01e4 reserved ? ? base + 0x01e8 ? base + 0x01eb emios_1 uc14 control register emios1_uc14_sc 32-bit base + 0x01ec emios_1 uc14 status register emios1_uc14_ss 32-bit base + 0x01f0 reserved ? ? base + 0x01f4 ? base + 0x01ff emios_1 uc15 a register emios1_uc15_a 32-bit base + 0x0200 emios_1 uc15 b register emios1_uc15_b 32-bit base + 0x0204 reserved ? ? base + 0x0208 ? base + 0x020b emios_1 uc15 control register emios1_uc15_sc 32-bit base + 0x020c emios_1 uc15 status register emios1_uc15_ss 32-bit base + 0x0210 reserved ? ? base + 0x0214 ? base + 0x021f emios_1 uc16 a register emios1_uc16_a 32-bit base + 0x0220 emios_1 uc16 b register emios1_uc16_b 32-bit base + 0x0224 emios_1 uc16 cnt emios1_uc16_cnt 32-bit base + 0x0228 emios_1 uc16 control register emios1_uc16_sc 32-bit base + 0x022c emios_1 uc16 status register emios1_uc16_ss 32-bit base + 0x0230 reserved ? ? base + 0x0234 ? base + 0x023f emios_1 uc17 a register emios1_uc17_a 32-bit base + 0x0240 emios_1 uc17 b register emios1_uc17_b 32-bit base + 0x0244 reserved ? ? base + 0x0248 ? base + 0x024b emios_1 uc17 control register emios1_uc17_sc 32-bit base + 0x024c emios_1 uc17 status register emios1_uc17_ss 32-bit base + 0x0250 reserved ? ? base + 0x0254 ? base + 0x025f emios_1 uc18 a register emios1_uc18_a 32-bit base + 0x0260 emios_1 uc18 b register emios1_uc18_b 32-bit base + 0x0264 reserved ? ? base + 0x0268 ? base + 0x026b emios_1 uc18 control register emios1_uc18_sc 32-bit base + 0x026c emios_1 uc18 status register emios1_uc18_ss 32-bit base + 0x0270 table 432. detailed register map (continued) register description register name used size address register map RM0017 821/904 doc id 14629 rev 8 reserved ? ? base + 0x0274 ? base + 0x027f emios_1 uc19 a register emios1_uc19_a 32-bit base + 0x0280 emios_1 uc19 b register emios1_uc19_b 32-bit base + 0x0284 reserved ? ? base + 0x0288 ? base + 0x028b emios_1 uc19 control register emios1_uc19_sc 32-bit base + 0x028c emios_1 uc19 status register emios1_uc19_ss 32-bit base + 0x0290 reserved ? ? base + 0x0294 ? base + 0x029f emios_1 uc20 a register emios1_uc20_a 32-bit base + 0x02a0 emios_1 uc20 b register emios1_uc20_b 32-bit base + 0x02a4 reserved ? ? base + 0x02a8 ? base + 0x02ab emios_1 uc20 control register emios1_uc20_sc 32-bit base + 0x02ac emios_1 uc20 status register emios1_uc20_ss 32-bit base + 0x02b0 reserved ? ? base + 0x02b4 ? base + 0x02bf emios_1 uc21 a register emios1_uc21_a 32-bit base + 0x02c0 emios_1 uc21 b register emios1_uc21_b 32-bit base + 0x02c4 reserved ? ? base + 0x02c8 ? base + 0x02cb emios_1 uc21 control register emios1_uc21_sc 32-bit base + 0x02cc emios_1 uc21 status register emios1_uc21_ss 32-bit base + 0x02d0 reserved ? ? base + 0x02d4 ? base + 0x02df emios_1 uc22 a register emios1_uc22_a 32-bit base + 0x02e0 emios_1 uc22 b register emios1_uc22_b 32-bit base + 0x02e4 reserved ? ? base + 0x02e8 ? base + 0x02eb emios_1 uc22 control register emios1_uc22_sc 32-bit base + 0x02ec emios_1 uc22 status register emios1_uc22_ss 32-bit base + 0x02f0 reserved ? ? base + 0x02f4 ? base + 0x02ff emios_1 uc23 a register emios1_uc23_a 32-bit base + 0x0300 emios_1 uc23 b register emios1_uc23_b 32-bit base + 0x0304 emios_1 uc23 cnt emios1_uc23_cnt 32-bit base + 0x0308 table 432. detailed register map (continued) register description register name used size address RM0017 register map doc id 14629 rev 8 822/904 emios_1 uc23 control register emios1_uc23_sc 32-bit base + 0x030c emios_1 uc23 status register emios1_uc23_ss 32-bit base + 0x0310 system status and configuration module (sscm) 0xc3fd_8000 system status register st atus 16-bit base + 0x0000 system memory configuration regi ster memconfig 16-bit base + 0x0002 reserved - - base + (0x0004 ? 0x0005) error configuration error 16-bit base + 0x0006 reserved - - base + (0x0008 ? 0x000b) password comparison register high word pwcmph 32-bit base + 0x000c password comparison register low word pwcmpl 32-bit base + 0x0010 reserved - - base + (0x0014 ? 0x3fff) mode entry module (mc_me) 0xc3fd_c000 global status me_gs 32-bit base + 0x0000 mode control me_mctl 32-bit base + 0x0004 mode enable me_me 32-bit base + 0x0008 interrupt status me_is 32-bit base + 0x000c interrupt mask me_im 32-bit base + 0x0010 invalid mode transition status me_imts 32-bit base + 0x0014 debug mode transition status me_dmts 32-bit base + 0x0018 reset mode configuration me_reset_mc 32-bit base + 0x0020 test mode configuration me_test_mc 32-bit base + 0x0024 safe mode configuration me_safe_mc 32-bit base + 0x0028 drun mode configuration me_drun_mc 32-bit base + 0x002c run0 mode configuration me_run0_mc 32-bit base + 0x0030 run1 mode configuration me_run1_mc 32-bit base + 0x0034 run2 mode configuration me_run2_mc 32-bit base + 0x0038 run3 mode configuration me_run3_mc 32-bit base + 0x003c halt mode configuration me_halt_mc 32-bit base + 0x0040 reserved ? ? base + 0x0044 ? base + 0x0047 stop mode configuration me_stop_mc 32-bit base + 0x0048 reserved ? ? base + 0x004c ? base + 0x0053 table 432. detailed register map (continued) register description register name used size address register map RM0017 823/904 doc id 14629 rev 8 standby mode configuration me_ standby_mc 32-bit base + 0x0054 reserved ? ? base + 0x0058 ? base + 0x005f peripheral status registers me_ps0 32-bit base + 0x0060 peripheral status registers me_ps1 32-bit base + 0x0064 peripheral status registers me_ps2 32-bit base + 0x0068 peripheral status registers me_ps3 32-bit base + 0x006c reserved - - (base + 0x0070) ? (base + 0x007f) run peripheral configuration registers me_run_pc0 32-bit base + 0x0080 run peripheral configuration registers me_run_pc1 32-bit base + 0x0084 run peripheral configuration registers me_run_pc2 32-bit base + 0x0088 run peripheral configuration registers me_run_pc3 32-bit base + 0x008c run peripheral configuration registers me_run_pc4 32-bit base + 0x0090 run peripheral configuration registers me_run_pc5 32-bit base + 0x0094 run peripheral configuration registers me_run_pc6 32-bit base + 0x0098 run peripheral configuration registers me_run_pc7 32-bit base + 0x009c low power peripheral configuration registers me_lp_pc0 32-bit base + 0x00a0 low power peripheral configuration registers me_lp_pc1 32-bit base + 0x00a4 low power peripheral configuration registers me_lp_pc2 32-bit base + 0x00a8 low power peripheral configuration registers me_lp_pc3 32-bit base + 0x00ac low power peripheral configuration registers me_lp_pc4 32-bit base + 0x00b0 low power peripheral configuration registers me_lp_pc5 32-bit base + 0x00b4 low power peripheral configuration registers me_lp_pc6 32-bit base + 0x00b8 low power peripheral configuration registers me_lp_pc7 32-bit base + 0x00bc reserved - - (base + 0x00c0) ? (base + 0x00c3) dspi0 control me_pctl4 8-bit base + 0x00c4 dspi1 control me_pctl5 8-bit base + 0x00c5 dspi2 control me_pctl6 8-bit base + 0x00c6 reserved - - (base + 0x00c7) ? (base + 0x00cf) flexcan0 control me_pctl16 8-bit base + 0x00d0 flexcan1 control me_pctl17 8-bit base + 0x00d1 flexcan2 control me_pctl18 8-bit base + 0x00d2 table 432. detailed register map (continued) register description register name used size address RM0017 register map doc id 14629 rev 8 824/904 flexcan3 control me_pctl19 8-bit base + 0x00d3 flexcan4 control me_pctl20 8-bit base + 0x00d4 flexcan5 control me_pctl21 8-bit base + 0x00d5 reserved - - (base + 0x00d6) ? (base + 0x00df) adc0 control me_pctl32 8-bit base + 0x00e0 reserved - - (base + 0x00e1) ? (base + 0x00eb) i2c0 control me_pctl44 8-bit base + 0x00ec reserved - - (base + 0x00ed) ? (base + 0x00ef) linflex0 control me_pctl48 8-bit base + 0x00f0 linflex1 control me_pctl49 8-bit base + 0x00f1 linflex2 control me_pctl50 8-bit base + 0x00f2 linflex3 control me_pctl51 8-bit base + 0x00f3 reserved - - (base + 0x00f4) ? (base + 0x00f8) ctu control me_pctl57 8-bit base + 0x00f9 reserved - - (base + 0x00fa) ? (base + 0x00fb) can sampler control me_pctl60 8-bit base + 0x00fc reserved - - (base + 0x00fd) ? (base + 0x0103) siul control me_pctl68 8-bit base + 0x0104 wkpu control me_pctl69 8-bit base + 0x0105 reserved - - (base + 0x0106) ? (base + 0x0107) emios0 control me_pctl72 8-bit base + 0x0108 emios1 control me_pctl73 8-bit base + 0x0109 reserved - - (base + 0x010a) ? (base + 0x011a) rtc_api control me_pctl91 8-bit base + 0x011b pit control me_pctl92 8-bit base + 0x011c reserved ? ? (base + 0x011d) ? (base + 0x0127) cmu control me_pctl104 8-bit base + 0x0128 reserved ? ? (base + 0x0129) ? (base + 0x014f) table 432. detailed register map (continued) register description register name used size address register map RM0017 825/904 doc id 14629 rev 8 fxosc 0xc3fe_0000 fast external crystal oscillator control register fxosc_ctl 32-bit base + 0x0000 reserved ? ? (base + 0x0004) ? (base + 0x003f) sxosc 0xc3fe_0040 slow external crystal oscillator control register sxosc_ctl 32-bit base + 0x0000 reserved ? ? (base + 0x0004) ? (base + 0x005f) firc digital interface 0xc3fe_0060 rc digital interface registers rc_ctl 32-bit base + 0x0000 reserved ? ? (base + 0x0004) ? (base + 0x007f) sirc digital interface 0xc3fe_0080 slow power rc control register lprc_ctl 32-bit base + 0x0000 reserved ? ? (base + 0x0004) ? (base + 0x009f) fmpll 0xc3fe_00a0 control register plld0_cr 32-bit base + 0x0000 plld modulation register plld0_mr 32-bit base + 0x0004 reserved ? ? (base + 0x0008) ? (base + 0x00ff) cmu 0xc3fe_0100 control status register cmu_csr 32-bit base + 0x0000 frequency display register cmu_fdr 32-bit base + 0x0004 high frequency reference register cmu_hfrefr_a 32-bit base + 0x0008 low frequency reference register cmu_lfrefr_a 32-bit base + 0x000c interrupt status register cmu_isr 32-bit base + 0x0010 reserved ? ? (base + 0x0014) ? (base + 0x0017) measurement duration register cmu_mdr 32-bit base + 0x0018 reserved ? ? (base + 0x001c) ? (base + 0x036f) clock generation modu le (mc_cgm) 0xc3fe_0370 output clock enable register cgm_oc_en 32-bit base + 0x0000 output clock division select regi ster cgm_ocds_sc 32-bit base + 0x0004 system clock select status register cgm_sc_ss 32-bit base + 0x0008 system clock divider configuration 0 registers cgm_sc_dc0 8-bit base + 0x000c table 432. detailed register map (continued) register description register name used size address RM0017 register map doc id 14629 rev 8 826/904 system clock divider configuration 1 registers cgm_sc_dc1 8-bit base + 0x000d system clock divider configuration 2 registers cgm_sc_dc2 8-bit base + 0x000e reset generation module (mc_rgm) 0xc3fe_4000 functional event status rgm_fes 16-bit base + 0x0000 destructive event status rg m_des 16-bit base + 0x0002 functional event reset disable rgm_ferd 16-bit base + 0x0004 destructive event reset disable rgm_derd 16-bit base + 0x0006 reserved ? ? (base + 0x0008) ? (base + 0x000f) functional event alternate request rgm_fear 16-bit base + 0x0010 destructive event alternate request rgm_dear 16-bit base + 0x0012 reserved ? ? (base + 0x0014) ? (base + 0x0017) functional event short sequence rgm_fess 16-bit base + 0x0018 standby reset sequence rgm_stdby 16-bit base + 0x001a functional bidirectional reset enable rgm_fbre 16-bit base + 0x001c reserved ? ? (base + 0x001e) ? (base + 0x3fff) power control unit (mc_pcu) 0xc3fe_8000 power domain #0 configuration register pconf0 32-bit base + 0x0000 power domain #1 configuration register pconf1 32-bit base + 0x0004 power domain #2 configuration register pconf2 32-bit base + 0x0008 reserved ? ? (base + 0x000c) ? (base + 0x003f) power domain status register pstat 32-bit base + 0x0040 reserved ? ? (base + 0x0044) ? (base + 0x007c) voltage regulator control register vctl 32-bit base + 0x0080 reserved ? ? (base + 0x0084) ? (base + 0x3fff) real time counter (rtc/api) 0xc3fe_c000 rtc supervisor control register rtcsupv 32-bit base + 0x0000 rtc control register rtcc 32-bit base + 0x0004 rtc status register rtcs 32-bit base + 0x0008 rtc counter register rtccnt 32-bit base + 0x000c reserved ? ? (base + 0x0010) ? (base + 0x3fff) table 432. detailed register map (continued) register description register name used size address register map RM0017 827/904 doc id 14629 rev 8 periodic interrupt timer (pit) 0xc3ff_0000 pit module control register pitmcr 32-bit base + 0x0000 reserved ? ? base + (0x0004 ? 0x00fc) timer load value register ldval0 32-bit base + 0x0100 current timer value register 0 cval0 32-bit base + 0x0104 timer control register 0 tctrl0 32-bit base + 0x0108 timer flag register 0 tflg0 32-bit base + 0x010c timer load value register 1 ldval1 32-bit base + 0x0110 current timer value register 1 cval1 32-bit base + 0x0114 timer control register 1 tctrl1 32-bit base + 0x0118 timer flag register 1 tflg1 32-bit base + 0x011c timer load value register 2 ldval2 32-bit base + 0x0120 current timer value register 2 cval2 32-bit base + 0x0124 timer control register 2 tctrl2 32-bit base + 0x0128 timer flag register 2 tflg2 32-bit base + 0x012c timer load value register 3 ldval3 32-bit base + 0x0130 current timer value register 3 cval3 32-bit base + 0x0134 timer control register 3 tctrl3 32-bit base + 0x0138 timer flag register 3 tflg3 32-bit base + 0x013c timer load value register 4 ldval4 32-bit base + 0x0140 current timer value register 4 cval4 32-bit base + 0x0144 timer control register 4 tctrl4 32-bit base + 0x0148 timer flag register 4 tflg4 32-bit base + 0x014c timer load value register 5 ldval5 32-bit base + 0x0150 current timer value register 5 cval5 32-bit base + 0x0154 timer control register 5 tctrl5 32-bit base + 0x0158 timer flag register 5 tflg5 32-bit base + 0x015c reserved ? ? base + 0x0160 ? 0x01ff adc 0xffe0_0000 main configuration register mcr 32-bit base + 0x0000 main status register msr 32-bit base + 0x0004 reserved ? ? base + 0x0008 ? 0x000f table 432. detailed register map (continued) register description register name used size address RM0017 register map doc id 14629 rev 8 828/904 interrupt status register isr 32-bit base + 0x0010 channel pending register ceocfr0 32-bit base + 0x0014 channel pending register ceocfr1 32-bit base + 0x0018 channel pending register ceocfr2 32-bit base + 0x001c interrupt mask register imr 32-bit base + 0x0020 channel interrupt mask register cimr0 32-bit base + 0x0024 channel interrupt mask register cimr1 32-bit base + 0x0028 channel interrupt mask register cimr2 32-bit base + 0x002c watchdog threshold interrupt status register wtisr 32-bit base + 0x0030 watchdog threshold interrupt mask register wtimr 32-bit base + 0x0034 reserved ? ? base + 0x0038 ? 0x004f threshold control register 0 trc0 32-bit base + 0x0050 threshold control register 1 trc1 32-bit base + 0x0054 threshold control register 2 trc2 32-bit base + 0x0058 threshold control register 3 trc3 32-bit base + 0x005c threshold register 0 thrhlr0 32-bit base + 0x0060 threshold register 1 thrhlr1 32-bit base + 0x0064 threshold register 2 thrhlr2 32-bit base + 0x0068 threshold register 3 thrhlr3 32-bit base + 0x006c presampling control register pscr 32-bit base + 0x0080 presampling register 0 psr0 32-bit base + 0x0084 presampling register 1 psr1 32-bit base + 0x0088 presampling register 2 psr2 32-bit base + 0x008c reserved ? ? base + 0x0090 ? 0x0093 conversion timing register 0 ctr0 32-bit base + 0x0094 conversion timing register 1 ctr1 32-bit base + 0x0098 conversion timing register 2 ctr2 32-bit base + 0x009c reserved ? ? base + 0x00a0 ? 0x00a3 normal conversion mask register 0 ncmr0 32-bit base + 0x00a4 normal conversion mask register 1 ncmr1 32-bit base + 0x00a8 normal conversion mask register 2 ncmr2 32-bit base + 0x00ac table 432. detailed register map (continued) register description register name used size address register map RM0017 829/904 doc id 14629 rev 8 reserved ? ? base + 0x00b0 ? 0x00b3 injected conversion mask register 0 jcmr0 32-bit base + 0x00b4 injected conversion mask register 1 jcmr1 32-bit base + 0x00b8 injected conversion mask register 2 jcmr2 32-bit base + 0x00bc reserved ? ? base + 0x00c0 ? 0x00c3 decode signals delay register dsdr 32-bit base + 0x00c4 power-down exit delay register pdedr 32-bit base + 0x00c8 reserved ? ? base + 0x00cc ? 0x00ff channel 0 data register cdr0 32-bit base + 0x0100 channel 1 data register cdr1 32-bit base + 0x0104 channel 2 data register cdr2 32-bit base + 0x0108 channel 3 data register cdr3 32-bit base + 0x010c channel 4 data register cdr4 32-bit base + 0x0110 channel 5 data register cdr5 32-bit base + 0x0114 channel 6 data register cdr6 32-bit base + 0x0118 channel 7 data register cdr7 32-bit base + 0x011c channel 8 data register cdr8 32-bit base + 0x0120 channel 9 data register cdr9 32-bit base + 0x0124 channel 10 data register cdr10 32-bit base + 0x0128 channel 11 data register cdr11 32-bit base + 0x012c channel 12 data register cdr12 32-bit base + 0x0130 channel 13 data register cdr13 32-bit base + 0x0134 channel 14 data register cdr14 32-bit base + 0x0138 channel 15 data register cdr15 32-bit base + 0x013c reserved ? ? base + 0x0140 ? 0x017f channel 32 data register cdr32 32-bit base + 0x0180 channel 33 data register cdr33 32-bit base + 0x0184 channel 34 data register cdr34 32-bit base + 0x0188 channel 35 data register cdr35 32-bit base + 0x018c channel 36 data register cdr36 32-bit base + 0x0190 channel 37 data register cdr37 32-bit base + 0x0194 table 432. detailed register map (continued) register description register name used size address RM0017 register map doc id 14629 rev 8 830/904 channel 38 data register cdr38 32-bit base + 0x0198 channel 39 data register cdr39 32-bit base + 0x019c channel 40 data register cdr40 32-bit base + 0x01a0 channel 41 data register cdr41 32-bit base + 0x01a4 channel 42 data register cdr42 32-bit base + 0x01a8 channel 43 data register cdr43 32-bit base + 0x01ac channel 44 data register cdr44 32-bit base + 0x01b0 channel 45 data register cdr45 32-bit base + 0x01b4 channel 46 data register cdr46 32-bit base + 0x01b8 channel 47 data register cdr47 32-bit base + 0x01bc reserved ? ? base + 0x01c0 ? 0x01ff channel 64 data register cdr64 32-bit base + 0x0200 channel 65 data register cdr65 32-bit base + 0x0204 channel 66 data register cdr66 32-bit base + 0x0208 channel 67 data register cdr67 32-bit base + 0x020c channel 68 data register cdr68 32-bit base + 0x0210 channel 69 data register cdr69 32-bit base + 0x0214 channel 70 data register cdr70 32-bit base + 0x0218 channel 71 data register cdr71 32-bit base + 0x021c channel 72 data register cdr72 32-bit base + 0x0220 channel 73 data register cdr73 32-bit base + 0x0224 channel 74 data register cdr74 32-bit base + 0x0228 channel 75 data register cdr75 32-bit base + 0x022c channel 76 data register cdr76 32-bit base + 0x0230 channel 77 data register cdr77 32-bit base + 0x0234 channel 78 data register cdr78 32-bit base + 0x0238 channel 79 data register cdr79 32-bit base + 0x023c channel 80 data register cdr80 32-bit base + 0x0240 channel 81 data register cdr81 32-bit base + 0x0244 channel 82 data register cdr82 32-bit base + 0x0248 channel 83 data register cdr83 32-bit base + 0x024c channel 84 data register cdr84 32-bit base + 0x0250 channel 85 data register cdr85 32-bit base + 0x0254 table 432. detailed register map (continued) register description register name used size address register map RM0017 831/904 doc id 14629 rev 8 channel 86 data register cdr86 32-bit base + 0x0258 channel 87 data register cdr87 32-bit base + 0x025c channel 88 data register cdr88 32-bit base + 0x0260 channel 89 data register cdr89 32-bit base + 0x0264 channel 90 data register cdr90 32-bit base + 0x0268 channel 91 data register cdr91 32-bit base + 0x026c channel 92 data register cdr92 32-bit base + 0x0270 channel 93 data register cdr93 32-bit base + 0x0274 channel 94 data register cdr94 32-bit base + 0x0278 channel 95 data register cdr95 32-bit base + 0x027c reserved ? ? base + 0x0280 ? 0x02ff i2c 0xffe3_0000 i2c bus address register ibad 8-bit base + 0x0000 i2c bus frequency divider register ibfd 8-bit base + 0x0001 i2c bus control register ibcr 8-bit base + 0x0002 i2c bus status register ibsr 8-bit base + 0x0003 i2c bus data i/o register ibdr 8-bit base + 0x0004 i2c bus interrupt configuration register ibic 8-bit base + 0x0005 reserved ? ? (base + 0x0006) ? (base + 0xffff) linflex_0 0xffe4_0000 lin control register 1 lincr1 32-bit base + 0x0000 lin interrupt enable register linier 32-bit base + 0x0004 lin status register linsr 32-bit base + 0x0008 lin error status register linesr 32-bit base + 0x000c uart mode control register uartcr 32-bit base + 0x0010 uart mode status register uartsr 32-bit base + 0x0014 lin timeout control status regi ster lintcsr 32-bit base + 0x0018 lin output compare register linocr 32-bit base + 0x001c lin timeout control register lintocr 32-bit base + 0x0020 lin fractional baud rate register linfbrr 32-bit base + 0x0024 lin integer baud rate register linibrr 32-bit base + 0x0028 lin checksum field register lincfr 32-bit base + 0x002c lin control register 2 lincr2 32-bit base + 0x0030 table 432. detailed register map (continued) register description register name used size address RM0017 register map doc id 14629 rev 8 832/904 buffer identifier register bidr 32-bit base + 0x0034 buffer data register lsb bdrl 32-bit base + 0x0038 buffer data register msb bdrm 32-bit base + 0x003c identifier filter enable register ifer 32-bit base + 0x0040 identifier filter match i ndex ifmi 32-bit base + 0x0044 identifier filter mode regi ster ifmr 32-bit base + 0x0048 identifier filter control regi ster 0 ifcr0 32-bit base + 0x004c identifier filter control regi ster 1 ifcr1 32-bit base + 0x0050 identifier filter control regi ster 2 ifcr2 32-bit base + 0x0054 identifier filter control regi ster 3 ifcr3 32-bit base + 0x0058 identifier filter control regi ster 4 ifcr4 32-bit base + 0x005c identifier filter control regi ster 5 ifcr5 32-bit base + 0x0060 identifier filter control regi ster 6 ifcr6 32-bit base + 0x0064 identifier filter control regi ster 7 ifcr7 32-bit base + 0x0068 identifier filter control regi ster 8 ifcr8 32-bit base + 0x006c identifier filter control regi ster 9 ifcr9 32-bit base + 0x0070 identifier filter control regi ster 10 ifcr10 32-bit base + 0x0074 identifier filter control regi ster 11 ifcr11 32-bit base + 0x0078 identifier filter control regi ster 12 ifcr12 32-bit base + 0x007c identifier filter control regi ster 13 ifcr13 32-bit base + 0x0080 identifier filter control regi ster 14 ifcr14 32-bit base + 0x0084 identifier filter control regi ster 15 ifcr15 32-bit base + 0x0088 linflex_1 0xffe4_4000 lin control register 1 lincr1 32-bit base + 0x0000 lin interrupt enable register linier 32-bit base + 0x0004 lin status register linsr 32-bit base + 0x0008 lin error status register linesr 32-bit base + 0x000c uart mode control register uartcr 32-bit base + 0x0010 uart mode status register uartsr 32-bit base + 0x0014 lin timeout control status regi ster lintcsr 32-bit base + 0x0018 lin output compare register linocr 32-bit base + 0x001c lin timeout control register lintocr 32-bit base + 0x0020 lin fractional baud rate register linfbrr 32-bit base + 0x0024 lin integer baud rate register linibrr 32-bit base + 0x0028 table 432. detailed register map (continued) register description register name used size address register map RM0017 833/904 doc id 14629 rev 8 lin checksum field register lincfr 32-bit base + 0x002c lin control register 2 lincr2 32-bit base + 0x0030 buffer identifier register bidr 32-bit base + 0x0034 buffer data register lsb bdrl 32-bit base + 0x0038 buffer data register msb bdrm 32-bit base + 0x003c reserved ? ? (base + 0x0040)? (base + 0x7fff) linflex_2 0xffe4_8000 lin control register 1 lincr1 32-bit base + 0x0000 lin interrupt enable register linier 32-bit base + 0x0004 lin status register linsr 32-bit base + 0x0008 lin error status register linesr 32-bit base + 0x000c uart mode control register uartcr 32-bit base + 0x0010 uart mode status register uartsr 32-bit base + 0x0014 lin timeout control status regi ster lintcsr 32-bit base + 0x0018 lin output compare register linocr 32-bit base + 0x001c lin timeout control register lintocr 32-bit base + 0x0020 lin fractional baud rate register linfbrr 32-bit base + 0x0024 lin integer baud rate register linibrr 32-bit base + 0x0028 lin checksum field register lincfr 32-bit base + 0x002c lin control register 2 lincr2 32-bit base + 0x0030 buffer identifier register bidr 32-bit base + 0x0034 buffer data register lsb bdrl 32-bit base + 0x0038 buffer data register msb bdrm 32-bit base + 0x003c reserved ? ? (base + 0x0040)? (base + 0xbfff) linflex_3 0xffe4_c000 lin control register 1 lincr1 32-bit base + 0x0000 lin interrupt enable register linier 32-bit base + 0x0004 lin status register linsr 32-bit base + 0x0008 lin error status register linesr 32-bit base + 0x000c uart mode control register uartcr 32-bit base + 0x0010 uart mode status register uartsr 32-bit base + 0x0014 lin timeout control status regi ster lintcsr 32-bit base + 0x0018 lin output compare register linocr 32-bit base + 0x001c table 432. detailed register map (continued) register description register name used size address RM0017 register map doc id 14629 rev 8 834/904 lin timeout control register lintocr 32-bit base + 0x0020 lin fractional baud rate register linfbrr 32-bit base + 0x0024 lin integer baud rate register linibrr 32-bit base + 0x0028 lin checksum field register lincfr 32-bit base + 0x002c lin control register 2 lincr2 32-bit base + 0x0030 buffer identifier register bidr 32-bit base + 0x0034 buffer data register lsb bdrl 32-bit base + 0x0038 buffer data register msb bdrm 32-bit base + 0x003c reserved ? ? (base + 0x0040)? (base + 0x3fff) ctu 0xffe6_4000 reserved ? ? base + 0x0000 ? base + 0x002c event configuration register0 c tu_evtcfgr0 32-bit base + 0x0030 event configuration register1 c tu_evtcfgr1 32-bit base + 0x0034 event configuration register2 c tu_evtcfgr2 32-bit base + 0x0038 event configuration register3 c tu_evtcfgr3 32-bit base + 0x003c event configuration register4 c tu_evtcfgr4 32-bit base + 0x0040 event configuration register5 c tu_evtcfgr5 32-bit base + 0x0044 event configuration register6 c tu_evtcfgr6 32-bit base + 0x0048 event configuration register7 c tu_evtcfgr7 32-bit base + 0x004c event configuration register8 c tu_evtcfgr8 32-bit base + 0x0050 event configuration register9 c tu_evtcfgr9 32-bit base + 0x0054 event configuration register10 ct u_evtcfgr10 32-bit base + 0x0058 event configuration register11 ct u_evtcfgr11 32-bit base + 0x005c event configuration register12 ct u_evtcfgr12 32-bit base + 0x0060 event configuration register13 ct u_evtcfgr13 32-bit base + 0x0064 event configuration register14 ct u_evtcfgr14 32-bit base + 0x0068 event configuration register15 ct u_evtcfgr15 32-bit base + 0x006c event configuration register16 ct u_evtcfgr16 32-bit base + 0x0070 event configuration register17 ct u_evtcfgr17 32-bit base + 0x0074 event configuration register18 ct u_evtcfgr18 32-bit base + 0x0078 event configuration register19 ct u_evtcfgr19 32-bit base + 0x007c event configuration register20 ct u_evtcfgr20 32-bit base + 0x0080 event configuration register21 ct u_evtcfgr21 32-bit base + 0x0084 table 432. detailed register map (continued) register description register name used size address register map RM0017 835/904 doc id 14629 rev 8 event configuration register22 ct u_evtcfgr22 32-bit base + 0x0088 event configuration register23 ct u_evtcfgr23 32-bit base + 0x008c event configuration register24 ct u_evtcfgr24 32-bit base + 0x0090 event configuration register25 ct u_evtcfgr25 32-bit base + 0x0094 event configuration register26 ct u_evtcfgr26 32-bit base + 0x0098 event configuration register27 ct u_evtcfgr27 32-bit base + 0x009c event configuration register28 ctu_evtcfgr28 32-bit base + 0x00a0 event configuration register29 ctu_evtcfgr29 32-bit base + 0x00a4 event configuration register30 ctu_evtcfgr30 32-bit base + 0x00a8 event configuration register31 ct u_evtcfgr31 32-bit base + 0x00ac event configuration register32 ctu_evtcfgr32 32-bit base + 0x00b0 event configuration register33 ctu_evtcfgr33 32-bit base + 0x00b4 event configuration register34 ctu_evtcfgr34 32-bit base + 0x00b8 event configuration register35 ct u_evtcfgr35 32-bit base + 0x00bc event configuration register36 ct u_evtcfgr36 32-bit base + 0x00c0 event configuration register37 ct u_evtcfgr37 32-bit base + 0x00c4 event configuration register38 ct u_evtcfgr38 32-bit base + 0x00c8 event configuration register39 ct u_evtcfgr39 32-bit base + 0x00cc event configuration register40 ct u_evtcfgr40 32-bit base + 0x00d0 event configuration register41 ct u_evtcfgr41 32-bit base + 0x00d4 event configuration register42 ct u_evtcfgr42 32-bit base + 0x00d8 event configuration register43 ct u_evtcfgr43 32-bit base + 0x00dc event configuration register44 ctu_evtcfgr44 32-bit base + 0x00e0 event configuration register45 ctu_evtcfgr45 32-bit base + 0x00e4 event configuration register46 ctu_evtcfgr46 32-bit base + 0x00e8 event configuration register47 ct u_evtcfgr47 32-bit base + 0x00ec event configuration register48 ct u_evtcfgr48 32-bit base + 0x00f0 event configuration register49 ct u_evtcfgr49 32-bit base + 0x00f4 event configuration register50 ct u_evtcfgr50 32-bit base + 0x00f8 event configuration register51 ct u_evtcfgr51 32-bit base + 0x00fc event configuration register52 ct u_evtcfgr52 32-bit base + 0x0100 event configuration register53 ct u_evtcfgr53 32-bit base + 0x0104 event configuration register54 ct u_evtcfgr54 32-bit base + 0x0108 event configuration register55 ct u_evtcfgr55 32-bit base + 0x010c table 432. detailed register map (continued) register description register name used size address RM0017 register map doc id 14629 rev 8 836/904 event configuration register56 ct u_evtcfgr56 32-bit base + 0x0110 event configuration register57 ct u_evtcfgr57 32-bit base + 0x0114 event configuration register58 ct u_evtcfgr58 32-bit base + 0x0118 event configuration register59 ct u_evtcfgr59 32-bit base + 0x011c event configuration register60 ct u_evtcfgr60 32-bit base + 0x0120 event configuration register61 ct u_evtcfgr61 32-bit base + 0x0124 event configuration register62 ct u_evtcfgr62 32-bit base + 0x0128 event configuration register63 ct u_evtcfgr63 32-bit base + 0x012c reserved ? ? (base + 0x0130) ? 0xffe6_ffff can sampler 0xffe7_0000 control status register cans_cr 32-bit base + 0x0000 sample register 0 can_sr0 32-bit base + 0x0004 sample register 1 can_sr1 32-bit base + 0x0008 sample register 2 can_sr2 32-bit base + 0x000c sample register 3 can_sr3 32-bit base + 0x0010 sample register 4 can_sr4 32-bit base + 0x0014 sample register 5 can_sr5 32-bit base + 0x0018 sample register 6 can_sr6 32-bit base + 0x001c sample register 7 can_sr7 32-bit base + 0x0020 sample register 8 can_sr8 32-bit base + 0x0024 sample register 9 can_sr9 32-bit base + 0x0028 sample register 10 can_sr10 32-bit base + 0x002c sample register 11 can_sr11 32-bit base + 0x0030 reserved ? ? (base + 0x0034) ? 0xfff0_ffff mpu 0xfff1_0000 mpu control/error status register mpu_cesr 32-bit base + 0x0000 reserved ? ? base + 0x0004 ? base + 0x000f mpu error address register, slave port 0 mpu_ear0 32-bit base + 0x0010 mpu error detail register, slave port 0 mpu_edr0 32-bit base + 0x0014 mpu error address register, slave port 1 mpu_ear1 32-bit base + 0x0018 mpu error detail register, slave port 1 mpu_edr1 32-bit base + 0x001c mpu error address register, slave port 2 mpu_ear2 32-bit base + 0x0020 table 432. detailed register map (continued) register description register name used size address register map RM0017 837/904 doc id 14629 rev 8 mpu error detail register, slave port 2 mpu_edr2 32-bit base + 0x0024 mpu error address register, slave port 3 mpu_ear3 32-bit base + 0x0028 mpu error detail register, slave port 3 mpu_edr3 32-bit base + 0x002c reserved ? ? base + 0x0030 ? base + 0x03ff mpu region descriptor 0 mpu_rgd0 128 base + 0x0400 mpu region descriptor 1 mpu_rgd1 128 base + 0x0410 mpu region descriptor 2 mpu_rgd2 128 base + 0x0420 mpu region descriptor 3 mpu_rgd3 128 base + 0x0430 mpu region descriptor 4 mpu_rgd4 128 base + 0x0440 mpu region descriptor 5 mpu_rgd5 128 base + 0x0450 mpu region descriptor 6 mpu_rgd6 128 base + 0x0460 mpu region descriptor 7 mpu_rgd7 128 base + 0x0470 reserved ? ? base + 0x0480 ? base + 0x07ff mpu rgd alternate access control 0 mpu_rgdaac0 32-bit base + 0x0800 mpu rgd alternate access control 1 mpu_rgdaac1 32-bit base + 0x0804 mpu rgd alternate access control 2 mpu_rgdaac2 32-bit base + 0x0808 mpu rgd alternate access control 3 mpu_rgdaac3 32-bit base + 0x080c mpu rgd alternate access control 4 mpu_rgdaac4 32-bit base + 0x0810 mpu rgd alternate access control 5 mpu_rgdaac5 32-bit base + 0x0814 mpu rgd alternate access control 6 mpu_rgdaac6 32-bit base + 0x0818 mpu rgd alternate access control 7 mpu_rgdaac7 32-bit base + 0x081c reserved ? ? base + 0x0820 ? base + 0x3fff swt 0xfff3_8000 control register swt_cr 32-bit base + 0x0000 swt interrupt register swt_ir 32-bit base + 0x0004 swt time-out register swt_to 32-bit base + 0x0008 swt window register swt_wn 32-bit base + 0x000c swt service register swt_sr 32-bit base + 0x0010 swt counter output register swt_co 32-bit base + 0x0014 reserved ? ? (base + 0x0018) ? 0xfff3_bfff stm 0xfff3_c000 table 432. detailed register map (continued) register description register name used size address RM0017 register map doc id 14629 rev 8 838/904 control register stm_cr 32-bit base + 0x0000 stm count register stm_cnt 32-bit base + 0x0004 reserved ? ? base + (0x0008 ? 0x000f) stm channel 0 control register stm_ccr0 32-bit base + 0x00010 stm channel 0 interrupt register stm_cir0 32-bit base + 0x00014 stm channel 0 compare register stm_cmp0 32-bit base + 0x00018 reserved ? ? base + (0x001c ? 0x001f) stm channel 1 control register stm_ccr1 32-bit base + 0x00020 stm channel 1 interrupt register stm_cir1 32-bit base + 0x00024 stm channel 1 compare register stm_cmp1 32-bit base + 0x00028 reserved ? ? base + (0x002c ? 0x002f) stm channel 2 control register stm_ccr2 32-bit base + 0x00030 stm channel 2 interrupt register stm_cir2 32-bit base + 0x00034 stm channel 2 compare register stm_cmp2 32-bit base + 0x00038 reserved ? ? base + (0x003c ? 0x003f) stm channel 3 control register stm_ccr3 32-bit base + 0x00040 stm channel 3 interrupt register stm_cir3 32-bit base + 0x00044 stm channel 3 compare register stm_cmp3 32-bit base + 0x00048 reserved ? ? base + (0x003c ? 0x03fff) ecsm 0xfff4_0000 processor core type ecsm_pct 16-bit base + 0x0000 soc-defined platform revision ecsm_rev 16-bit base + 0x0002 reserved ? ? base + (0x0004 ? 0x0007) ips on-platform module configuration ecsm_imc 32-bit base + 0x0008 reserved ? ? base + (0x000c ? 0x0012) miscellaneous wakeup control register ecsm_mwcr 8-bit base + 0x0013 reserved ? ? base + (0x0014 ? 0x001e) miscellaneous interrupt register ecsm_mir 8-bit base + 0x001f table 432. detailed register map (continued) register description register name used size address register map RM0017 839/904 doc id 14629 rev 8 reserved ? ? base + (0x0020 ? 0x0023) miscellaneous user defined control register ecsm_mudcr 32-bit base + 0x0024 reserved ? ? base + (0x0028 ? 0x0042) ecc configuration register ecsm_ecr 8-bit base + 0x0043 reserved ? ? base + (0x0044 ? 0x0046) ecc status register ecsm _esr 8-bit base + 0x0047 reserved ? ? base + (0x0048 ? 0x0049) ecc error generation register ecsm_eegr 16-bit base + 0x004a reserved ? ? base + (0x04c ? 0x004f) platform flash ecc error address register ecsm_pfear 32-bit base + 0x0050 reserved ? ? base + (0x054 ? 0x0055) platform flash ecc master number register ecsm_pfemr 8-bit base + 0x0056 platform flash ecc attributes register ecsm_pfeat 8-bit base + 0x0057 reserved ? ? base + (0x058 ? 0x005b) platform flash ecc data register ecsm_pfedr 32-bit base + 0x005c platform ram ecc address register ecsm_prear 32-bit base + 0x0060 reserved ? ? base + 0x064 platform ram ecc syndrome register ecsm_presr 8-bit base + 0x0065 platform ram ecc master number register ecsm_premr 8-bit base + 0x0066 platform ram ecc attributes register ecsm_preat 8-bit base + 0x0067 reserved ? ? base + (0x068 ? 0x006b) platform ram ecc data register ecsm_predr 32-bit base + 0x006c reserved ? ? base + (0x0070 ? 0x3fff) intc 0xfff4_8000 block configuration register intc_pbcr 32-bit base + 0x0000 reserved ? ? base + (0x0004 ? 0x0007) current priority register intc_cpr 32-bit base + 0x0008 table 432. detailed register map (continued) register description register name used size address RM0017 register map doc id 14629 rev 8 840/904 reserved ? ? base + (0x000c ? 0x000f) interrupt acknowledge register intc_iackr 32-bit base + 0x0010 reserved ? ? base + (0x0014 ? 0x0017) end of interrupt register intc_eoir 32-bit base + 0x0018 reserved ? ? base + (0x001c ? 0x001f) software set/clear interrupt register intc_sscir0_3 32-bit base + 0x0020 software set/clear interrupt register intc_sscir4_7 32-bit base + 0x0024 reserved ? ? base + (0x0028 ? 0x003f) priority select register intc_psr0_3 32-bit base + 0x0040 priority select register intc_psr4_7 32-bit base + 0x0044 priority select register intc_psr8_11 32-bit base + 0x0048 priority select register intc_psr12_15 32-bit base + 0x004c priority select register intc_psr16_19 32-bit base + 0x0050 priority select register intc_psr20_23 32-bit base + 0x0054 priority select register intc_psr24_27 32-bit base + 0x0058 priority select register intc_psr28_31 32-bit base + 0x005c priority select register intc_psr32_35 32-bit base + 0x0060 priority select register intc_psr36_39 32-bit base + 0x0064 priority select register intc_psr40_43 32-bit base + 0x0068 priority select register intc_psr44_47 32-bit base + 0x006c priority select register intc_psr48_51 32-bit base + 0x0070 priority select register intc_psr52_55 32-bit base + 0x0074 priority select register intc_psr56_59 32-bit base + 0x0078 priority select register intc_psr60_63 32-bit base + 0x007c priority select register intc_psr64_67 32-bit base + 0x0080 priority select register intc_psr68_71 32-bit base + 0x0084 priority select register intc_psr72_75 32-bit base + 0x0088 priority select register intc_psr76_79 32-bit base + 0x008c priority select register intc_psr80_83 32-bit base + 0x0090 priority select register intc_psr84_87 32-bit base + 0x0094 priority select register intc_psr88_91 32-bit base + 0x0098 table 432. detailed register map (continued) register description register name used size address register map RM0017 841/904 doc id 14629 rev 8 priority select register intc_psr92_95 32-bit base + 0x009c priority select register intc_psr96_99 32-bit base + 0x00a0 priority select register intc_psr100_103 32-bit base + 0x00a4 priority select register intc_psr104_107 32-bit base + 0x00a8 priority select register intc_psr108_111 32-bit base + 0x00ac priority select register intc_psr112_115 32-bit base + 0x00b0 priority select register intc_psr116_119 32-bit base + 0x00b4 priority select register intc_psr120_123 32-bit base + 0x00b8 priority select register intc_psr124_127 32-bit base + 0x00bc priority select register intc_psr128_131 32-bit base + 0x00c0 priority select register intc_psr132_135 32-bit base + 0x00c4 priority select register intc_psr136_139 32-bit base + 0x00c8 priority select register intc_psr140_143 32-bit base + 0x00cc priority select register intc_psr144_147 32-bit base + 0x00d0 priority select register intc_psr148_151 32-bit base + 0x00d4 priority select register intc_psr152_155 32-bit base + 0x00d8 priority select register intc_psr156_159 32-bit base + 0x00dc priority select register intc_psr160_163 32-bit base + 0x00e0 priority select register intc_psr164_167 32-bit base + 0x00e4 priority select register intc_psr168_171 32-bit base + 0x00e8 priority select register intc_psr172_175 32-bit base + 0x00ec priority select register intc_psr176_179 32-bit base + 0x00f0 priority select register intc_psr180_183 32-bit base + 0x00f4 priority select register intc_psr184_187 32-bit base + 0x00f8 priority select register intc_psr188_191 32-bit base + 0x00fc priority select register intc_psr192_195 32-bit base + 0x0100 priority select register intc_psr196_199 32-bit base + 0x0104 priority select register intc_psr200_203 32-bit base + 0x0108 priority select register intc_psr204_207 32-bit base + 0x010c priority select register intc_psr208_210 32-bit base + 0x0110 dspi_0 0xfff9_0000 module configuration register pmcr 32-bit base + 0x0000 reserved ? ? (base + 0x0004) ? (base + 0x0007) table 432. detailed register map (continued) register description register name used size address RM0017 register map doc id 14629 rev 8 842/904 transfer count register tcr 32-bit base + 0x0008 clock and transfer attribute registers ctar0 32-bit base + 0x000c clock and transfer attribute registers ctar1 32-bit base + 0x0010 clock and transfer attribute registers ctar2 32-bit base + 0x0014 clock and transfer attribute registers ctar3 32-bit base + 0x0018 clock and transfer attribute registers ctar4 32-bit base + 0x001c clock and transfer attribute registers ctar5 32-bit base + 0x0020 reserved ? ? (base + 0x0024) ? (base + 0x0028) status register sr 32-bit base + 0x002c dspi interrupt request enable register rser 32-bit base + 0x0030 push tx fifo register pushr 32-bit base + 0x0034 pop rx fifo register popr 32-bit base + 0x0038 dspi transmit fifo registers txfr0 32-bit base + 0x003c dspi transmit fifo registers txfr1 32-bit base + 0x0040 dspi transmit fifo registers txfr2 32-bit base + 0x0044 dspi transmit fifo registers txfr3 32-bit base + 0x0048 reserved ? ? (base + 0x004c) ? (base + 0x007b) receive fifo registers rxfr0 32-bit base + 0x007c receive fifo registers rxfr1 32-bit base + 0x0080 receive fifo registers rxfr2 32-bit base + 0x0084 receive fifo registers rxfr3 32-bit base + 0x0088 reserved ? ? (base + 0x008c) ? (base + 0x3fff) dspi_1 0xfff9_4000 module configuration register pmcr 32-bit base + 0x0000 reserved ? ? (base + 0x0004) ? (base + 0x0007) transfer count register tcr 32-bit base + 0x0008 clock and transfer attribute registers ctar0 32-bit base + 0x000c clock and transfer attribute registers ctar1 32-bit base + 0x0010 clock and transfer attribute registers ctar2 32-bit base + 0x0014 clock and transfer attribute registers ctar3 32-bit base + 0x0018 clock and transfer attribute registers ctar4 32-bit base + 0x001c table 432. detailed register map (continued) register description register name used size address register map RM0017 843/904 doc id 14629 rev 8 clock and transfer attribute registers ctar5 32-bit base + 0x0020 clock and transfer attribute registers ctar6 32-bit base + 0x0024 clock and transfer attribute registers ctar7 32-bit base + 0x0028 status register sr 32-bit base + 0x002c dspi interrupt request enable register rser 32-bit base + 0x0030 push tx fifo register pushr 32-bit base + 0x0034 pop rx fifo register popr 32-bit base + 0x0038 dspi transmit fifo registers txfr0 32-bit base + 0x003c dspi transmit fifo registers txfr1 32-bit base + 0x0040 dspi transmit fifo registers txfr2 32-bit base + 0x0044 dspi transmit fifo registers txfr3 32-bit base + 0x0048 reserved ? ? (base + 0x004c) ? (base + 0x007b) receive fifo registers rxfr0 32-bit base + 0x007c receive fifo registers rxfr1 32-bit base + 0x0080 receive fifo registers rxfr2 32-bit base + 0x0084 receive fifo registers rxfr3 32-bit base + 0x0088 reserved ? ? (base + 0x0090) ? (base + 0x3fff) dspi_2 0xfff9_8000 module configuration register pmcr 32-bit base + 0x0000 reserved ? ? (base + 0x0004) ? (base + 0x0007) transfer count register tcr 32-bit base + 0x0008 clock and transfer attribute registers ctar0 32-bit base + 0x000c clock and transfer attribute registers ctar1 32-bit base + 0x0010 clock and transfer attribute registers ctar2 32-bit base + 0x0014 clock and transfer attribute registers ctar3 32-bit base + 0x0018 clock and transfer attribute registers ctar4 32-bit base + 0x001c clock and transfer attribute registers ctar5 32-bit base + 0x0020 clock and transfer attribute registers ctar6 32-bit base + 0x0024 clock and transfer attribute registers ctar7 32-bit base + 0x0028 status register sr 32-bit base + 0x002c dspi interrupt request enable register rser 32-bit base + 0x0030 push tx fifo register pushr 32-bit base + 0x0034 table 432. detailed register map (continued) register description register name used size address RM0017 register map doc id 14629 rev 8 844/904 pop rx fifo register popr 32-bit base + 0x0038 dspi transmit fifo registers txfr0 32-bit base + 0x003c dspi transmit fifo registers txfr1 32-bit base + 0x0040 dspi transmit fifo registers txfr2 32-bit base + 0x0044 dspi transmit fifo registers txfr3 32-bit base + 0x0048 reserved ? ? (base + 0x004c) ? (base + 0x007b) receive fifo registers rxfr0 32-bit base + 0x007c receive fifo registers rxfr1 32-bit base + 0x0080 receive fifo registers rxfr2 32-bit base + 0x0084 receive fifo registers rxfr3 32-bit base + 0x0088 reserved ? ? (base + 0x0090) ? (0xffff_bfff) flexcan_0 0xfffc_0000 module configuration register mcr 32-bit base + 0x0000 control register ctrl 32-bit base + 0x0004 free running timer timer 32-bit base + 0x0008 reserved ? ? base + (0x000c ? 0x000f) rx global mask register rxgmask 32-bit base + 0x0010 rx 14 mask register rx14mask 32-bit base + 0x0014 rx 15 mask register rx15mask 32-bit base + 0x0018 error counter register ecr 32-bit base + 0x001c error and status register esr 32-bit base + 0x0020 interrupt masks 2 register imask2 32-bit base + 0x0024 interrupt masks 1 register imask1 32-bit base + 0x0028 interrupt flags 2 register iflag2 32-bit base + 0x002c interrupt flags 1 register iflag1 32-bit base + 0x0030 reserved ? ? base + (0x0034 ? 0x007f) message buffer 0 mb0 128 bits per mb base + 0x0080 message buffer 1 mb1 128 bits per mb base + 0x0090 message buffer 2 mb2 128 bits per mb base + 0x00a0 table 432. detailed register map (continued) register description register name used size address register map RM0017 845/904 doc id 14629 rev 8 message buffer 3 mb3 128 bits per mb base + 0x00b0 message buffer 4 mb4 128 bits per mb base + 0x00c0 message buffer 5 mb5 128 bits per mb base + 0x00d0 message buffer 6 mb6 128 bits per mb base + 0x00e0 message buffer 7 mb7 128 bits per mb base + 0x00f0 message buffer 8 mb8 128 bits per mb base + 0x0100 message buffer 9 mb9 128 bits per mb base + 0x0110 message buffer 10 mb10 128 bits per mb base + 0x0120 message buffer 11 mb11 128 bits per mb base + 0x0130 message buffer 12 mb12 128 bits per mb base + 0x0140 message buffer 13 mb13 128 bits per mb base + 0x0150 message buffer 14 mb14 128 bits per mb base + 0x0160 message buffer 15 mb15 128 bits per mb base + 0x0170 message buffer 16 mb16 128 bits per mb base + 0x0180 message buffer 17 mb17 128 bits per mb base + 0x0190 message buffer 18 mb18 128 bits per mb base + 0x01a0 message buffer 19 mb19 128 bits per mb base + 0x01b0 message buffer 20 mb20 128 bits per mb base + 0x01c0 message buffer 21 mb21 128 bits per mb base + 0x01d0 message buffer 22 mb22 128 bits per mb base + 0x01e0 table 432. detailed register map (continued) register description register name used size address RM0017 register map doc id 14629 rev 8 846/904 message buffer 23 mb23 128 bits per mb base + 0x01f0 message buffer 24 mb24 128 bits per mb base + 0x0200 message buffer 25 mb25 128 bits per mb base + 0x0210 message buffer 26 mb26 128 bits per mb base + 0x0220 message buffer 27 mb27 128 bits per mb base + 0x0230 message buffer 28 mb28 128 bits per mb base + 0x0240 message buffer 29 mb29 128 bits per mb base + 0x0250 message buffer 30 mb30 128 bits per mb base + 0x0260 message buffer 31 mb31 128 bits per mb base + 0x0270 message buffer 32 mb32 128 bits per mb base + 0x0280 message buffer 33 mb33 128 bits per mb base + 0x0290 message buffer 34 mb34 128 bits per mb base + 0x02a0 message buffer 35 mb35 128 bits per mb base + 0x02b0 message buffer 36 mb36 128 bits per mb base + 0x02c0 message buffer 37 mb37 128 bits per mb base + 0x02d0 message buffer 38 mb38 128 bits per mb base + 0x02e0 message buffer 39 mb39 128 bits per mb base + 0x02f0 message buffer 40 mb40 128 bits per mb base + 0x0300 message buffer 41 mb41 128 bits per mb base + 0x0310 message buffer 42 mb42 128 bits per mb base + 0x0320 table 432. detailed register map (continued) register description register name used size address register map RM0017 847/904 doc id 14629 rev 8 message buffer 43 mb43 128 bits per mb base + 0x0330 message buffer 44 mb44 128 bits per mb base + 0x0340 message buffer 45 mb45 128 bits per mb base + 0x0350 message buffer 46 mb46 128 bits per mb base + 0x0360 message buffer 47 mb47 128 bits per mb base + 0x0370 message buffer 48 mb48 128 bits per mb base + 0x0380 message buffer 49 mb49 128 bits per mb base + 0x0390 message buffer 50 mb50 128 bits per mb base + 0x03a0 message buffer 51 mb51 128 bits per mb base + 0x03b0 message buffer 52 mb52 128 bits per mb base + 0x03c0 message buffer 53 mb53 128 bits per mb base + 0x03d0 message buffer 54 mb54 128 bits per mb base + 0x03e0 message buffer 55 mb55 128 bits per mb base + 0x03f0 message buffer 56 mb56 128 bits per mb base + 0x0400 message buffer 57 mb57 128 bits per mb base + 0x0410 message buffer 58 mb58 128 bits per mb base + 0x0420 message buffer 59 mb59 128 bits per mb base + 0x0430 message buffer 60 mb60 128 bits per mb base + 0x0440 message buffer 61 mb61 128 bits per mb base + 0x0450 message buffer 62 mb62 128 bits per mb base + 0x0460 table 432. detailed register map (continued) register description register name used size address RM0017 register map doc id 14629 rev 8 848/904 message buffer 63 mb63 128 bits per mb base + 0x0470 reserved ? ? (base + 0x0480) ? (base + 0x087f) rx individual mask register 0 rximr0 32-bit base + 0x0880 rx individual mask register 1 rximr1 32-bit base + 0x0884 rx individual mask register 2 rximr2 32-bit base + 0x0888 rx individual mask register 3 rximr3 32-bit base + 0x088c rx individual mask register 4 rximr4 32-bit base + 0x0890 rx individual mask register 5 rximr5 32-bit base + 0x0894 rx individual mask register 6 rximr6 32-bit base + 0x0898 rx individual mask register 7 rximr7 32-bit base + 0x089c rx individual mask register 8 rximr8 32-bit base + 0x08a0 rx individual mask register 9 rximr9 32-bit base + 0x08a4 rx individual mask register 10 rximr10 32-bit base + 0x08a8 rx individual mask register 11 rximr11 32-bit base + 0x08ac rx individual mask register 12 rximr12 32-bit base + 0x08b0 rx individual mask register 13 rximr13 32-bit base + 0x08b4 rx individual mask register 14 rximr14 32-bit base + 0x08b8 rx individual mask register 15 rximr15 32-bit base + 0x08bc rx individual mask register 16 rximr16 32-bit base + 0x08c0 rx individual mask register 17 rximr17 32-bit base + 0x08c4 rx individual mask register 18 rximr18 32-bit base + 0x08c8 rx individual mask register 19 rximr19 32-bit base + 0x08cc rx individual mask register 20 rximr20 32-bit base + 0x08d0 rx individual mask register 21 rximr21 32-bit base + 0x08d4 rx individual mask register 22 rximr22 32-bit base + 0x08d8 rx individual mask register 23 rximr23 32-bit base + 0x08dc rx individual mask register 24 rximr24 32-bit base + 0x08e0 rx individual mask register 25 rximr25 32-bit base + 0x08e4 rx individual mask register 26 rximr26 32-bit base + 0x08e8 rx individual mask register 27 rximr27 32-bit base + 0x08ec rx individual mask register 28 rximr28 32-bit base + 0x08f0 rx individual mask register 29 rximr29 32-bit base + 0x08f4 rx individual mask register 30 rximr30 32-bit base + 0x08f8 table 432. detailed register map (continued) register description register name used size address register map RM0017 849/904 doc id 14629 rev 8 rx individual mask register 31 rximr31 32-bit base + 0x08fc rx individual mask register 32 rximr32 32-bit base + 0x0900 rx individual mask register 33 rximr33 32-bit base + 0x0904 rx individual mask register 34 rximr34 32-bit base + 0x0908 rx individual mask register 35 rximr35 32-bit base + 0x090c rx individual mask register 36 rximr36 32-bit base + 0x0910 rx individual mask register 37 rximr37 32-bit base + 0x0914 rx individual mask register 38 rximr38 32-bit base + 0x0918 rx individual mask register 39 rximr39 32-bit base + 0x091c rx individual mask register 40 rximr40 32-bit base + 0x0920 rx individual mask register 41 rximr41 32-bit base + 0x0924 rx individual mask register 42 rximr42 32-bit base + 0x0928 rx individual mask register 43 rximr43 32-bit base + 0x092c rx individual mask register 44 rximr44 32-bit base + 0x0930 rx individual mask register 45 rximr45 32-bit base + 0x0934 rx individual mask register 46 rximr46 32-bit base + 0x0938 rx individual mask register 47 rximr47 32-bit base + 0x093c rx individual mask register 48 rximr48 32-bit base + 0x0940 rx individual mask register 49 rximr49 32-bit base + 0x0944 rx individual mask register 50 rximr50 32-bit base + 0x0948 rx individual mask register 51 rximr51 32-bit base + 0x094c rx individual mask register 52 rximr52 32-bit base + 0x0950 rx individual mask register 53 rximr53 32-bit base + 0x0954 rx individual mask register 54 rximr54 32-bit base + 0x0958 rx individual mask register 55 rximr55 32-bit base + 0x095c rx individual mask register 56 rximr56 32-bit base + 0x0960 rx individual mask register 57 rximr57 32-bit base + 0x0964 rx individual mask register 58 rximr58 32-bit base + 0x0968 rx individual mask register 59 rximr59 32-bit base + 0x096c rx individual mask register 60 rximr60 32-bit base + 0x0970 rx individual mask register 61 rximr61 32-bit base + 0x0974 rx individual mask register 62 rximr62 32-bit base + 0x0978 rx individual mask register 63 rximr63 32-bit base + 0x097c table 432. detailed register map (continued) register description register name used size address RM0017 register map doc id 14629 rev 8 850/904 reserved ? ? (base + 0x0980) ? (base + 0x3fff) flexcan_1 0xfffc_4000 module configuration mcr 32-bit base + 0x0000 control register ctrl 32-bit base + 0x0004 free running timer timer 32-bit base + 0x0008 reserved ? ? base + (0x000c ? 0x000f) rx global mask register rxgmask 32-bit base + 0x0010 rx 14 mask register rx14mask 32-bit base + 0x0014 rx 15 mask register rx15mask 32-bit base + 0x0018 error counter register ecr 32-bit base + 0x001c error and status register esr 32-bit base + 0x0020 interrupt masks 2 register imask2 32-bit base + 0x0024 interrupt masks 1 register imask1 32-bit base + 0x0028 interrupt flags 2 register iflag2 32-bit base + 0x002c interrupt flags 1 register iflag1 32-bit base + 0x0030 reserved ? ? base + (0x0034 ? 0x007f) message buffer 0 mb0 128 bits per mb base + 0x0080 message buffer 1 mb1 128 bits per mb base + 0x0090 message buffer 2 mb2 128 bits per mb base + 0x00a0 message buffer 3 mb3 128 bits per mb base + 0x00b0 message buffer 4 mb4 128 bits per mb base + 0x00c0 message buffer 5 mb5 128 bits per mb base + 0x00d0 message buffer 6 mb6 128 bits per mb base + 0x00e0 message buffer 7 mb7 128 bits per mb base + 0x00f0 message buffer 8 mb8 128 bits per mb base + 0x0100 message buffer 9 mb9 128 bits per mb base + 0x0110 table 432. detailed register map (continued) register description register name used size address register map RM0017 851/904 doc id 14629 rev 8 message buffer 10 mb10 128 bits per mb base + 0x0120 message buffer 11 mb11 128 bits per mb base + 0x0130 message buffer 12 mb12 128 bits per mb base + 0x0140 message buffer 13 mb13 128 bits per mb base + 0x0150 message buffer 14 mb14 128 bits per mb base + 0x0160 message buffer 15 mb15 128 bits per mb base + 0x0170 message buffer 16 mb16 128 bits per mb base + 0x0180 message buffer 17 mb17 128 bits per mb base + 0x0190 message buffer 18 mb18 128 bits per mb base + 0x01a0 message buffer 19 mb19 128 bits per mb base + 0x01b0 message buffer 20 mb20 128 bits per mb base + 0x01c0 message buffer 21 mb21 128 bits per mb base + 0x01d0 message buffer 22 mb22 128 bits per mb base + 0x01e0 message buffer 23 mb23 128 bits per mb base + 0x01f0 message buffer 24 mb24 128 bits per mb base + 0x0200 message buffer 25 mb25 128 bits per mb base + 0x0210 message buffer 26 mb26 128 bits per mb base + 0x0220 message buffer 27 mb27 128 bits per mb base + 0x0230 message buffer 28 mb28 128 bits per mb base + 0x0240 message buffer 29 mb29 128 bits per mb base + 0x0250 table 432. detailed register map (continued) register description register name used size address RM0017 register map doc id 14629 rev 8 852/904 message buffer 30 mb30 128 bits per mb base + 0x0260 message buffer 31 mb31 128 bits per mb base + 0x0270 message buffer 32 mb32 128 bits per mb base + 0x0280 message buffer 33 mb33 128 bits per mb base + 0x0290 message buffer 34 mb34 128 bits per mb base + 0x02a0 message buffer 35 mb35 128 bits per mb base + 0x02b0 message buffer 36 mb36 128 bits per mb base + 0x02c0 message buffer 37 mb37 128 bits per mb base + 0x02d0 message buffer 38 mb38 128 bits per mb base + 0x02e0 message buffer 39 mb39 128 bits per mb base + 0x02f0 message buffer 40 mb40 128 bits per mb base + 0x0300 message buffer 41 mb41 128 bits per mb base + 0x0310 message buffer 42 mb42 128 bits per mb base + 0x0320 message buffer 43 mb43 128 bits per mb base + 0x0330 message buffer 44 mb44 128 bits per mb base + 0x0340 message buffer 45 mb45 128 bits per mb base + 0x0350 message buffer 46 mb46 128 bits per mb base + 0x0360 message buffer 47 mb47 128 bits per mb base + 0x0370 message buffer 48 mb48 128 bits per mb base + 0x0380 message buffer 49 mb49 128 bits per mb base + 0x0390 table 432. detailed register map (continued) register description register name used size address register map RM0017 853/904 doc id 14629 rev 8 message buffer 50 mb50 128 bits per mb base + 0x03a0 message buffer 51 mb51 128 bits per mb base + 0x03b0 message buffer 52 mb52 128 bits per mb base + 0x03c0 message buffer 53 mb53 128 bits per mb base + 0x03d0 message buffer 54 mb54 128 bits per mb base + 0x03e0 message buffer 55 mb55 128 bits per mb base + 0x03f0 message buffer 56 mb56 128 bits per mb base + 0x0400 message buffer 57 mb57 128 bits per mb base + 0x0410 message buffer 58 mb58 128 bits per mb base + 0x0420 message buffer 59 mb59 128 bits per mb base + 0x0430 message buffer 60 mb60 128 bits per mb base + 0x0440 message buffer 61 mb61 128 bits per mb base + 0x0450 message buffer 62 mb62 128 bits per mb base + 0x0460 message buffer 63 mb63 128 bits per mb base + 0x0470 reserved ? ? (base + 0x0480) ? (base + 0x087f) rx individual mask register 0 rximr0 32-bit base + 0x0880 rx individual mask register 1 rximr1 32-bit base + 0x0884 rx individual mask register 2 rximr2 32-bit base + 0x0888 rx individual mask register 3 rximr3 32-bit base + 0x088c rx individual mask register 4 rximr4 32-bit base + 0x0890 rx individual mask register 5 rximr5 32-bit base + 0x0894 rx individual mask register 6 rximr6 32-bit base + 0x0898 rx individual mask register 7 rximr7 32-bit base + 0x089c rx individual mask register 8 rximr8 32-bit base + 0x08a0 table 432. detailed register map (continued) register description register name used size address RM0017 register map doc id 14629 rev 8 854/904 rx individual mask register 9 rximr9 32-bit base + 0x08a4 rx individual mask register 10 rximr10 32-bit base + 0x08a8 rx individual mask register 11 rximr11 32-bit base + 0x08ac rx individual mask register 12 rximr12 32-bit base + 0x08b0 rx individual mask register 13 rximr13 32-bit base + 0x08b4 rx individual mask register 14 rximr14 32-bit base + 0x08b8 rx individual mask register 15 rximr15 32-bit base + 0x08bc rx individual mask register 16 rximr16 32-bit base + 0x08c0 rx individual mask register 17 rximr17 32-bit base + 0x08c4 rx individual mask register 18 rximr18 32-bit base + 0x08c8 rx individual mask register 19 rximr19 32-bit base + 0x08cc rx individual mask register 20 rximr20 32-bit base + 0x08d0 rx individual mask register 21 rximr21 32-bit base + 0x08d4 rx individual mask register 22 rximr22 32-bit base + 0x08d8 rx individual mask register 23 rximr23 32-bit base + 0x08dc rx individual mask register 24 rximr24 32-bit base + 0x08e0 rx individual mask register 25 rximr25 32-bit base + 0x08e4 rx individual mask register 26 rximr26 32-bit base + 0x08e8 rx individual mask register 27 rximr27 32-bit base + 0x08ec rx individual mask register 28 rximr28 32-bit base + 0x08f0 rx individual mask register 29 rximr29 32-bit base + 0x08f4 rx individual mask register 30 rximr30 32-bit base + 0x08f8 rx individual mask register 31 rximr31 32-bit base + 0x08fc rx individual mask register 32 rximr32 32-bit base + 0x0900 rx individual mask register 33 rximr33 32-bit base + 0x0904 rx individual mask register 34 rximr34 32-bit base + 0x0908 rx individual mask register 35 rximr35 32-bit base + 0x090c rx individual mask register 36 rximr36 32-bit base + 0x0910 rx individual mask register 37 rximr37 32-bit base + 0x0914 rx individual mask register 38 rximr38 32-bit base + 0x0918 rx individual mask register 39 rximr39 32-bit base + 0x091c rx individual mask register 40 rximr40 32-bit base + 0x0920 rx individual mask register 41 rximr41 32-bit base + 0x0924 rx individual mask register 42 rximr42 32-bit base + 0x0928 table 432. detailed register map (continued) register description register name used size address register map RM0017 855/904 doc id 14629 rev 8 rx individual mask register 43 rximr43 32-bit base + 0x092c rx individual mask register 44 rximr44 32-bit base + 0x0930 rx individual mask register 45 rximr45 32-bit base + 0x0934 rx individual mask register 46 rximr46 32-bit base + 0x0938 rx individual mask register 47 rximr47 32-bit base + 0x093c rx individual mask register 48 rximr48 32-bit base + 0x0940 rx individual mask register 49 rximr49 32-bit base + 0x0944 rx individual mask register 50 rximr50 32-bit base + 0x0948 rx individual mask register 51 rximr51 32-bit base + 0x094c rx individual mask register 52 rximr52 32-bit base + 0x0950 rx individual mask register 53 rximr53 32-bit base + 0x0954 rx individual mask register 54 rximr54 32-bit base + 0x0958 rx individual mask register 55 rximr55 32-bit base + 0x095c rx individual mask register 56 rximr56 32-bit base + 0x0960 rx individual mask register 57 rximr57 32-bit base + 0x0964 rx individual mask register 58 rximr58 32-bit base + 0x0968 rx individual mask register 59 rximr59 32-bit base + 0x096c rx individual mask register 60 rximr60 32-bit base + 0x0970 rx individual mask register 61 rximr61 32-bit base + 0x0974 rx individual mask register 62 rximr62 32-bit base + 0x0978 rx individual mask register 63 rximr63 32-bit base + 0x097c reserved ? ? (base + 0x0980) ? (base + 0x3fff) flexcan_2 0xfffc_8000 module configuration mcr 32-bit base + 0x0000 control register ctrl 32-bit base + 0x0004 free running timer timer 32-bit base + 0x0008 reserved ? ? base + (0x000c ? 0x000f) rx global mask register rxgmask 32-bit base + 0x0010 rx 14 mask register rx14mask 32-bit base + 0x0014 rx 15 mask register rx15mask 32-bit base + 0x0018 error counter register ecr 32-bit base + 0x001c error and status register esr 32-bit base + 0x0020 interrupt masks 2 register imask2 32-bit base + 0x0024 table 432. detailed register map (continued) register description register name used size address RM0017 register map doc id 14629 rev 8 856/904 interrupt masks 1 register imask1 32-bit base + 0x0028 interrupt flags 2 register iflag2 32-bit base + 0x002c interrupt flags 1 register iflag1 32-bit base + 0x0030 reserved ? ? base + (0x0034 ? 0x007f) message buffer 0 mb0 128 bits per mb base + 0x0080 message buffer 1 mb1 128 bits per mb base + 0x0090 message buffer 2 mb2 128 bits per mb base + 0x00a0 message buffer 3 mb3 128 bits per mb base + 0x00b0 message buffer 4 mb4 128 bits per mb base + 0x00c0 message buffer 5 mb5 128 bits per mb base + 0x00d0 message buffer 6 mb6 128 bits per mb base + 0x00e0 message buffer 7 mb7 128 bits per mb base + 0x00f0 message buffer 8 mb8 128 bits per mb base + 0x0100 message buffer 9 mb9 128 bits per mb base + 0x0110 message buffer 10 mb10 128 bits per mb base + 0x0120 message buffer 11 mb11 128 bits per mb base + 0x0130 message buffer 12 mb12 128 bits per mb base + 0x0140 message buffer 13 mb13 128 bits per mb base + 0x0150 message buffer 14 mb14 128 bits per mb base + 0x0160 message buffer 15 mb15 128 bits per mb base + 0x0170 message buffer 16 mb16 128 bits per mb base + 0x0180 message buffer 17 mb17 128 bits per mb base + 0x0190 table 432. detailed register map (continued) register description register name used size address register map RM0017 857/904 doc id 14629 rev 8 message buffer 18 mb18 128 bits per mb base + 0x01a0 message buffer 19 mb19 128 bits per mb base + 0x01b0 message buffer 20 mb20 128 bits per mb base + 0x01c0 message buffer 21 mb21 128 bits per mb base + 0x01d0 message buffer 22 mb22 128 bits per mb base + 0x01e0 message buffer 23 mb23 128 bits per mb base + 0x01f0 message buffer 24 mb24 128 bits per mb base + 0x0200 message buffer 25 mb25 128 bits per mb base + 0x0210 message buffer 26 mb26 128 bits per mb base + 0x0220 message buffer 27 mb27 128 bits per mb base + 0x0230 message buffer 28 mb28 128 bits per mb base + 0x0240 message buffer 29 mb29 128 bits per mb base + 0x0250 message buffer 30 mb30 128 bits per mb base + 0x0260 message buffer 31 mb31 128 bits per mb base + 0x0270 message buffer 32 mb32 128 bits per mb base + 0x0280 message buffer 33 mb33 128 bits per mb base + 0x0290 message buffer 34 mb34 128 bits per mb base + 0x02a0 message buffer 35 mb35 128 bits per mb base + 0x02b0 message buffer 36 mb36 128 bits per mb base + 0x02c0 message buffer 37 mb37 128 bits per mb base + 0x02d0 table 432. detailed register map (continued) register description register name used size address RM0017 register map doc id 14629 rev 8 858/904 message buffer 38 mb38 128 bits per mb base + 0x02e0 message buffer 39 mb39 128 bits per mb base + 0x02f0 message buffer 40 mb40 128 bits per mb base + 0x0300 message buffer 41 mb41 128 bits per mb base + 0x0310 message buffer 42 mb42 128 bits per mb base + 0x0320 message buffer 43 mb43 128 bits per mb base + 0x0330 message buffer 44 mb44 128 bits per mb base + 0x0340 message buffer 45 mb45 128 bits per mb base + 0x0350 message buffer 46 mb46 128 bits per mb base + 0x0360 message buffer 47 mb47 128 bits per mb base + 0x0370 message buffer 48 mb48 128 bits per mb base + 0x0380 message buffer 49 mb49 128 bits per mb base + 0x0390 message buffer 50 mb50 128 bits per mb base + 0x03a0 message buffer 51 mb51 128 bits per mb base + 0x03b0 message buffer 52 mb52 128 bits per mb base + 0x03c0 message buffer 53 mb53 128 bits per mb base + 0x03d0 message buffer 54 mb54 128 bits per mb base + 0x03e0 message buffer 55 mb55 128 bits per mb base + 0x03f0 message buffer 56 mb56 128 bits per mb base + 0x0400 message buffer 57 mb57 128 bits per mb base + 0x0410 table 432. detailed register map (continued) register description register name used size address register map RM0017 859/904 doc id 14629 rev 8 message buffer 58 mb58 128 bits per mb base + 0x0420 message buffer 59 mb59 128 bits per mb base + 0x0430 message buffer 60 mb60 128 bits per mb base + 0x0440 message buffer 61 mb61 128 bits per mb base + 0x0450 message buffer 62 mb62 128 bits per mb base + 0x0460 message buffer 63 mb63 128 bits per mb base + 0x0470 reserved ? ? (base + 0x0480) ? (base + 0x087f) rx individual mask register 0 rximr0 32-bit base + 0x0880 rx individual mask register 1 rximr1 32-bit base + 0x0884 rx individual mask register 2 rximr2 32-bit base + 0x0888 rx individual mask register 3 rximr3 32-bit base + 0x088c rx individual mask register 4 rximr4 32-bit base + 0x0890 rx individual mask register 5 rximr5 32-bit base + 0x0894 rx individual mask register 6 rximr6 32-bit base + 0x0898 rx individual mask register 7 rximr7 32-bit base + 0x089c rx individual mask register 8 rximr8 32-bit base + 0x08a0 rx individual mask register 9 rximr9 32-bit base + 0x08a4 rx individual mask register 10 rximr10 32-bit base + 0x08a8 rx individual mask register 11 rximr11 32-bit base + 0x08ac rx individual mask register 12 rximr12 32-bit base + 0x08b0 rx individual mask register 13 rximr13 32-bit base + 0x08b4 rx individual mask register 14 rximr14 32-bit base + 0x08b8 rx individual mask register 15 rximr15 32-bit base + 0x08bc rx individual mask register 16 rximr16 32-bit base + 0x08c0 rx individual mask register 17 rximr17 32-bit base + 0x08c4 rx individual mask register 18 rximr18 32-bit base + 0x08c8 rx individual mask register 19 rximr19 32-bit base + 0x08cc rx individual mask register 20 rximr20 32-bit base + 0x08d0 rx individual mask register 21 rximr21 32-bit base + 0x08d4 rx individual mask register 22 rximr22 32-bit base + 0x08d8 table 432. detailed register map (continued) register description register name used size address RM0017 register map doc id 14629 rev 8 860/904 rx individual mask register 23 rximr23 32-bit base + 0x08dc rx individual mask register 24 rximr24 32-bit base + 0x08e0 rx individual mask register 25 rximr25 32-bit base + 0x08e4 rx individual mask register 26 rximr26 32-bit base + 0x08e8 rx individual mask register 27 rximr27 32-bit base + 0x08ec rx individual mask register 28 rximr28 32-bit base + 0x08f0 rx individual mask register 29 rximr29 32-bit base + 0x08f4 rx individual mask register 30 rximr30 32-bit base + 0x08f8 rx individual mask register 31 rximr31 32-bit base + 0x08fc rx individual mask register 32 rximr32 32-bit base + 0x0900 rx individual mask register 33 rximr33 32-bit base + 0x0904 rx individual mask register 34 rximr34 32-bit base + 0x0908 rx individual mask register 35 rximr35 32-bit base + 0x090c rx individual mask register 36 rximr36 32-bit base + 0x0910 rx individual mask register 37 rximr37 32-bit base + 0x0914 rx individual mask register 38 rximr38 32-bit base + 0x0918 rx individual mask register 39 rximr39 32-bit base + 0x091c rx individual mask register 40 rximr40 32-bit base + 0x0920 rx individual mask register 41 rximr41 32-bit base + 0x0924 rx individual mask register 42 rximr42 32-bit base + 0x0928 rx individual mask register 43 rximr43 32-bit base + 0x092c rx individual mask register 44 rximr44 32-bit base + 0x0930 rx individual mask register 45 rximr45 32-bit base + 0x0934 rx individual mask register 46 rximr46 32-bit base + 0x0938 rx individual mask register 47 rximr47 32-bit base + 0x093c rx individual mask register 48 rximr48 32-bit base + 0x0940 rx individual mask register 49 rximr49 32-bit base + 0x0944 rx individual mask register 50 rximr50 32-bit base + 0x0948 rx individual mask register 51 rximr51 32-bit base + 0x094c rx individual mask register 52 rximr52 32-bit base + 0x0950 rx individual mask register 53 rximr53 32-bit base + 0x0954 rx individual mask register 54 rximr54 32-bit base + 0x0958 rx individual mask register 55 rximr55 32-bit base + 0x095c rx individual mask register 56 rximr56 32-bit base + 0x0960 table 432. detailed register map (continued) register description register name used size address register map RM0017 861/904 doc id 14629 rev 8 rx individual mask register 57 rximr57 32-bit base + 0x0964 rx individual mask register 58 rximr58 32-bit base + 0x0968 rx individual mask register 59 rximr59 32-bit base + 0x096c rx individual mask register 60 rximr60 32-bit base + 0x0970 rx individual mask register 61 rximr61 32-bit base + 0x0974 rx individual mask register 62 rximr62 32-bit base + 0x0978 rx individual mask register 63 rximr63 32-bit base + 0x097c reserved ? ? (base + 0x0980) ? (base + 0x3fff) flexcan_3 0xfffc_c000 module configuration mcr 32-bit base + 0x0000 control register ctrl 32-bit base + 0x0004 free running timer timer 32-bit base + 0x0008 reserved ? ? base + (0x000c ? 0x000f) rx global mask register rxgmask 32-bit base + 0x0010 rx 14 mask register rx14mask 32-bit base + 0x0014 rx 15 mask register rx15mask 32-bit base + 0x0018 error counter register ecr 32-bit base + 0x001c error and status register esr 32-bit base + 0x0020 interrupt masks 2 register imask2 32-bit base + 0x0024 interrupt masks 1 register imask1 32-bit base + 0x0028 interrupt flags 2 register iflag2 32-bit base + 0x002c interrupt flags 1 register iflag1 32-bit base + 0x0030 reserved ? ? base + (0x0034 ? 0x007f) message buffer 0 mb0 128 bits per mb base + 0x0080 message buffer 1 mb1 128 bits per mb base + 0x0090 message buffer 2 mb2 128 bits per mb base + 0x00a0 message buffer 3 mb3 128 bits per mb base + 0x00b0 message buffer 4 mb4 128 bits per mb base + 0x00c0 table 432. detailed register map (continued) register description register name used size address RM0017 register map doc id 14629 rev 8 862/904 message buffer 5 mb5 128 bits per mb base + 0x00d0 message buffer 6 mb6 128 bits per mb base + 0x00e0 message buffer 7 mb7 128 bits per mb base + 0x00f0 message buffer 8 mb8 128 bits per mb base + 0x0100 message buffer 9 mb9 128 bits per mb base + 0x0110 message buffer 10 mb10 128 bits per mb base + 0x0120 message buffer 11 mb11 128 bits per mb base + 0x0130 message buffer 12 mb12 128 bits per mb base + 0x0140 message buffer 13 mb13 128 bits per mb base + 0x0150 message buffer 14 mb14 128 bits per mb base + 0x0160 message buffer 15 mb15 128 bits per mb base + 0x0170 message buffer 16 mb16 128 bits per mb base + 0x0180 message buffer 17 mb17 128 bits per mb base + 0x0190 message buffer 18 mb18 128 bits per mb base + 0x01a0 message buffer 19 mb19 128 bits per mb base + 0x01b0 message buffer 20 mb20 128 bits per mb base + 0x01c0 message buffer 21 mb21 128 bits per mb base + 0x01d0 message buffer 22 mb22 128 bits per mb base + 0x01e0 message buffer 23 mb23 128 bits per mb base + 0x01f0 message buffer 24 mb24 128 bits per mb base + 0x0200 table 432. detailed register map (continued) register description register name used size address register map RM0017 863/904 doc id 14629 rev 8 message buffer 25 mb25 128 bits per mb base + 0x0210 message buffer 26 mb26 128 bits per mb base + 0x0220 message buffer 27 mb27 128 bits per mb base + 0x0230 message buffer 28 mb28 128 bits per mb base + 0x0240 message buffer 29 mb29 128 bits per mb base + 0x0250 message buffer 30 mb30 128 bits per mb base + 0x0260 message buffer 31 mb31 128 bits per mb base + 0x0270 message buffer 32 mb32 128 bits per mb base + 0x0280 message buffer 33 mb33 128 bits per mb base + 0x0290 message buffer 34 mb34 128 bits per mb base + 0x02a0 message buffer 35 mb35 128 bits per mb base + 0x02b0 message buffer 36 mb36 128 bits per mb base + 0x02c0 message buffer 37 mb37 128 bits per mb base + 0x02d0 message buffer 38 mb38 128 bits per mb base + 0x02e0 message buffer 39 mb39 128 bits per mb base + 0x02f0 message buffer 40 mb40 128 bits per mb base + 0x0300 message buffer 41 mb41 128 bits per mb base + 0x0310 message buffer 42 mb42 128 bits per mb base + 0x0320 message buffer 43 mb43 128 bits per mb base + 0x0330 message buffer 44 mb44 128 bits per mb base + 0x0340 table 432. detailed register map (continued) register description register name used size address RM0017 register map doc id 14629 rev 8 864/904 message buffer 45 mb45 128 bits per mb base + 0x0350 message buffer 46 mb46 128 bits per mb base + 0x0360 message buffer 47 mb47 128 bits per mb base + 0x0370 message buffer 48 mb48 128 bits per mb base + 0x0380 message buffer 49 mb49 128 bits per mb base + 0x0390 message buffer 50 mb50 128 bits per mb base + 0x03a0 message buffer 51 mb51 128 bits per mb base + 0x03b0 message buffer 52 mb52 128 bits per mb base + 0x03c0 message buffer 53 mb53 128 bits per mb base + 0x03d0 message buffer 54 mb54 128 bits per mb base + 0x03e0 message buffer 55 mb55 128 bits per mb base + 0x03f0 message buffer 56 mb56 128 bits per mb base + 0x0400 message buffer 57 mb57 128 bits per mb base + 0x0410 message buffer 58 mb58 128 bits per mb base + 0x0420 message buffer 59 mb59 128 bits per mb base + 0x0430 message buffer 60 mb60 128 bits per mb base + 0x0440 message buffer 61 mb61 128 bits per mb base + 0x0450 message buffer 62 mb62 128 bits per mb base + 0x0460 message buffer 63 mb63 128 bits per mb base + 0x0470 reserved ? ? (base + 0x0480) ? (base + 0x087f) rx individual mask register 0 rximr0 32-bit base + 0x0880 table 432. detailed register map (continued) register description register name used size address register map RM0017 865/904 doc id 14629 rev 8 rx individual mask register 1 rximr1 32-bit base + 0x0884 rx individual mask register 2 rximr2 32-bit base + 0x0888 rx individual mask register 3 rximr3 32-bit base + 0x088c rx individual mask register 4 rximr4 32-bit base + 0x0890 rx individual mask register 5 rximr5 32-bit base + 0x0894 rx individual mask register 6 rximr6 32-bit base + 0x0898 rx individual mask register 7 rximr7 32-bit base + 0x089c rx individual mask register 8 rximr8 32-bit base + 0x08a0 rx individual mask register 9 rximr9 32-bit base + 0x08a4 rx individual mask register 10 rximr10 32-bit base + 0x08a8 rx individual mask register 11 rximr11 32-bit base + 0x08ac rx individual mask register 12 rximr12 32-bit base + 0x08b0 rx individual mask register 13 rximr13 32-bit base + 0x08b4 rx individual mask register 14 rximr14 32-bit base + 0x08b8 rx individual mask register 15 rximr15 32-bit base + 0x08bc rx individual mask register 16 rximr16 32-bit base + 0x08c0 rx individual mask register 17 rximr17 32-bit base + 0x08c4 rx individual mask register 18 rximr18 32-bit base + 0x08c8 rx individual mask register 19 rximr19 32-bit base + 0x08cc rx individual mask register 20 rximr20 32-bit base + 0x08d0 rx individual mask register 21 rximr21 32-bit base + 0x08d4 rx individual mask register 22 rximr22 32-bit base + 0x08d8 rx individual mask register 23 rximr23 32-bit base + 0x08dc rx individual mask register 24 rximr24 32-bit base + 0x08e0 rx individual mask register 25 rximr25 32-bit base + 0x08e4 rx individual mask register 26 rximr26 32-bit base + 0x08e8 rx individual mask register 27 rximr27 32-bit base + 0x08ec rx individual mask register 28 rximr28 32-bit base + 0x08f0 rx individual mask register 29 rximr29 32-bit base + 0x08f4 rx individual mask register 30 rximr30 32-bit base + 0x08f8 rx individual mask register 31 rximr31 32-bit base + 0x08fc rx individual mask register 32 rximr32 32-bit base + 0x0900 rx individual mask register 33 rximr33 32-bit base + 0x0904 rx individual mask register 34 rximr34 32-bit base + 0x0908 table 432. detailed register map (continued) register description register name used size address RM0017 register map doc id 14629 rev 8 866/904 rx individual mask register 35 rximr35 32-bit base + 0x090c rx individual mask register 36 rximr36 32-bit base + 0x0910 rx individual mask register 37 rximr37 32-bit base + 0x0914 rx individual mask register 38 rximr38 32-bit base + 0x0918 rx individual mask register 39 rximr39 32-bit base + 0x091c rx individual mask register 40 rximr40 32-bit base + 0x0920 rx individual mask register 41 rximr41 32-bit base + 0x0924 rx individual mask register 42 rximr42 32-bit base + 0x0928 rx individual mask register 43 rximr43 32-bit base + 0x092c rx individual mask register 44 rximr44 32-bit base + 0x0930 rx individual mask register 45 rximr45 32-bit base + 0x0934 rx individual mask register 46 rximr46 32-bit base + 0x0938 rx individual mask register 47 rximr47 32-bit base + 0x093c rx individual mask register 48 rximr48 32-bit base + 0x0940 rx individual mask register 49 rximr49 32-bit base + 0x0944 rx individual mask register 50 rximr50 32-bit base + 0x0948 rx individual mask register 51 rximr51 32-bit base + 0x094c rx individual mask register 52 rximr52 32-bit base + 0x0950 rx individual mask register 53 rximr53 32-bit base + 0x0954 rx individual mask register 54 rximr54 32-bit base + 0x0958 rx individual mask register 55 rximr55 32-bit base + 0x095c rx individual mask register 56 rximr56 32-bit base + 0x0960 rx individual mask register 57 rximr57 32-bit base + 0x0964 rx individual mask register 58 rximr58 32-bit base + 0x0968 rx individual mask register 59 rximr59 32-bit base + 0x096c rx individual mask register 60 rximr60 32-bit base + 0x0970 rx individual mask register 61 rximr61 32-bit base + 0x0974 rx individual mask register 62 rximr62 32-bit base + 0x0978 rx individual mask register 63 rximr63 32-bit base + 0x097c reserved ? ? (base + 0x0980) ? (base + 0x3fff) flexcan_4 0xfffd_0000 module configuration mcr 32-bit base + 0x0000 control register ctrl 32-bit base + 0x0004 table 432. detailed register map (continued) register description register name used size address register map RM0017 867/904 doc id 14629 rev 8 free running timer timer 32-bit base + 0x0008 reserved ? ? base + (0x000c ? 0x000f) rx global mask register rxgmask 32-bit base + 0x0010 rx 14 mask register rx14mask 32-bit base + 0x0014 rx 15 mask register rx15mask 32-bit base + 0x0018 error counter register ecr 32-bit base + 0x001c error and status register esr 32-bit base + 0x0020 interrupt masks 2 register imask2 32-bit base + 0x0024 interrupt masks 1 register imask1 32-bit base + 0x0028 interrupt flags 2 register iflag2 32-bit base + 0x002c interrupt flags 1 register iflag1 32-bit base + 0x0030 reserved ? ? base + (0x0034 ? 0x007f) message buffer 0 mb0 128 bits per mb base + 0x0080 message buffer 1 mb1 128 bits per mb base + 0x0090 message buffer 2 mb2 128 bits per mb base + 0x00a0 message buffer 3 mb3 128 bits per mb base + 0x00b0 message buffer 4 mb4 128 bits per mb base + 0x00c0 message buffer 5 mb5 128 bits per mb base + 0x00d0 message buffer 6 mb6 128 bits per mb base + 0x00e0 message buffer 7 mb7 128 bits per mb base + 0x00f0 message buffer 8 mb8 128 bits per mb base + 0x0100 message buffer 9 mb9 128 bits per mb base + 0x0110 message buffer 10 mb10 128 bits per mb base + 0x0120 message buffer 11 mb11 128 bits per mb base + 0x0130 table 432. detailed register map (continued) register description register name used size address RM0017 register map doc id 14629 rev 8 868/904 message buffer 12 mb12 128 bits per mb base + 0x0140 message buffer 13 mb13 128 bits per mb base + 0x0150 message buffer 14 mb14 128 bits per mb base + 0x0160 message buffer 15 mb15 128 bits per mb base + 0x0170 message buffer 16 mb16 128 bits per mb base + 0x0180 message buffer 17 mb17 128 bits per mb base + 0x0190 message buffer 18 mb18 128 bits per mb base + 0x01a0 message buffer 19 mb19 128 bits per mb base + 0x01b0 message buffer 20 mb20 128 bits per mb base + 0x01c0 message buffer 21 mb21 128 bits per mb base + 0x01d0 message buffer 22 mb22 128 bits per mb base + 0x01e0 message buffer 23 mb23 128 bits per mb base + 0x01f0 message buffer 24 mb24 128 bits per mb base + 0x0200 message buffer 25 mb25 128 bits per mb base + 0x0210 message buffer 26 mb26 128 bits per mb base + 0x0220 message buffer 27 mb27 128 bits per mb base + 0x0230 message buffer 28 mb28 128 bits per mb base + 0x0240 message buffer 29 mb29 128 bits per mb base + 0x0250 message buffer 30 mb30 128 bits per mb base + 0x0260 message buffer 31 mb31 128 bits per mb base + 0x0270 table 432. detailed register map (continued) register description register name used size address register map RM0017 869/904 doc id 14629 rev 8 message buffer 32 mb32 128 bits per mb base + 0x0280 message buffer 33 mb33 128 bits per mb base + 0x0290 message buffer 34 mb34 128 bits per mb base + 0x02a0 message buffer 35 mb35 128 bits per mb base + 0x02b0 message buffer 36 mb36 128 bits per mb base + 0x02c0 message buffer 37 mb37 128 bits per mb base + 0x02d0 message buffer 38 mb38 128 bits per mb base + 0x02e0 message buffer 39 mb39 128 bits per mb base + 0x02f0 message buffer 40 mb40 128 bits per mb base + 0x0300 message buffer 41 mb41 128 bits per mb base + 0x0310 message buffer 42 mb42 128 bits per mb base + 0x0320 message buffer 43 mb43 128 bits per mb base + 0x0330 message buffer 44 mb44 128 bits per mb base + 0x0340 message buffer 45 mb45 128 bits per mb base + 0x0350 message buffer 46 mb46 128 bits per mb base + 0x0360 message buffer 47 mb47 128 bits per mb base + 0x0370 message buffer 48 mb48 128 bits per mb base + 0x0380 message buffer 49 mb49 128 bits per mb base + 0x0390 message buffer 50 mb50 128 bits per mb base + 0x03a0 message buffer 51 mb51 128 bits per mb base + 0x03b0 table 432. detailed register map (continued) register description register name used size address RM0017 register map doc id 14629 rev 8 870/904 message buffer 52 mb52 128 bits per mb base + 0x03c0 message buffer 53 mb53 128 bits per mb base + 0x03d0 message buffer 54 mb54 128 bits per mb base + 0x03e0 message buffer 55 mb55 128 bits per mb base + 0x03f0 message buffer 56 mb56 128 bits per mb base + 0x0400 message buffer 57 mb57 128 bits per mb base + 0x0410 message buffer 58 mb58 128 bits per mb base + 0x0420 message buffer 59 mb59 128 bits per mb base + 0x0430 message buffer 60 mb60 128 bits per mb base + 0x0440 message buffer 61 mb61 128 bits per mb base + 0x0450 message buffer 62 mb62 128 bits per mb base + 0x0460 message buffer 63 mb63 128 bits per mb base + 0x0470 reserved ? ? (base + 0x0480) ? (base + 0x087f) rx individual mask register 0 rximr0 32-bit base + 0x0880 rx individual mask register 1 rximr1 32-bit base + 0x0884 rx individual mask register 2 rximr2 32-bit base + 0x0888 rx individual mask register 3 rximr3 32-bit base + 0x088c rx individual mask register 4 rximr4 32-bit base + 0x0890 rx individual mask register 5 rximr5 32-bit base + 0x0894 rx individual mask register 6 rximr6 32-bit base + 0x0898 rx individual mask register 7 rximr7 32-bit base + 0x089c rx individual mask register 8 rximr8 32-bit base + 0x08a0 rx individual mask register 9 rximr9 32-bit base + 0x08a4 rx individual mask register 10 rximr10 32-bit base + 0x08a8 rx individual mask register 11 rximr11 32-bit base + 0x08ac rx individual mask register 12 rximr12 32-bit base + 0x08b0 table 432. detailed register map (continued) register description register name used size address register map RM0017 871/904 doc id 14629 rev 8 rx individual mask register 13 rximr13 32-bit base + 0x08b4 rx individual mask register 14 rximr14 32-bit base + 0x08b8 rx individual mask register 15 rximr15 32-bit base + 0x08bc rx individual mask register 16 rximr16 32-bit base + 0x08c0 rx individual mask register 17 rximr17 32-bit base + 0x08c4 rx individual mask register 18 rximr18 32-bit base + 0x08c8 rx individual mask register 19 rximr19 32-bit base + 0x08cc rx individual mask register 20 rximr20 32-bit base + 0x08d0 rx individual mask register 21 rximr21 32-bit base + 0x08d4 rx individual mask register 22 rximr22 32-bit base + 0x08d8 rx individual mask register 23 rximr23 32-bit base + 0x08dc rx individual mask register 24 rximr24 32-bit base + 0x08e0 rx individual mask register 25 rximr25 32-bit base + 0x08e4 rx individual mask register 26 rximr26 32-bit base + 0x08e8 rx individual mask register 27 rximr27 32-bit base + 0x08ec rx individual mask register 28 rximr28 32-bit base + 0x08f0 rx individual mask register 29 rximr29 32-bit base + 0x08f4 rx individual mask register 30 rximr30 32-bit base + 0x08f8 rx individual mask register 31 rximr31 32-bit base + 0x08fc rx individual mask register 32 rximr32 32-bit base + 0x0900 rx individual mask register 33 rximr33 32-bit base + 0x0904 rx individual mask register 34 rximr34 32-bit base + 0x0908 rx individual mask register 35 rximr35 32-bit base + 0x090c rx individual mask register 36 rximr36 32-bit base + 0x0910 rx individual mask register 37 rximr37 32-bit base + 0x0914 rx individual mask register 38 rximr38 32-bit base + 0x0918 rx individual mask register 39 rximr39 32-bit base + 0x091c rx individual mask register 40 rximr40 32-bit base + 0x0920 rx individual mask register 41 rximr41 32-bit base + 0x0924 rx individual mask register 42 rximr42 32-bit base + 0x0928 rx individual mask register 43 rximr43 32-bit base + 0x092c rx individual mask register 44 rximr44 32-bit base + 0x0930 rx individual mask register 45 rximr45 32-bit base + 0x0934 rx individual mask register 46 rximr46 32-bit base + 0x0938 table 432. detailed register map (continued) register description register name used size address RM0017 register map doc id 14629 rev 8 872/904 rx individual mask register 47 rximr47 32-bit base + 0x093c rx individual mask register 48 rximr48 32-bit base + 0x0940 rx individual mask register 49 rximr49 32-bit base + 0x0944 rx individual mask register 50 rximr50 32-bit base + 0x0948 rx individual mask register 51 rximr51 32-bit base + 0x094c rx individual mask register 52 rximr52 32-bit base + 0x0950 rx individual mask register 53 rximr53 32-bit base + 0x0954 rx individual mask register 54 rximr54 32-bit base + 0x0958 rx individual mask register 55 rximr55 32-bit base + 0x095c rx individual mask register 56 rximr56 32-bit base + 0x0960 rx individual mask register 57 rximr57 32-bit base + 0x0964 rx individual mask register 58 rximr58 32-bit base + 0x0968 rx individual mask register 59 rximr59 32-bit base + 0x096c rx individual mask register 60 rximr60 32-bit base + 0x0970 rx individual mask register 61 rximr61 32-bit base + 0x0974 rx individual mask register 62 rximr62 32-bit base + 0x0978 rx individual mask register 63 rximr63 32-bit base + 0x097c reserved ? ? (base + 0x0980) ? (base + 0x3fff) flexcan_5 0xfffd_4000 module configuration mcr 32-bit base + 0x0000 control register ctrl 32-bit base + 0x0004 free running timer timer 32-bit base + 0x0008 reserved ? ? base + (0x000c ? 0x000f) rx global mask register rxgmask 32-bit base + 0x0010 rx 14 mask register rx14mask 32-bit base + 0x0014 rx 15 mask register rx15mask 32-bit base + 0x0018 error counter register ecr 32-bit base + 0x001c error and status register esr 32-bit base + 0x0020 interrupt masks 2 register imask2 32-bit base + 0x0024 interrupt masks 1 register imask1 32-bit base + 0x0028 interrupt flags 2 register iflag2 32-bit base + 0x002c interrupt flags 1 register iflag1 32-bit base + 0x0030 table 432. detailed register map (continued) register description register name used size address register map RM0017 873/904 doc id 14629 rev 8 reserved ? ? base + (0x0034 ? 0x007f) message buffer 0 mb0 128 bits per mb base + 0x0080 message buffer 1 mb1 128 bits per mb base + 0x0090 message buffer 2 mb2 128 bits per mb base + 0x00a0 message buffer 3 mb3 128 bits per mb base + 0x00b0 message buffer 4 mb4 128 bits per mb base + 0x00c0 message buffer 5 mb5 128 bits per mb base + 0x00d0 message buffer 6 mb6 128 bits per mb base + 0x00e0 message buffer 7 mb7 128 bits per mb base + 0x00f0 message buffer 8 mb8 128 bits per mb base + 0x0100 message buffer 9 mb9 128 bits per mb base + 0x0110 message buffer 10 mb10 128 bits per mb base + 0x0120 message buffer 11 mb11 128 bits per mb base + 0x0130 message buffer 12 mb12 128 bits per mb base + 0x0140 message buffer 13 mb13 128 bits per mb base + 0x0150 message buffer 14 mb14 128 bits per mb base + 0x0160 message buffer 15 mb15 128 bits per mb base + 0x0170 message buffer 16 mb16 128 bits per mb base + 0x0180 message buffer 17 mb17 128 bits per mb base + 0x0190 message buffer 18 mb18 128 bits per mb base + 0x01a0 table 432. detailed register map (continued) register description register name used size address RM0017 register map doc id 14629 rev 8 874/904 message buffer 19 mb19 128 bits per mb base + 0x01b0 message buffer 20 mb20 128 bits per mb base + 0x01c0 message buffer 21 mb21 128 bits per mb base + 0x01d0 message buffer 22 mb22 128 bits per mb base + 0x01e0 message buffer 23 mb23 128 bits per mb base + 0x01f0 message buffer 24 mb24 128 bits per mb base + 0x0200 message buffer 25 mb25 128 bits per mb base + 0x0210 message buffer 26 mb26 128 bits per mb base + 0x0220 message buffer 27 mb27 128 bits per mb base + 0x0230 message buffer 28 mb28 128 bits per mb base + 0x0240 message buffer 29 mb29 128 bits per mb base + 0x0250 message buffer 30 mb30 128 bits per mb base + 0x0260 message buffer 31 mb31 128 bits per mb base + 0x0270 message buffer 32 mb32 128 bits per mb base + 0x0280 message buffer 33 mb33 128 bits per mb base + 0x0290 message buffer 34 mb34 128 bits per mb base + 0x02a0 message buffer 35 mb35 128 bits per mb base + 0x02b0 message buffer 36 mb36 128 bits per mb base + 0x02c0 message buffer 37 mb37 128 bits per mb base + 0x02d0 message buffer 38 mb38 128 bits per mb base + 0x02e0 table 432. detailed register map (continued) register description register name used size address register map RM0017 875/904 doc id 14629 rev 8 message buffer 39 mb39 128 bits per mb base + 0x02f0 message buffer 40 mb40 128 bits per mb base + 0x0300 message buffer 41 mb41 128 bits per mb base + 0x0310 message buffer 42 mb42 128 bits per mb base + 0x0320 message buffer 43 mb43 128 bits per mb base + 0x0330 message buffer 44 mb44 128 bits per mb base + 0x0340 message buffer 45 mb45 128 bits per mb base + 0x0350 message buffer 46 mb46 128 bits per mb base + 0x0360 message buffer 47 mb47 128 bits per mb base + 0x0370 message buffer 48 mb48 128 bits per mb base + 0x0380 message buffer 49 mb49 128 bits per mb base + 0x0390 message buffer 50 mb50 128 bits per mb base + 0x03a0 message buffer 51 mb51 128 bits per mb base + 0x03b0 message buffer 52 mb52 128 bits per mb base + 0x03c0 message buffer 53 mb53 128 bits per mb base + 0x03d0 message buffer 54 mb54 128 bits per mb base + 0x03e0 message buffer 55 mb55 128 bits per mb base + 0x03f0 message buffer 56 mb56 128 bits per mb base + 0x0400 message buffer 57 mb57 128 bits per mb base + 0x0410 message buffer 58 mb58 128 bits per mb base + 0x0420 table 432. detailed register map (continued) register description register name used size address RM0017 register map doc id 14629 rev 8 876/904 message buffer 59 mb59 128 bits per mb base + 0x0430 message buffer 60 mb60 128 bits per mb base + 0x0440 message buffer 61 mb61 128 bits per mb base + 0x0450 message buffer 62 mb62 128 bits per mb base + 0x0460 message buffer 63 mb63 128 bits per mb base + 0x0470 reserved ? ? (base + 0x0480) ? (base + 0x087f) rx individual mask register 0 rximr0 32-bit base + 0x0880 rx individual mask register 1 rximr1 32-bit base + 0x0884 rx individual mask register 2 rximr2 32-bit base + 0x0888 rx individual mask register 3 rximr3 32-bit base + 0x088c rx individual mask register 4 rximr4 32-bit base + 0x0890 rx individual mask register 5 rximr5 32-bit base + 0x0894 rx individual mask register 6 rximr6 32-bit base + 0x0898 rx individual mask register 7 rximr7 32-bit base + 0x089c rx individual mask register 8 rximr8 32-bit base + 0x08a0 rx individual mask register 9 rximr9 32-bit base + 0x08a4 rx individual mask register 10 rximr10 32-bit base + 0x08a8 rx individual mask register 11 rximr11 32-bit base + 0x08ac rx individual mask register 12 rximr12 32-bit base + 0x08b0 rx individual mask register 13 rximr13 32-bit base + 0x08b4 rx individual mask register 14 rximr14 32-bit base + 0x08b8 rx individual mask register 15 rximr15 32-bit base + 0x08bc rx individual mask register 16 rximr16 32-bit base + 0x08c0 rx individual mask register 17 rximr17 32-bit base + 0x08c4 rx individual mask register 18 rximr18 32-bit base + 0x08c8 rx individual mask register 19 rximr19 32-bit base + 0x08cc rx individual mask register 20 rximr20 32-bit base + 0x08d0 rx individual mask register 21 rximr21 32-bit base + 0x08d4 rx individual mask register 22 rximr22 32-bit base + 0x08d8 rx individual mask register 23 rximr23 32-bit base + 0x08dc table 432. detailed register map (continued) register description register name used size address register map RM0017 877/904 doc id 14629 rev 8 rx individual mask register 24 rximr24 32-bit base + 0x08e0 rx individual mask register 25 rximr25 32-bit base + 0x08e4 rx individual mask register 26 rximr26 32-bit base + 0x08e8 rx individual mask register 27 rximr27 32-bit base + 0x08ec rx individual mask register 28 rximr28 32-bit base + 0x08f0 rx individual mask register 29 rximr29 32-bit base + 0x08f4 rx individual mask register 30 rximr30 32-bit base + 0x08f8 rx individual mask register 31 rximr31 32-bit base + 0x08fc rx individual mask register 32 rximr32 32-bit base + 0x0900 rx individual mask register 33 rximr33 32-bit base + 0x0904 rx individual mask register 34 rximr34 32-bit base + 0x0908 rx individual mask register 35 rximr35 32-bit base + 0x090c rx individual mask register 36 rximr36 32-bit base + 0x0910 rx individual mask register 37 rximr37 32-bit base + 0x0914 rx individual mask register 38 rximr38 32-bit base + 0x0918 rx individual mask register 39 rximr39 32-bit base + 0x091c rx individual mask register 40 rximr40 32-bit base + 0x0920 rx individual mask register 41 rximr41 32-bit base + 0x0924 rx individual mask register 42 rximr42 32-bit base + 0x0928 rx individual mask register 43 rximr43 32-bit base + 0x092c rx individual mask register 44 rximr44 32-bit base + 0x0930 rx individual mask register 45 rximr45 32-bit base + 0x0934 rx individual mask register 46 rximr46 32-bit base + 0x0938 rx individual mask register 47 rximr47 32-bit base + 0x093c rx individual mask register 48 rximr48 32-bit base + 0x0940 rx individual mask register 49 rximr49 32-bit base + 0x0944 rx individual mask register 50 rximr50 32-bit base + 0x0948 rx individual mask register 51 rximr51 32-bit base + 0x094c rx individual mask register 52 rximr52 32-bit base + 0x0950 rx individual mask register 53 rximr53 32-bit base + 0x0954 rx individual mask register 54 rximr54 32-bit base + 0x0958 rx individual mask register 55 rximr55 32-bit base + 0x095c rx individual mask register 56 rximr56 32-bit base + 0x0960 rx individual mask register 57 rximr57 32-bit base + 0x0964 table 432. detailed register map (continued) register description register name used size address RM0017 register map doc id 14629 rev 8 878/904 rx individual mask register 58 rximr58 32-bit base + 0x0968 rx individual mask register 59 rximr59 32-bit base + 0x096c rx individual mask register 60 rximr60 32-bit base + 0x0970 rx individual mask register 61 rximr61 32-bit base + 0x0974 rx individual mask register 62 rximr62 32-bit base + 0x0978 rx individual mask register 63 rximr63 32-bit base + 0x097c reserved ? ? (base + 0x0980) ? (base + 0x3fff) table 432. detailed register map (continued) register description register name used size address revision history RM0017 879/904 doc id 14629 rev 8 revision history table 433. document revision history date revision changes 01-apr-2008 1 initial release 19-feb-2009 2 cover page: done the same progressive numbering of figure and table throgh whole document: - harmonized the name of the 4 different clock source with the name listened here: - fxosc or fast external crystal oscillator 4-16 mhz - firc or fast internal rc oscillator 16 mhz - sirc or slow internal rc oscillator 128 khz - sxosc or slow external crystal oscillator 32 khz - fmpll or frequency modulated phase locked loop - harmonized the cross reference to sections. - replaced every ?miscellaneous control module? or ?mcm? occurrences rispectively with ?error correction stat us module? or ?(ecsm)?. chapter 1 overview - section 1.1 features : replaced with a new one. - ta b l e 2 : added rows, extended the sram memory to 48 kb. - ta b l e 4 : removed the cell of ?ap?. chapter 2 signal description - section 2.2 package pinouts : updated all pin map. - section 2.3 pad configuration during reset phases and section 2.6 system pins : updated because after power-up phase the majori ty of pins is in tristate end not inpu waek pull-up. - ta b l e 6 : - pc[1] type changed from ?f? to ?m?. - footnote 9: included also ph[9:10] among the exepted pins. - section 2.5 pad types : changed the note . chapter 3 clock description : - removed the reference to normal end test access, all accesses are seen as supervisor. - ta b l e 9 : replaced pit_rit with pit. - ta b l e 1 0 : - replaced ?enable? heading rows with ?me_gs.s_xosc?. - replaced ?byp? heading rows with ?osc_ctl.oscbyop?. - replaced ?hiz? with ?high z?. - ta b l e 1 2 : - replaced ?enable? heading rows with ?osc_ctl.s_osc?. - replaced ?byp? heading rows with ?osc_ctl.oscbyop?. - replaced ?hiz? with ?high z?. - ta b l e 2 3 : removed flci_a field. - figure 10 : removed mode and div4 path. - section 3.3, ?clock gene ration module (mc_cgm)? : replaced with a new section. chapter 5 mode entry module (mc_me) : replaced with a new chapter. RM0017 revision history doc id 14629 rev 8 880/904 19-feb-2009 2 (continued) chapter 6 boot assist module (bam) : - aligned naming of linflex module. - section bam resources : removed any references to stm, cmu and fmpll. chapter 7 reset genera tion module (mc_rgm) : replaced with a new chapter. chapter 8 system integration unit lite (siul) : - repleced the number of i/o pins from ?121? to ?123? for 144-pin and 208-pin packages. - repleced the number of i/o pins from ?77? to ?79? for 100-pin packages. - ta b l e 7 7 : modified the reset value for bit 28:31 to ?0?. - ta b l e 8 3 : changed the size of the field ?src? form 2 to 1 bit. - ta b l e 8 6 : changed the definition of pcrx.src. chapter 9 power control unit (mc_pcu) : replaced with a new chapter. chapter 11 e200z0h core : replaced all e200z0 e200z1 occurrences with e200z0h. chapter 15 error correction status module (ecsm) ?: - removed mrsr register and descibed as reserved. - removed section ?13.4.3 high priority enables?. ta bl e 1 2 4 : removed mrsr register and descibed as reserved. section 16.6 external signal description : - updated the period since all 4 jtag pin are shared with gpio. - table 145 : updated dc field description. - section 16.8.4 jtagc instructions : removed cut.1 information. chapter 17 nexus develo pment interface (ndi) : - removed references to jcomp. - removed section ?nexus reset control?. chapter 18 static ram (sram) : - updated the size of the ram from 38 to 42kb. - section 18.6 initialization and application information : reformatted. chapter 19 flash memory : - table 166 updated. - section 19.4.1 introduction : replaced ?spp? with ?rpp?. - removed figure?flash memo ry controller block diagram?. - ta b l e 2 3 0 : replaced the reset value with which ones defined in the table footnote and removed them. chapter 20 deserial serial peripheral interface (dspi) : - removed all the note that refer to rx mask. - removed dspi x _ctar6 and dspi x _ctar7 register. - added following tables: ta b l e 2 4 2 , table 243 , ta b l e 2 4 4 , table 245 , ta b l e 2 4 6 , ta bl e 2 4 7 , table 248 , ta b l e 2 4 9 , table 250 , ta b l e 2 5 1 , table 252 , ta b l e 2 5 3 , ta bl e 2 5 4 . section20.4features : replaced ?eight clock and transfer attribute registers? with ?six clock and transfer attribute registers?. table 433. document revision history (continued) date revision changes revision history RM0017 881/904 doc id 14629 rev 8 19-feb-2009 2 (continued) section dspi module configuration register (dspix_mcr) : removed clr_txf and clr_rxf fields from dspix_mcr register. chapter 21 lin controller (linflex) : replaced with a new chapter. chapter 22 flexcan : - removed ?[ref.1]?. - section 22.1.2 flexcan module features . - added bullet ?hardware cancellation on tx message buffers.? . - removed note. - table 326 : replaced the footnote with new one. - section 22.3.3 rx fifo structure : ta b l e 2 7 4 fixed the offset value. - updated section module configuration register (mcr) (maxmb note). - updated section error and status register (esr) (bit numbers in first paragraph). - fixed information about the number of fram es accumulated in the fifo to generate a warning interrupt, which is 5. (affected sections: section interrupt flags 1 register (iflag1) and section 22.4.8 rx fifo ). - section 22.4.2 local priority transmission : added. chapter 24 inter-integrated circuit bus controller module (i2c) : - replaced ?i2c_dma? ?i2c? through whole chapter. - section 24.1.1 overview : replaced the capacitance value from ?400pf? to ?50pf?. - table 329 : removed mode column. chapter 25 configurable enhanced modular io subsystem (emios) : replaced with a new chapter. chapter 26 analog-to-digital converter (adc) : replaced with a new chapter. chapter 27 cross triggering unit (ctu) - table 381 : corrected emios channel assignment on ctu inputs. chapter 29 system status and configuration module (sscm) : - section system memory configuration register (memconfig) : updated register definition. - removed section ?initialization/application information?. table 433. document revision history (continued) date revision changes RM0017 revision history doc id 14629 rev 8 882/904 19-feb-2009 2 (continued) chapter 30 wakeup unit (wkpu) : - related bit12 and bit13 to the wakeup line respectively 19 and 18 of the following register: wisr, irer, wrer, wi reer, wifeer, wifer, wipuer. - wkup line 0: previously = rtc/api; now = api. - 'old'wkup line 1 -> now wkup line 19. - 'new' wkup line 1 -> rtc. - replaced ?nmi[0]? whti [nmi]. - moved the note of ?interrupt vector 2?, this note is valid only for pf[13], pg[3] and pg[5]. - figure 421 : replaced ?0-18? instead ?0-19?. - figure 433 : updated in according to the previous change. - section 30.2 features : - updated the ?external wakeup/interrupt suppor t? list to explain that system interrupt vectors are 3. - updated the ?on-chip wakeup support? lis t to explain that wakeup spurces are 2. - section 30.4.1 memory map : table 406 removed redundant rows. chapter 31 periodic interrupt timer (pit) : - figure 434 : replaced ?timer 3? with ?timer 5?. chapter 33 real time clock / autonomous periodic interrupt (rtc/api) : - added ?/autonomous periodic interrupt? in the title. - figure 444 : updated to explain that ?rtc rollover wakeup? and ?rtc cnt_or_rlovr? are not connected on spc560bx and spc560cx. - figure 33.4 : removed section ?test mode?. - removed section ?external signal description?. chapter 34 voltage regulators and power supplies : aligned the electrical value with datasheet 08-may-2009 3 improved the formatting through whole document. chapter 3 clock description : fixed the issue about the bit numbering of all registers. chapter 10 interrupt controller (intc) : - figure 99 : updated. chapter 25 configurable enhanced modular io subsystem (emios) : - figure 307 : updated. chapter 26 analog-to-digital converter (adc) : updated the following tables: figure 365 , figure 368 , figure 376 , figure 377 , figure 378 , figure 379 , figure 380 , figure 381 , figure 384 , figure 385 , figure 388 , figure 391 , figure 392 , figure 393 . chapter 29 system status and configuration module (sscm) : updated the following tables: figure 419 , figure 420 , ta b l e 4 0 4 . table 433. document revision history (continued) date revision changes revision history RM0017 883/904 doc id 14629 rev 8 08-may-2009 3 (continued) chapter 30 wakeup unit (wkpu) : updated the following tables: figure 425 , table 409 , figure 426 , ta bl e 4 1 0 , figure 427 . chapter 33 real time clock / autonomous periodic interrupt (rtc/api) : updated the following tables: ta bl e 4 3 5 , figure 449 , figure 450 , ta bl e 4 3 7 . chapter 34 voltage regulators and power supplies : updated figure 451 . 13-jan-2010 4 chapter 1 overview minor editorial and formatting changes updated spc560bx and spc560cx series block diagram section 1.1.3 chip-level features : changed emios-lite to emios section 1.3 developer support : added footnote defining autosar memory map: ? changed periodic interrupt timer (pit/rti) to periodic interrupt timer (pit) ? changed ctu-lite to ctu ? changed sram size from 32 kb to 48 kb chapter 2 signal description minor editorial and formatting changes section 2.2 package pinouts : inverted the order of figure 2 and figure 3 208 mapbgalbga208 configur ation: changed description for ball h1 from nc to vss_hv section 2.3 pad configuration during reset phases : added bam function abs[0] to pa [ 8 ] voltage supply pin descriptions: added ball h1 to vss_hv pins functional port pin descriptions: ? added a footnote regarding ?i/o direction? column ? replaced gpio[20] with gpi[20] ? changed gpi[21] to gpio[21] ? changed the ?reset config? of pb[7] and pb[8] to tristate ? changed ?pad type? from s to m in 27 pads ? changed pad type from s to m on port pin pe[7] chapter 3 clock description editorial and formatting changes section 3.5, ?memory map and register definition? , section 3.3.3 register description added ?location? column to mc_cgm register description; added clock domain information to clock source selection re gister descriptions section 3.5 slow internal rc oscillator (sirc) digital interface : replaced all lprc occurrences with sirc table 433. document revision history (continued) date revision changes RM0017 revision history doc id 14629 rev 8 884/904 13-jan-2010 4 (continued) section normal mode : replaced ?cr? with ?cr. ndiv? and ?ldf? with ?ndiv? fast external crystal oscillator control register (fxosc_ctl) field descriptions: updated description of eocv[7:0] fmpll block diagram: added footnote to div2 fmpll memory map: updated access types cr field descriptions: updated description of field en_pll_sw progressive clock switching on pll_select rising edge: updated column header titles added figure ?fmpll output clock division flow during progressive switching? chapter 5 mode entry module (mc_me) section 5.3 memory map and register definition : minor editorial and formatting changes; reset mode configuration register (m e_reset_mc): corrected title of bitmap, section 5.4.1 mode transition request , section reset mode , section standby0 mode : added ?location? column to mc_me register description; added note for s_mtrans polling; cleaned up mc_me mode diagram; added details to reset mode description; added details of bo oting from backup ram on standby0 exit chapter 6 boot assist module (bam) minor editorial and formatting changes to improve readability updated oscillator naming removed all references to ?autobaud? and to abd field of sscm_status register (autobaud feature not supported by device) section 6.3.2 reset configuration half word source (rchw) : changed offset from 0x02 to 0x00 section 6.3.3 single chip boot mode : added a footnote bam memory organization: added column header ?parameter? updated fields of sscm status register used by bam section bam resources : updated list of mcu resources section download and execute the new code : removed optional first step no. 0 (step concerned send/receive message for autobaud rate selection) updated serial boot mode ? baud rates updated system clock frequency related to external clock frequency reset configuration half word (rchw): changed reset value for all fields: was 0; is 1 updated section download 64-bit password and password check chapter 7 reset genera tion module (mc_rgm) added ?location? column as navigational aid to mc_rgm register description chapter 8 system integration unit lite (siul) editorial and formatting changes to improve readability updated siul signal properties updated siul memory map updated register descriptions section 8.6.2 general purpose i nput and output pads (gpio) : updated number of interrupt vectors and number of external interrupts table 433. document revision history (continued) date revision changes revision history RM0017 885/904 doc id 14629 rev 8 13-jan-2010 4 (continued) chapter 9 power control unit (mc_pcu) added ?location? column as navigational aid to mc_pcu register description chapter 10 interrupt controller (intc) : editorial and formatting changes chapter 11 e200z0h core minor editorial and formatting changes updated e200z0h block diagram section e200z0h system bus features : added footnotes chapter 12 peripheral bridge (pbridge) editorial and formatting changes, including chapter title change replaced ?aips? with ?peripheral bridge?, or ?pbridge? where appropriate, throughout chapter peripheral bridge interface: updated pbridge1 peripheral names updated section 12.1.4 modes of operation chapter 13 crossbar switch (xbar) minor editorial and formatting changes updated xbar block diagram chapter 14 memory protection unit (mpu) minor editorial and formatting changes updated mpu block diagram updated section 14.2.2 register description to include adding bit numbers to field names and changing field bit numbers format to lsb=0 where needed mpu memory map: removed mpu_ear3 and mpu_edr3 mpu error address register, slave port n (mpu_earn): removed mpu_ear3 content mpu error detail register, slave port n (mpu_edrn): removed mpu_edr3 content mpu region descriptor, wo rd 0 register (mpu_rgdn. word0): replaced asterisks with ?0? as reset value for bits 27:31 mpu_rgdn.word0 field descriptions: re placed srtaddr[31:0] with srtaddr[26:0] mpu_rgdn.word1 field descriptions: replaced endaddr[31:0] with endaddr[26:0] chapter 15 error correction status module (ecsm) editorial and formatting changes; repaired cross-reference links replaced aips with ?peripheral bridge? or ?pbridge? section 15.4.2 register description : applied lsb=0 to field internal bit numbers ecsm 32-bit memory map: added ecsm base address section processor core type (pct) register : added reset values to bitmap section revision (rev) register : added reset values to bitmap section ips module configuration (imc) register : added reset values to bitmap table 433. document revision history (continued) date revision changes RM0017 revision history doc id 14629 rev 8 886/904 13-jan-2010 4 (continued) section miscellaneous user-defined control register (mudcr) ? updated bit numbers and field descriptions ? updated text following field description table section ecc configuration register (ecr) : removed paragraph about reporting of single-bit memo ry corrections updated ecc configuration (ecr) field descriptions section ecc error generation register (eegr) : removed paragraph about enabling of error generation modes section ecc error generation register (eegr) : replaced ?for the ecc configuration register definition? with ?for the ecc error generation register definition? in sentence above bitmap updated ecc error generation (eegr) field descriptions chapter 16 ieee 1149.1 test acce ss port controller (jtagc) editorial and formatting changes; repaired cross-references section 16.1 introduction : removed paragra ph about i eee 1149.7 e200z0 once register addressing: replac ed ?shared nexus control register (snc)? with ?reserved? (snc register not implemented on this device) chapter 17 nexus develo pment interface (ndi) editorial and formatting changes ndi implementation block diagram: replaced ppc with cpu nexus debug interface registers: ? added ?location? column as navigational aid ? removed client select control (csc) register (csc register not implemented on this device) ? updated register names ? removed sentence referencing device mpc5516 from footnote 1 nexus device id (did) register bitmap: changed reset value for field mic?was 0xe, is 0x20 pcr field descriptions: updat ed description of mcko_div[2:0] updated section 17.7.3 programmable mcko frequency section 16.7.4, ?nexus messaging? : removed sentence referencing client select control register section 16.7.6.1, ?evti generated break request? : removed sentence referencing shared nexus control (snc) register (snc register not implemented on this device) chapter 18 static ram (sram) editorial and formatting changes, including modification of chapter title section 18.3 register memory map : replaced ?32 kb? with ?48 kb? in first sentence chapter 19 flash memory editorial and formatting changes section 19.1 introduction : replaced 544 kbyte with 512 kbyte flash memory architecture: replac ed ?eee? with ? eeprom emulation? section 19.2 code flash : changed title and content to replace ?program flash? with ?code flash? table 433. document revision history (continued) date revision changes revision history RM0017 887/904 doc id 14629 rev 8 13-jan-2010 4 (continued) updated section 19.2.1 introduction section 19.2.2 main features : removed bullet ?usable as main code memory? updated section 19.2.3 block diagram updated section flash module sectorization updated section 19.2.6 module configuration register (mcr) updated section 19.2.8 high address space block locking register (hbl) updated section 19.2.11 high address space block select register (hbs) adr field descriptions: removed the phrase ?if the device is configured to show this feature? in the ad22-3 description section 19.2.13 bus interface unit 0 register (biu0) : ? removed sentence ?the availability of this register is device dependent?. ? updated biu0 field descriptions section 19.2.14 bus interface unit 1 register (biu1) : ? removed sentence ?the availability of this register is device dependent?. ? updated biu1 field descriptions section non-volatile bus interface unit 2 register (nvbiu2) : ? removed sentence ?the availability of this register is device dependent?. ? updated biu2 field descriptions section 19.2.16 user test 0 register (ut0) : modified first sentence non-volatile private censorship password 0 register (nvpwd0): changed delivery value 0xxxxxxxxx to 0xffff_ffff non-volatile private censorship password 1 register (nvpwd1): changed delivery value 0xxxxxxxxx to 0xffff_ffff nvsci0 field descriptions: replaced ?or nvsci1 = nvsci0? with ?or nvsci1 != nvsci0? in fields sc and cw nvsci1 field descriptions: ? replaced ?sc32-16: serial censorship control word 32-16 (read/write)? with ?sc[31:16]: serial censorship control word 31-16 (read/write)? ? replaced ?cw32-16: censorship control word 32-16 (read/write)? with ?cw[31:16]: censorship control word 31-16 (read/write)? ? replaced ?or nvsci1 = nvsc i0? with ?or nvsci1 != n vsci0? in fields sc and cw section 19.2.28 non-volatile user options register (nvusro) : ? removed sentence ?the availability of this register is device dependent?. ? updated ta b l e 1 9 8 updated ta b l e 1 9 9 section 19.3.14 user test 0 register (ut0) : modified first sentence section 19.4.1 introduction : replaced aips-lite with pbridge pfcr0 field descriptions: modified field descriptions for bk0_apc, bk0_wwsc and bk0_rwsc pfcr1 field descriptions: modified field descriptions for bk1_apc, bk1_wwsc and bk1_rwsc section 19.5.13 timing diagrams : reformatted and rescaled timing diagrams to improve readability and alignment of content table 433. document revision history (continued) date revision changes RM0017 revision history doc id 14629 rev 8 888/904 13-jan-2010 4 (continued) chapter 20 deserial serial peripheral interface (dspi) editorial and formatting changes removed all references to dsi (deserial serial interface) and csi (combined serial interface) (device does not implement dsi and csi) removed all references to dma (dspi does not support dma in this device) dspi module configuration register (dspix_ mcr): replaced the reset value of mdis bitfield with ?1?. made same modification on dspix_mcr field descriptions. section20.3overview : replaced ?dspi 0, dspi 1 and d spi 2? with ?dspi 0 ? dspi 5? section20.4features : removed bullet ?supports all functional modes from qspi subblock of qsmcm (mpc500 family)? section 20.5 modes of operation : updated to add external stop mode section 20.6.2 signal names and descriptions : formatted all cs signals as ?csn_x? section 20.7 memory map and register description : removed all dma requests content section dspi clock and transfer attrib utes registers 0?5 (dspix_ctarn) : changed number of clock and transfer attr ibute registers from eight to six section dspi status register (dspix_sr) : modified first paragraph dspi detailed memory map: added ?location? column as navigational aid baud rate computation example: changed f sys from 100 mhz to 64 mhz and updated baud rate accordingly section 20.8 functional description : removed all dma requests content and edma controller content section 20.8.1 modes of operation : updated to add external stop mode section 20.9.1 how to change queues : modified list of events: was 1?11, is 1?7 updated section 20.9.3 delay settings chapter 21 lin controller (linflex) editorial and formatting changes updated section 21.2.1 lin mode features added names for example 15 and example 16 replaced linflex memory map section 21.7.2 register description ? aligned hexidecimal reset values to reset values shown in bitmaps where necessary ? aligned bit numbering in register field description tables to numbering in register bitmaps where necessary lin control register 1 (lincr1): ? changed reset value from 0x0082_0000 to 0x0000_0082 ? changed access from w1c to r/w for fields ccd, cfd, lase, awum, mbl[0:3], bf, sftm, lbkm, mme, sbdt, rblm, sleep and init lin interrupt enable register (linier): ? updated lsie field description ? changed access from w1c to r/w for fiel ds szie, ocie, beie, ceie, heie, feie, boie, lsie, wuie, dbfie, dbeie, drie, dtie and hrie section lin status register (linsr) : updated lins field description; changed access from w1c to read-only for field rps table 433. document revision history (continued) date revision changes revision history RM0017 889/904 doc id 14629 rev 8 13-jan-2010 4 (continued) section lin error status register (linesr) : updated szf field description uart mode control register (uartcr): ch anged access from w1c to r/w for fields rxen, txen, op, pce, wl and uart uartsr field descriptions: added footnote 1 lin timeout control status register (lintc sr): changed access from w1c to r/w for fields ltom, iot and toce lin output compare register (linocr): ch anged access from w1c to r/w for ocx[0:7] section lin timeout control status register (lintcsr) : updated hto field description lin fractional baud rate register (linfbrr): changed access from w1c to r/w for div_f[0:3] lin integer baud rate register (linibrr): changed access from w1c to r/w for div_m[0:12] lin checksum field register (lincfr): cha nged access from w1c to r/w for cf[0:7] lin control register 2 (lincr2): ? changed access from w1c to r/w for fields iobe and iope ? changed access from w1c to write-only for fields wurq, ddrq, dtrq, abrq and htrq section buffer identifier register (bidr) : updated ccs field description; changed access from w1c to r/w for fields dir and ccs buffer data register lsb (bdrl): changed access from w1c to r/w for datax[0:7] section identifier filter enable register (ifer) : updated description of fact[0:7]; added ifer[fact] configuration table section identifier filter match index (ifmi) : replaced ifmi[0:3] with ifmi[0:4] section identifier filter mode register (ifmr) : replaced ifm[0:3] with ifm[0:7]; added ifmr[ifm] configuration table; changed regist er access from user read-only to user read/write; changed access from read-only to r/w for ifm[0:7] section identifier filter co ntrol register (ifcr2n) : amended address offsets; changed access from w1c to r/w for fields dir and ccs section identifier filter co ntrol register (ifcr2n + 1) : amended address offsets; changed access from w1c to r/w for fields dir and ccs register map and reset values: ? updated bits of ifmi and ifmr ? amended address offsets for ifcr2n and for ifcr2n+1 added section clock gating to section 21.8.1 uart mode section 21.8.2 lin mode : added footnote regarding slave mode updated section data reception (transceiver as subscriber) updated section data discard updated section data transmission (transceiver as publisher) updated section data reception (transceiver as subscriber) updated section data discard filter configuration?re gister organization: replaced id5:0 with id[0:5] added section clock gating updated section 21.8.3 8-bit timeout counter header and response timeout: updated arrows for oc header , oc response and oc frame table 433. document revision history (continued) date revision changes RM0017 revision history doc id 14629 rev 8 890/904 13-jan-2010 4 (continued) chapter 22 flexcan editorial and formatting changes, including removing all references to consulting a device user guide removed any reference to the flexcan wake-up interrupt module memory map: added ?location? column as navigational aid updated section module configuration register (mcr) updated section control register (ctrl) added text in section rx global mask (rxgmask) , section rx 14 mask (rx14mask) and section rx 15 mask (rx15mask) referring to section 22.4.8 rx fifo section message buffer lock mechanism : added a note error and status register (esr) field descr iption: updated titles of bits tx_wrn and rx_wrn can standard compliant bit time segment settings: specified that it refers to the official can specification chapter 23 can sampler formatting and editorial changes updated oscillator naming (?16 mhz fast internal rc oscillator?) updated section 23.3 register description section 23.4 functional description : removed section ?selecting the rx port? (information already exists in register field description in table 327 ) section 23.4.2 baud rate generation : replaced brp bits 5:1 with brp[4:0] can sampler register map: updated field descriptions chapter 24 inter-integrated circuit bus controller module (i2c) formatting and editorial changes throughout , including harmonizing register names module memory map: added ?location? column as navigational aid ibsr field descriptions: removed comment ?check w/design if this is the case (only tcf)? from description of field ibif interrupt description : removed comment ?to be checked? from byte transfer condition chapter 25 configurable enhanced modular io subsystem (emios) organizational, editorial and formatting changes, including changing ?$? to ?0x? throughout section 25.1.2 features of the emios module : removed ?identical? from first bullet in list modified section 25.1.1 overview of the emios module removed ?identical? from first bullet in features list channel configuration: ? modified emios block numbering?was emios_a and emios_b, is emios_0 and emios_1 ? corrected position of horizontal arrow between counter bus_b and ch1 in emios_0 ? added gpio to diagram key updated section channel mode selection section 25.3 memory map and register description : harmonized register naming and added location columns to memory map tables table 433. document revision history (continued) date revision changes revision history RM0017 891/904 doc id 14629 rev 8 13-jan-2010 4 (continued) emios module configuration register (emi osmcr): changed reset value of mdis to ?0? emiosmcr field descriptions: corrected table title emiosoudis register field description s: replaced ou31:ou0 with ou27:ou0 updated section emios uc contro l (emiosc[n]) register uc bsl bits: added ?channels 24 to 27: counter bus[e]? to selected bus for field value ?01? emioss[n] register field descriptions: updated flag field description section 25.4 functional description : changed the number of channel types; was three, is five updated section coherent accesses unified channel block diagram: ? changed ips_wda to ips_wdata[0:31] ? changed uc_rd_d to uc_rd_data[0:31] ? changed ips_ad to ips_addr[27:29] chapter 26 analog-to-digital converter (adc) formatting changes section 26.1.1 device-specific features : ? replaced ma[0:2] with ma[2:0] ? removed 1.2 v from presampling options updated adc implementation diagram updated section 26.2 introduction section normal conversion : minor editorial change section start of normal conversion : minor editorial change updated second paragraph in section 26.3.2 analog clock generator and conversion timings updated section 26.3.3 adc sampling and conversion timing updated section presampling channel enable signals updated presampling voltage selection based on prevalx fields updated section 26.3.7 interrupts main configuration register (mcr) field descriptions: updated description for field owren main status register (msr) field descrip tions: updated values for adcstatus[0:2] (and removed stand-alone description table for this field) watchdog threshold interrupt status regi ster (wtisr) field descriptions: changed ?corresponds to the interrupt generated ? to ?corresponds to the status flag generated? in both bit descriptions presampling control register (pscr) field descriptions: updated descriptions for preval fields section 26.4.6 conversion timing registers ctr[0..2] : restored offshift field channel data register (cdr[0..95]) field descriptions: ? updated description for field overw ? added value ?11? to field result[0:1] table 433. document revision history (continued) date revision changes RM0017 revision history doc id 14629 rev 8 892/904 13-jan-2010 4 (continued) chapter 27 cross triggering unit (ctu) minor editorial and formatting changes ctu register map: added ?location? column and base address trigger source: corrected emios channel assignment on ctu inputs amended end of section 27.4.1 event configuration register (ctu_evtcfgrx) (x = 0...63) chapter 28 safety editorial and formatting changes section overview : replaced aips with pbridge section 28.2 software watchdog timer (swt) : replaced ?software? by ?system? replaced ?system watchdog? with ?sof tware watchdog? throughout chapter swt memory map: added ?location? column as navigational aid chapter 29 system status and configuration module (sscm) formatting and editorial changes section 29.2.2 register description : updated introduction and applied lsb=0 numbering to field bit numbers where needed module memory map: added ?location? column as navigational aid error configuration (error) field descripti ons: replaced ?aips? with ?pbridge? in rae field description system memory configuration register (me mconfig) field descriptions: modified descriptions of fields prsz and pvlb to replace ?program flash? and ?instruction flash? with ?code flash? chapter 30 wakeup unit (wkpu) editorial and formatting changes updated section30.1overview updated wakeup unit block diagram wkpu memory map: added ?location? column as navigational aid interrupt vector 1: updated pb[3] interrupt vector 2: updated pg[3] and pg[5] wakeup/interrupt status flag register (wisr): updated footnote updated wisr field descriptions interrupt request enable regi ster (irer): updated footnote wakeup request enable register (wrer): updated footnote wakeup/interrupt rising-edge event enable register (wireer): updated footnote wakeup/interrupt falling-edge event enable register (wifeer): updated footnote wakeup/interrupt filter enable re gister (wifer): updated footnote wakeup/interrupt pullup enable register (wipuer): updated footnote section 30.5.3 external wakeups/interrupts : replaced ?supports up to two interrupt vectors? with ?supports up to three interrupt vectors? table 433. document revision history (continued) date revision changes revision history RM0017 893/904 doc id 14629 rev 8 13-jan-2010 4 (continued) chapter 31 periodic interrupt timer (pit) editorial and formatting changes replaced pit_rti with pit throughout document tables pit memory map and timer channel n: added ?location? column as navigational aid section 31.5.1 example configuration : removed rti lines from code chapter 32 system timer module (stm) : no content changes chapter 33 real time clock / autonomous periodic interrupt (rtc/api) editorial and formatting changes, including updating and harmonizing oscillator names section 33.5 register descriptions : added register map; added key to register fields chapter 34 voltage regulators and power supplies formatting and editing changes updated figure updated section 34.1.1 high power regulator (hpreg) section 34.3 power domain organization : modified number of power domains; was two, is three appendix a: register under protection : no content changes appendix b: register map minor editorial and formatting changes module base addresses: ? changed periodic interrupt timer (pit/rti) to periodic interrupt timer (pit) ? changed ctu-lite to ctu detailed register map: ? changed register name pit_rti control to pit_control ? changed periodic interrupt timer (pit/rti) to periodic interrupt timer (pit) ? changed ctu-lite to ctu ? updated description of rser ? replaced ?program flash a configur ation? with ?code flash a configuration? ? replaced registers ifer, ifmi, ifmr, ifcr2n and ifcr2n+1 with ?reserved? for linflex modules 1, 2 and 3 table 433. document revision history (continued) date revision changes RM0017 revision history doc id 14629 rev 8 894/904 31-mar-2010 5 (continued) internal release. chapter 1 overview ?spc560bx and spc560cx series block diagram?figure: ? added ?interrupt request with wake-up functio nality? as an input to the wkpu block. chapter 2 signal description ?functional port pin description? table: ? improved the footnote regarding jtagc pins in order to explain when the device get incompliance with ieee 1149.1-2001. ? added a footnote concerning the family compatibility. ? footnote 11: replaced ?spc560b44l3 and spc560b44l? with ?spc560b40l3 and spc560b40l5?. chapter 3 clock description ?spc560bx and spc560cx system clock generation? figure: ? changed the dividers from 1 to 15 to 1 to 16 of the system clock selectors. ?progressive clock switching? section: ? revised. ? added ?progressive clock switching scheme? figure. ? update definition of en_pll_sw bit filed on control register. ?slow external crystal oscillator (sxosc) digital interface? section: ? interrupt functionalities are not available on sxosc. chapter 6 boot assist module (bam) ?hardware configuration to select boot mode? table: ? renamed the flag "standby-ram bo ot flag" to "boot_from_bkp_ram". ?download 64-bit password and password check? section: ? added note about password management. ?boot from flexcan? section: ? added note about the distir b provided by can traffic. chapter 10 interrupt controller (intc) replaced intc_psr121 with ?intc_psr147 updated ?intc priority select registers? and ?intc priority select register address offsets? table in according to ?interrupt vector table? table chapter 16 ieee 1149.1 test acce ss port controller (jtagc) ?external signal description? section: ? emphasized when the device ge t incompliance wit h ieee 1149.1-2001. chapter 17 nexus develo pment interface (ndi) ?ownership trace? section: ? added it. chapter 19 flash memory ? updated delivery values of nvpwd0 and nvpwd1 for code flash. ? revised the ?margin read? section for both flash. ? replaced ?margin mode? with ?margin read?. table 433. document revision history (continued) date revision changes revision history RM0017 895/904 doc id 14629 rev 8 31-mar-2010 5 (continued) chapter 20 deserial serial peripheral interface (dspi) ?dspix_mcr register?: ? included bit fields clr_txf and clr_rxf. chapter 21 lin controller (linflex) ?lintcsr? register: ? updated the reset value. chapter 22 flexcan ?control register (ctrl) field description? table: ? sorted correctly the bit fields. chapter 26 analog-to-digital converter (adc) ?threshold control? register: ? removed thrinv field. decode signals delay register (dsdr): ? update the description. ?max ad_clk frequency and related configuration settings? table: ? adeed a footnote. chapter 28 safety ?swt_cr? register: ? added the field ?key?. chapter 33 real time clock / autonomous periodic interrupt (rtc/api) ?rtcc? register: ? updated the apival description. table 433. document revision history (continued) date revision changes RM0017 revision history doc id 14629 rev 8 896/904 05-aug-2010 6 chapter 2 signal description 100 lqfp pinout and 144 lqfp pinout: ? removed alternate functions 208 mapbga pinout: ? osc32k_xtal at r9 changed to xtal32 ? osc32k_extal at t9 changed to extal32 chapter 3 clock description revised ?progressive cl ock switching? section. added ?progressive clock switching? scheme figure update definition of en_pll_sw bit filed on control register interrupt functionalities are not available on sxosc chapter 6 boot assist module (bam) added notes in the following section: download 64-bit password and password check download data execute code chapter 8 system integration unit lite (siul) clarified description of i/o pad function in overview section clarification: not all gpio pins have both input and output functions replaced parallel port register sections (pgpdo, pgpdi, and mpgdo), clarifying register function and bit ordering editorial updates throughout chapter chapter 16 ieee 1149.1 test acce ss port controller (jtagc) changed the code values for access _aux_tap_tcu and access_aux_tap_npc in the ?jtag instructions? table chapter 19 flash memory added a note in thr ?censorship password register? sections added information on rww-error during stall-while-write in the ?module configuration register (mcr)? table 433. document revision history (continued) date revision changes revision history RM0017 897/904 doc id 14629 rev 8 05-aug-2010 6 (continued) chapter 26 analog-to-digital converter (adc) updated following section: ?overview ? introduction ? injected channel conversion ? abort conversion ? adc ctu (cross triggering unit) ? presampling updated following registers: ?ceocfr ? cimr ?wtisr ?dmar ? psr ? ncmr ?jcmr ? cdr ? cwsel ?cwenr ?aworr inserted "ctu triggered conversion" in the conversion list of "functional description" section replaced generic ?syst em clock? with ?per ipheral set 3 clock? added information about ?adc_1? in the ?adc sampling and conversion timing? section moved cwsel, cwenr and aworr register within ?watchdog register? section inserted a footnote about offshi ft field in the ctr register changed the access type of dsdr in "read/write" updated the dsd description in the dsdr field description table chapter 27 cross triggering unit (ctu) replaced ?channel number value mapping? table with ?ctu-to-adc channel assignment? table removed ?control status register (ctu_csr )? because the interrupt feature is not implemented. cross triggering unit block diagram: trigger output control and output signals removed main features section: removed ?maskable interrupt generation whenever a trigger output is generated?. feature not implemented. 01-oct-2011 7 chapter throughout editorial changes and improvements (including reformatting of memory maps, register figures, and field descriptions to a consistent format). rearranged the chapter order. chapter preface added this chapter. chapter introduction changed the chapter title (was ?overview?, is ?introduction?). renamed ?introduction? to ?the spc560bx and spc560cx microcontroller family? and revised the section. renamed ?feature summary? to ?feature details?. moved the ?memory map? section to its own separate chapter. deleted the duplicate device-comparison tables. in the packages section, added a line for the 64-pin lqfp. table 433. document revision history (continued) date revision changes RM0017 revision history doc id 14629 rev 8 898/904 01-oct-2011 7 (continued) chapter memory map added this chapter (content previous ly contained in the overview chapter). changed ?test sector data flash array 0? to ?data test sector?. revised the numbers in the ?code flash sector? entries. changed ?flash shadow sector? to ?code flash shadow sector?. changed ?code flash array 0 test sector? to ?code flash test sector?. revised the numbers in the ?data flash array? entries. consolidated multiple adjacent reserved rows into single rows. chapter signal description added the 64-pin lqfp package figure. in the ?voltage supply pin descriptions? tabl e, added pin 6 to the entry for vss_hv in the 64-pin package. changed ?functional ports a, b, c, d, e, f, g, h? to ?functional ports?. in the ?functional ports? table, cha nged anp[0]?anp[15] to gpi[0]?gpi[15]. chapter safety migrated the chapter contents to the ?r egister protection? and ?swt? chapters. chapter microcontroller boot added this chapter. chapter clock description replaced the ?spc560bx and spc560cx syst em clock generation? figure with the version present in rev. 5 of the spc560bx and spc560cx reference manual. fast external crystal oscillator (fxosc) di gital interface section: changed the sentence from ?the fxosc digital interface controls the 4?40 mhz fast external crystal oscillator (fxosc).? to ?the fxosc digital interface controls the operation of the 4? 40 mhz fast external crystal oscillator (fxosc).? truth table of crystal oscillator table: replaced "me_gs.s_xosc" with ?me_xxx_mc[fxoscon]", replaced ?fxosc_ctl.oscbyp? with ?fxosc_ctl[oscbyp]? slow external crystal oscillator (sxosc) di gital interface section: changed the sentence from ?the sxosc digital interface controls the 32 khz slow external crystal oscillator (sxosc).? to ?the sxosc digital interface controls the operation of the 32 khz slow external crystal oscillator (sxosc).? sxosc truth table: replaced "s_osc? with ?oscon" renamed the figure title from ?rc oscillator control register (rc_ctl)? to ?firc oscillator cont rol register (firc_ctl)? renamed the table title from ?rc oscillator control regist er (rc_ctl) field descriptions? to ?firc oscillator control regist er (firc_ctl) field descriptions? in the fxosc_ctl figure, added footnotes to clarify the access to the oscbyp and i_osc fields. deleted the ?cmu register map? section. added notes for clarifying field access to the following registers ? fxosc_ctl ? sxosc_ctl ?cmu_csr table 433. document revision history (continued) date revision changes revision history RM0017 899/904 doc id 14629 rev 8 01-oct-2011 7 (continued) revised the sxosc _ctl section. in the sirc ?functional description? section, revised the information of sirc output frequency trimming. in the firc ?functional description? section, revised the information of firc output frequency trimming. in the firc_ctl section, del eted the fircon_stdby field. revised the reset values in the fmpll cr. revised the sirc_ctl[sirctrim] field description. revised the firc_ctl[firctrim] field description. changed standby0 to standby. in the fmpll features, changed ? sscg? to ?frequency modulation?. in the fmpll functional description, a dded the ?fmpll lookup table? table. in the cmu introduction, changed ?towards the mode? to ?towards the mc_me?. in the cmu introduction, deleted the ?cmu block diagram? figure. in the cmu introduction section, changed ?clock management unit? to mc_cgm. chapter mode entry module changed ?warning? to ?caution?. changed halt0 to halt. changed stop0 to stop. changed standby0 to standby. added the ?peripheral control registers by peripheral? table. in the me_ RM0017 revision history doc id 14629 rev 8 900/904 01-oct-2011 7 (continued) changed wkup to wkpu to match the official module abbreviation. in the overview section, replaced the wakeup vector mapping information with a table. in the overview section, changed the entries in ?interrupt vector 2? so that the footnote ?not available in 100-pin lqfp? is associated only with wkpu[19]. in the ?nmi management? section, changed ?thi s register is a clear-by-write-1 register type, preventing inadvertent overwriting of other flags in the same register.? to ?the nif and novf fields in this register are cl eared by writing a ?1? to them; this prevents inadvertent overwriting of other flags in the register.? in the ?external interrupt management? sectio n, changed ?this register is a clear-by- write-1 register type, preventing inadvertent overwriting of other flags in the same register.? to ?the bits in the wisr[eif] fiel d are cleared by writing a ?1? to them; this prevents inadvertent overwriting of other flags in the register.? in the nsr, changed nif to nif0 and novf to novf0. in the ncr, changed all field names to contain a trailing ?0? (example: nlock0). in the ?wkpu block diagram? figure, deleted single 0s. in the ?memory map? section, changed ?if supported and enabled by the soc? to ?if sscm_error[rae] is enabled?. in the wifer section, deleted ?the number of wakeups ... 1 and 18?. in the ?wkpu memory map? table, added the module base address. in the ncr[nwre0] field description, ad ded a note about the proper sequence for enabling the nmi. chapter real time clock / autonomous periodic interrupt replaced ipg_clk wi th ?system clock?. changed ?32 khz? to ?32 khz?. revised the rtcc[frzen] field description. added the following note to the rtcc[rtcval] field description: ?rtcval = 0 does not generate an interrupt.?. in the ?rtc functional description? section, deleted ?the rtcc[rtcval] field may only be updated when the rtcc[cnten] bit is cleared to disable the counter?. in the ?rtc/api register map? tabl e, added the module base address. chapter can sampler deleted the duplicate register map. in the ?can sampler memory map? table, added the module base address. chapter e200z0h core in the ?e200z0h block diagram? figure, added a box around the core elements. chapter interrupt controller revised ?intc priority select registers? a nd ?intc priority select register address offsets? table to show that ?intc_psr 208_210? contains pri208, pri209, and pri210 fields. revised the intc_iackr section to illustrate the register?s dependence on intc_mcr[vtes] more clearly. in the intc_eoir register figure, added ?see text? to the w row. in the ?interrupt vector table? table, changed ?wkup? to ?wkpu?. in the ?intc memory map? table, added the module base address. table 433. document revision history (continued) date revision changes revision history RM0017 901/904 doc id 14629 rev 8 01-oct-2011 7 (continued) chapter memory protection unit in the ?mpu block diagram? figure, changed the text at the top left to ?platform? and removed ?z0hn1 or?. revised the introduction section. changed ahb to xbar. deleted references to ips and r eplaced with ?peripheral? as needed. in the ?mpu access evaluation macro? figure, changed ?ahb_ap? to ?system bus address phase?. in the ?mpu memory map? table, added the module base address. chapter system integration unit lite changed ?warning? to ?caution?. in the register figures, changed ?access: none? to the corresponding actual level of access. in the midr1[pkg] field description: ? added ?any values not explicitly specified are reserved?. ? added the 64-pin lqfp setting. revised the description of the partnum fiel d in midr1 and midr2 to clarify that the field is split between the two registers. in the pcrx section, revised the wps and wpe field descriptions to indicate the correct functionality. in the ?external interrupts? section, changed ?t his register is a clear-by-write-1 register type, preventing inadvertent overwriting of other flags in the same register.? to ?the bits in the isr[eif] field are cleared by wr iting a ?1? to them; this prevents inadvertent overwriting of other flags in the register.? revised the ?midr2 field descriptions? table to show how to calculate total flash memory size. in the ?midr2 field description s? table, deleted the entr y for fr (not implemented). in the ?siul memory map? table, added the module base address. chapter inter-integrated ci rcuit bus controller module in the ibcr section, changed ?ms/sl ? to ?mssl? and ? tx/rx ? to ?txrx? to ensure compliance with field name convention. in the ibcr figure, changed bit 7 (was ibdoze, is reserved). in the ibsr figure, changed the ibal and ibif fields to w1c. in the ?interrupt description? section, changed ?(tcf bit set - to be checked)? to ?(a byte transfer interrupt occurs whenever the tcf bi t changes from 0 to 1, that is, transfer under progress to trans fer complete state)?. revised the last paragraph of the overview section. in the ibcr[mdis] field description, added ?s tatus register bits (ibsr) are not valid when module is disabled?. in the ibsr[rxak] field descrip tion, added ?this bit is valid only after transfer is complete?. in the ?interrupt description? section, re vised the entry for ?byte transfer condition?. in the ?initialization sequence? sect ion, changed ibcr[ibdis] to ibcr[mdis]. revised the ?post-transfer software response? section. added the ?transmit/receive sequence? section. in the ?generation of stop? section, in the code sample, changed ?bit 1? to ?bit 5?. in the ?i2c memory map? table, added the module base address. table 433. document revision history (continued) date revision changes RM0017 revision history doc id 14629 rev 8 902/904 01-oct-2011 7 (continued) chapter lin controller in the ?ifer field descriptions? table, switched ?activated? and ?deactivated? in order to match with ?ifer[fact] configuration? table. deleted the ?register map and reset values? section (duplicate content). in the ?uart mode? section, in the ?9-bit frames? subsection, changed ?sum of the 7 data bits? to ?sum of the 8 data bits?. in the lincr1[bf] field description, changed ?this bit is reserved? to ?this bit is reserved and always reads 1?. changed ?kbps? to ?kbit/s?. chapter flexcan in the ?flexcan memory map? table, added the module base addresses. chapter deserial serial peripheral interface in the ?continuous selection format? section, added a note about filling the tx fifo. added new rules to the ?continuous serial communications clock? section. in the ?dspi memory map? table, added the module base addresses. chapter timers added this chapter (incorporates conten t from stm, emios, and pit chapters). chapter analog-to-digital converter updated mcr[wlside] bit description. updated cdr register. replaced adcdig with adc, rewriting content as necessary. in the pdedr[pded] field description, added ?the delay is to allow time for the adc power supply to settle before commencing conversions.?. in the ?threshold registers? introduction se ction, deleted the sent ence ?the inverter bit and the mask bit for mask the interrupt are stored in the trc registers.?. deleted the ?bit access descriptions? table. in the cimr section, deleted the duplicate cimr1 figure. chapter cross triggering unit removed remaining references to ctu_csr (not implemented on this chip). in the ?ctu memory map? table: ? changed the end address of the rese rved space (was 0x002c, is 0x002f). ? added the module base address. chapter flash memory replaced the entire chapter. chapter register protection added this chapter. chapter software watchdog timer added this chapter. table 433. document revision history (continued) date revision changes revision history RM0017 903/904 doc id 14629 rev 8 01-oct-2011 7 (continued) chapter error correction status module revised the introduction section. revised the features section. revised the mudcr section to show completely that bit 1 is reserved. in the register descriptions, revised the names as needed to match the names in the memory map. in the premr section, added text on where to find bus master ids. aligned register names in the descriptions and the memory map. deleted the second paragraph in the introduction section. deleted the last bullet (about spp_ips_r eg_protection) in the features section. in the preat field descriptions, changed ?amba-ahb? to ?xbar?. renamed the ?spp_ips_reg_protection? section to ?register protection? and revised the section. revised the ?ecc registers? section. in the ?ecsm memory map? table, added the module base address. chapter ieee 1149.1 test access port controller in the features section, changed ?3 test dat a registers? to ?2 test data registers?. in the ?sample instruction? section, added information about pad status. in the ?sample/preload instruction? sect ion, added information about pad status. chapter nexus development interface added the ?npc_hndshk module? section. changed halt0 to halt. changed stop0 to stop. changed standby0 to standby. replaced the ?ndi configuration options? table. chapter boot assist module deleted this chapter (relevant content is no w represented by the ?microcontroller boot? chapter). chapter enhanced modular io subsystem deleted this chapter (relevant content is now represented by th e ?timers? chapter). chapter system status and configuration module deleted this chapter (relevant content is now represented by the ?microcontroller boot? chapter). appendix: register protection deleted this appendix (relevant content is now represented by the ?register protection? chapter). appendix: register map changed halt0 to halt. changed stop0 to stop. changed standby0 to standby. extended ?priority select register? to intc_psr208_210. removed ctu_csr (not implemented on this microcontroller). 17-sep-2013 8 updated disclaimer table 433. document revision history (continued) date revision changes RM0017 doc id 14629 rev 8 904/904 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particul ar purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ? automotive, automotive safe ty or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com |
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